spcr.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. /*
  2. * Copyright (c) 2012, Intel Corporation
  3. * Copyright (c) 2015, Red Hat, Inc.
  4. * Copyright (c) 2015, 2016 Linaro Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #define pr_fmt(fmt) "ACPI: SPCR: " fmt
  12. #include <linux/acpi.h>
  13. #include <linux/console.h>
  14. #include <linux/kernel.h>
  15. #include <linux/serial_core.h>
  16. /*
  17. * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
  18. * occasionally getting stuck as 1. To avoid the potential for a hang, check
  19. * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
  20. * implementations, so only do so if an affected platform is detected in
  21. * acpi_parse_spcr().
  22. */
  23. bool qdf2400_e44_present;
  24. EXPORT_SYMBOL(qdf2400_e44_present);
  25. /*
  26. * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
  27. * Detect them by examining the OEM fields in the SPCR header, similiar to PCI
  28. * quirk detection in pci_mcfg.c.
  29. */
  30. static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
  31. {
  32. if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
  33. return false;
  34. if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
  35. return true;
  36. if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
  37. h->oem_revision == 1)
  38. return true;
  39. return false;
  40. }
  41. /*
  42. * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
  43. * register aligned to 32-bit. In addition, the BIOS also encoded the
  44. * access width to be 8 bits. This function detects this errata condition.
  45. */
  46. static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
  47. {
  48. bool xgene_8250 = false;
  49. if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
  50. return false;
  51. if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
  52. memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE))
  53. return false;
  54. if (!memcmp(tb->header.oem_table_id, "XGENESPC",
  55. ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
  56. xgene_8250 = true;
  57. if (!memcmp(tb->header.oem_table_id, "ProLiant",
  58. ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
  59. xgene_8250 = true;
  60. return xgene_8250;
  61. }
  62. /**
  63. * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
  64. *
  65. * @enable_earlycon: set up earlycon for the console specified by the table
  66. * @enable_console: setup the console specified by the table.
  67. *
  68. * For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
  69. * defined to parse ACPI SPCR table. As a result of the parsing preferred
  70. * console is registered and if @enable_earlycon is true, earlycon is set up.
  71. * If @enable_console is true the system console is also configured.
  72. *
  73. * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
  74. * from arch initialization code as soon as the DT/ACPI decision is made.
  75. *
  76. */
  77. int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
  78. {
  79. static char opts[64];
  80. struct acpi_table_spcr *table;
  81. acpi_status status;
  82. char *uart;
  83. char *iotype;
  84. int baud_rate;
  85. int err;
  86. if (acpi_disabled)
  87. return -ENODEV;
  88. status = acpi_get_table(ACPI_SIG_SPCR, 0,
  89. (struct acpi_table_header **)&table);
  90. if (ACPI_FAILURE(status))
  91. return -ENOENT;
  92. if (table->header.revision < 2)
  93. pr_info("SPCR table version %d\n", table->header.revision);
  94. if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
  95. switch (ACPI_ACCESS_BIT_WIDTH((
  96. table->serial_port.access_width))) {
  97. default:
  98. pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n");
  99. /* fall through */
  100. case 8:
  101. iotype = "mmio";
  102. break;
  103. case 16:
  104. iotype = "mmio16";
  105. break;
  106. case 32:
  107. iotype = "mmio32";
  108. break;
  109. }
  110. } else
  111. iotype = "io";
  112. switch (table->interface_type) {
  113. case ACPI_DBG2_ARM_SBSA_32BIT:
  114. iotype = "mmio32";
  115. /* fall through */
  116. case ACPI_DBG2_ARM_PL011:
  117. case ACPI_DBG2_ARM_SBSA_GENERIC:
  118. case ACPI_DBG2_BCM2835:
  119. uart = "pl011";
  120. break;
  121. case ACPI_DBG2_16550_COMPATIBLE:
  122. case ACPI_DBG2_16550_SUBSET:
  123. uart = "uart";
  124. break;
  125. default:
  126. err = -ENOENT;
  127. goto done;
  128. }
  129. switch (table->baud_rate) {
  130. case 0:
  131. /*
  132. * SPCR 1.04 defines 0 as a preconfigured state of UART.
  133. * Assume firmware or bootloader configures console correctly.
  134. */
  135. baud_rate = 0;
  136. break;
  137. case 3:
  138. baud_rate = 9600;
  139. break;
  140. case 4:
  141. baud_rate = 19200;
  142. break;
  143. case 6:
  144. baud_rate = 57600;
  145. break;
  146. case 7:
  147. baud_rate = 115200;
  148. break;
  149. default:
  150. err = -ENOENT;
  151. goto done;
  152. }
  153. /*
  154. * If the E44 erratum is required, then we need to tell the pl011
  155. * driver to implement the work-around.
  156. *
  157. * The global variable is used by the probe function when it
  158. * creates the UARTs, whether or not they're used as a console.
  159. *
  160. * If the user specifies "traditional" earlycon, the qdf2400_e44
  161. * console name matches the EARLYCON_DECLARE() statement, and
  162. * SPCR is not used. Parameter "earlycon" is false.
  163. *
  164. * If the user specifies "SPCR" earlycon, then we need to update
  165. * the console name so that it also says "qdf2400_e44". Parameter
  166. * "earlycon" is true.
  167. *
  168. * For consistency, if we change the console name, then we do it
  169. * for everyone, not just earlycon.
  170. */
  171. if (qdf2400_erratum_44_present(&table->header)) {
  172. qdf2400_e44_present = true;
  173. if (enable_earlycon)
  174. uart = "qdf2400_e44";
  175. }
  176. if (xgene_8250_erratum_present(table)) {
  177. iotype = "mmio32";
  178. /* for xgene v1 and v2 we don't know the clock rate of the
  179. * UART so don't attempt to change to the baud rate state
  180. * in the table because driver cannot calculate the dividers
  181. */
  182. baud_rate = 0;
  183. }
  184. if (!baud_rate) {
  185. snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
  186. table->serial_port.address);
  187. } else {
  188. snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
  189. table->serial_port.address, baud_rate);
  190. }
  191. pr_info("console: %s\n", opts);
  192. if (enable_earlycon)
  193. setup_earlycon(opts);
  194. if (enable_console)
  195. err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
  196. else
  197. err = 0;
  198. done:
  199. acpi_put_table((struct acpi_table_header *)table);
  200. return err;
  201. }