rtc-sa1100.c 10 KB

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  1. /*
  2. * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
  3. *
  4. * Copyright (c) 2000 Nils Faerber
  5. *
  6. * Based on rtc.c by Paul Gortmaker
  7. *
  8. * Original Driver by Nils Faerber <nils@kernelconcepts.de>
  9. *
  10. * Modifications from:
  11. * CIH <cih@coventive.com>
  12. * Nicolas Pitre <nico@fluxnic.net>
  13. * Andrew Christian <andrew.christian@hp.com>
  14. *
  15. * Converted to the RTC subsystem and Driver Model
  16. * by Richard Purdie <rpurdie@rpsys.net>
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License
  20. * as published by the Free Software Foundation; either version
  21. * 2 of the License, or (at your option) any later version.
  22. */
  23. #include <linux/platform_device.h>
  24. #include <linux/module.h>
  25. #include <linux/clk.h>
  26. #include <linux/rtc.h>
  27. #include <linux/init.h>
  28. #include <linux/fs.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/slab.h>
  31. #include <linux/string.h>
  32. #include <linux/of.h>
  33. #include <linux/pm.h>
  34. #include <linux/bitops.h>
  35. #include <linux/io.h>
  36. #define RTSR_HZE BIT(3) /* HZ interrupt enable */
  37. #define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */
  38. #define RTSR_HZ BIT(1) /* HZ rising-edge detected */
  39. #define RTSR_AL BIT(0) /* RTC alarm detected */
  40. #include "rtc-sa1100.h"
  41. #define RTC_DEF_DIVIDER (32768 - 1)
  42. #define RTC_DEF_TRIM 0
  43. #define RTC_FREQ 1024
  44. static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
  45. {
  46. struct sa1100_rtc *info = dev_get_drvdata(dev_id);
  47. struct rtc_device *rtc = info->rtc;
  48. unsigned int rtsr;
  49. unsigned long events = 0;
  50. spin_lock(&info->lock);
  51. rtsr = readl_relaxed(info->rtsr);
  52. /* clear interrupt sources */
  53. writel_relaxed(0, info->rtsr);
  54. /* Fix for a nasty initialization problem the in SA11xx RTSR register.
  55. * See also the comments in sa1100_rtc_probe(). */
  56. if (rtsr & (RTSR_ALE | RTSR_HZE)) {
  57. /* This is the original code, before there was the if test
  58. * above. This code does not clear interrupts that were not
  59. * enabled. */
  60. writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
  61. } else {
  62. /* For some reason, it is possible to enter this routine
  63. * without interruptions enabled, it has been tested with
  64. * several units (Bug in SA11xx chip?).
  65. *
  66. * This situation leads to an infinite "loop" of interrupt
  67. * routine calling and as a result the processor seems to
  68. * lock on its first call to open(). */
  69. writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
  70. }
  71. /* clear alarm interrupt if it has occurred */
  72. if (rtsr & RTSR_AL)
  73. rtsr &= ~RTSR_ALE;
  74. writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
  75. /* update irq data & counter */
  76. if (rtsr & RTSR_AL)
  77. events |= RTC_AF | RTC_IRQF;
  78. if (rtsr & RTSR_HZ)
  79. events |= RTC_UF | RTC_IRQF;
  80. rtc_update_irq(rtc, 1, events);
  81. spin_unlock(&info->lock);
  82. return IRQ_HANDLED;
  83. }
  84. static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  85. {
  86. u32 rtsr;
  87. struct sa1100_rtc *info = dev_get_drvdata(dev);
  88. spin_lock_irq(&info->lock);
  89. rtsr = readl_relaxed(info->rtsr);
  90. if (enabled)
  91. rtsr |= RTSR_ALE;
  92. else
  93. rtsr &= ~RTSR_ALE;
  94. writel_relaxed(rtsr, info->rtsr);
  95. spin_unlock_irq(&info->lock);
  96. return 0;
  97. }
  98. static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
  99. {
  100. struct sa1100_rtc *info = dev_get_drvdata(dev);
  101. rtc_time_to_tm(readl_relaxed(info->rcnr), tm);
  102. return 0;
  103. }
  104. static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
  105. {
  106. struct sa1100_rtc *info = dev_get_drvdata(dev);
  107. unsigned long time;
  108. int ret;
  109. ret = rtc_tm_to_time(tm, &time);
  110. if (ret == 0)
  111. writel_relaxed(time, info->rcnr);
  112. return ret;
  113. }
  114. static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  115. {
  116. u32 rtsr;
  117. struct sa1100_rtc *info = dev_get_drvdata(dev);
  118. rtsr = readl_relaxed(info->rtsr);
  119. alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
  120. alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
  121. return 0;
  122. }
  123. static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  124. {
  125. struct sa1100_rtc *info = dev_get_drvdata(dev);
  126. unsigned long time;
  127. int ret;
  128. spin_lock_irq(&info->lock);
  129. ret = rtc_tm_to_time(&alrm->time, &time);
  130. if (ret != 0)
  131. goto out;
  132. writel_relaxed(readl_relaxed(info->rtsr) &
  133. (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr);
  134. writel_relaxed(time, info->rtar);
  135. if (alrm->enabled)
  136. writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
  137. else
  138. writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
  139. out:
  140. spin_unlock_irq(&info->lock);
  141. return ret;
  142. }
  143. static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
  144. {
  145. struct sa1100_rtc *info = dev_get_drvdata(dev);
  146. seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr));
  147. seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr));
  148. return 0;
  149. }
  150. static const struct rtc_class_ops sa1100_rtc_ops = {
  151. .read_time = sa1100_rtc_read_time,
  152. .set_time = sa1100_rtc_set_time,
  153. .read_alarm = sa1100_rtc_read_alarm,
  154. .set_alarm = sa1100_rtc_set_alarm,
  155. .proc = sa1100_rtc_proc,
  156. .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
  157. };
  158. int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info)
  159. {
  160. int ret;
  161. spin_lock_init(&info->lock);
  162. info->clk = devm_clk_get(&pdev->dev, NULL);
  163. if (IS_ERR(info->clk)) {
  164. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  165. return PTR_ERR(info->clk);
  166. }
  167. ret = clk_prepare_enable(info->clk);
  168. if (ret)
  169. return ret;
  170. /*
  171. * According to the manual we should be able to let RTTR be zero
  172. * and then a default diviser for a 32.768KHz clock is used.
  173. * Apparently this doesn't work, at least for my SA1110 rev 5.
  174. * If the clock divider is uninitialized then reset it to the
  175. * default value to get the 1Hz clock.
  176. */
  177. if (readl_relaxed(info->rttr) == 0) {
  178. writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
  179. dev_warn(&pdev->dev, "warning: "
  180. "initializing default clock divider/trim value\n");
  181. /* The current RTC value probably doesn't make sense either */
  182. writel_relaxed(0, info->rcnr);
  183. }
  184. info->rtc->ops = &sa1100_rtc_ops;
  185. info->rtc->max_user_freq = RTC_FREQ;
  186. ret = rtc_register_device(info->rtc);
  187. if (ret) {
  188. clk_disable_unprepare(info->clk);
  189. return ret;
  190. }
  191. /* Fix for a nasty initialization problem the in SA11xx RTSR register.
  192. * See also the comments in sa1100_rtc_interrupt().
  193. *
  194. * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
  195. * interrupt pending, even though interrupts were never enabled.
  196. * In this case, this bit it must be reset before enabling
  197. * interruptions to avoid a nonexistent interrupt to occur.
  198. *
  199. * In principle, the same problem would apply to bit 0, although it has
  200. * never been observed to happen.
  201. *
  202. * This issue is addressed both here and in sa1100_rtc_interrupt().
  203. * If the issue is not addressed here, in the times when the processor
  204. * wakes up with the bit set there will be one spurious interrupt.
  205. *
  206. * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
  207. * safe side, once the condition that lead to this strange
  208. * initialization is unknown and could in principle happen during
  209. * normal processing.
  210. *
  211. * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
  212. * the corresponding bits in RTSR. */
  213. writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
  214. return 0;
  215. }
  216. EXPORT_SYMBOL_GPL(sa1100_rtc_init);
  217. static int sa1100_rtc_probe(struct platform_device *pdev)
  218. {
  219. struct sa1100_rtc *info;
  220. struct resource *iores;
  221. void __iomem *base;
  222. int irq_1hz, irq_alarm;
  223. int ret;
  224. irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
  225. irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
  226. if (irq_1hz < 0 || irq_alarm < 0)
  227. return -ENODEV;
  228. info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL);
  229. if (!info)
  230. return -ENOMEM;
  231. info->irq_1hz = irq_1hz;
  232. info->irq_alarm = irq_alarm;
  233. info->rtc = devm_rtc_allocate_device(&pdev->dev);
  234. if (IS_ERR(info->rtc))
  235. return PTR_ERR(info->rtc);
  236. ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0,
  237. "rtc 1Hz", &pdev->dev);
  238. if (ret) {
  239. dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz);
  240. return ret;
  241. }
  242. ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0,
  243. "rtc Alrm", &pdev->dev);
  244. if (ret) {
  245. dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm);
  246. return ret;
  247. }
  248. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  249. base = devm_ioremap_resource(&pdev->dev, iores);
  250. if (IS_ERR(base))
  251. return PTR_ERR(base);
  252. if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
  253. of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
  254. info->rcnr = base + 0x04;
  255. info->rtsr = base + 0x10;
  256. info->rtar = base + 0x00;
  257. info->rttr = base + 0x08;
  258. } else {
  259. info->rcnr = base + 0x0;
  260. info->rtsr = base + 0x8;
  261. info->rtar = base + 0x4;
  262. info->rttr = base + 0xc;
  263. }
  264. platform_set_drvdata(pdev, info);
  265. device_init_wakeup(&pdev->dev, 1);
  266. return sa1100_rtc_init(pdev, info);
  267. }
  268. static int sa1100_rtc_remove(struct platform_device *pdev)
  269. {
  270. struct sa1100_rtc *info = platform_get_drvdata(pdev);
  271. if (info) {
  272. spin_lock_irq(&info->lock);
  273. writel_relaxed(0, info->rtsr);
  274. spin_unlock_irq(&info->lock);
  275. clk_disable_unprepare(info->clk);
  276. }
  277. return 0;
  278. }
  279. #ifdef CONFIG_PM_SLEEP
  280. static int sa1100_rtc_suspend(struct device *dev)
  281. {
  282. struct sa1100_rtc *info = dev_get_drvdata(dev);
  283. if (device_may_wakeup(dev))
  284. enable_irq_wake(info->irq_alarm);
  285. return 0;
  286. }
  287. static int sa1100_rtc_resume(struct device *dev)
  288. {
  289. struct sa1100_rtc *info = dev_get_drvdata(dev);
  290. if (device_may_wakeup(dev))
  291. disable_irq_wake(info->irq_alarm);
  292. return 0;
  293. }
  294. #endif
  295. static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend,
  296. sa1100_rtc_resume);
  297. #ifdef CONFIG_OF
  298. static const struct of_device_id sa1100_rtc_dt_ids[] = {
  299. { .compatible = "mrvl,sa1100-rtc", },
  300. { .compatible = "mrvl,mmp-rtc", },
  301. {}
  302. };
  303. MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
  304. #endif
  305. static struct platform_driver sa1100_rtc_driver = {
  306. .probe = sa1100_rtc_probe,
  307. .remove = sa1100_rtc_remove,
  308. .driver = {
  309. .name = "sa1100-rtc",
  310. .pm = &sa1100_rtc_pm_ops,
  311. .of_match_table = of_match_ptr(sa1100_rtc_dt_ids),
  312. },
  313. };
  314. module_platform_driver(sa1100_rtc_driver);
  315. MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
  316. MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
  317. MODULE_LICENSE("GPL");
  318. MODULE_ALIAS("platform:sa1100-rtc");