tegra186-mc.h 3.0 KB

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  1. #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
  2. #define DT_BINDINGS_MEMORY_TEGRA186_MC_H
  3. /* special clients */
  4. #define TEGRA186_SID_INVALID 0x00
  5. #define TEGRA186_SID_PASSTHROUGH 0x7f
  6. /* host1x clients */
  7. #define TEGRA186_SID_HOST1X 0x01
  8. #define TEGRA186_SID_CSI 0x02
  9. #define TEGRA186_SID_VIC 0x03
  10. #define TEGRA186_SID_VI 0x04
  11. #define TEGRA186_SID_ISP 0x05
  12. #define TEGRA186_SID_NVDEC 0x06
  13. #define TEGRA186_SID_NVENC 0x07
  14. #define TEGRA186_SID_NVJPG 0x08
  15. #define TEGRA186_SID_NVDISPLAY 0x09
  16. #define TEGRA186_SID_TSEC 0x0a
  17. #define TEGRA186_SID_TSECB 0x0b
  18. #define TEGRA186_SID_SE 0x0c
  19. #define TEGRA186_SID_SE1 0x0d
  20. #define TEGRA186_SID_SE2 0x0e
  21. #define TEGRA186_SID_SE3 0x0f
  22. /* GPU clients */
  23. #define TEGRA186_SID_GPU 0x10
  24. /* other SoC clients */
  25. #define TEGRA186_SID_AFI 0x11
  26. #define TEGRA186_SID_HDA 0x12
  27. #define TEGRA186_SID_ETR 0x13
  28. #define TEGRA186_SID_EQOS 0x14
  29. #define TEGRA186_SID_UFSHC 0x15
  30. #define TEGRA186_SID_AON 0x16
  31. #define TEGRA186_SID_SDMMC4 0x17
  32. #define TEGRA186_SID_SDMMC3 0x18
  33. #define TEGRA186_SID_SDMMC2 0x19
  34. #define TEGRA186_SID_SDMMC1 0x1a
  35. #define TEGRA186_SID_XUSB_HOST 0x1b
  36. #define TEGRA186_SID_XUSB_DEV 0x1c
  37. #define TEGRA186_SID_SATA 0x1d
  38. #define TEGRA186_SID_APE 0x1e
  39. #define TEGRA186_SID_SCE 0x1f
  40. /* GPC DMA clients */
  41. #define TEGRA186_SID_GPCDMA_0 0x20
  42. #define TEGRA186_SID_GPCDMA_1 0x21
  43. #define TEGRA186_SID_GPCDMA_2 0x22
  44. #define TEGRA186_SID_GPCDMA_3 0x23
  45. #define TEGRA186_SID_GPCDMA_4 0x24
  46. #define TEGRA186_SID_GPCDMA_5 0x25
  47. #define TEGRA186_SID_GPCDMA_6 0x26
  48. #define TEGRA186_SID_GPCDMA_7 0x27
  49. /* APE DMA clients */
  50. #define TEGRA186_SID_APE_1 0x28
  51. #define TEGRA186_SID_APE_2 0x29
  52. /* camera RTCPU */
  53. #define TEGRA186_SID_RCE 0x2a
  54. /* camera RTCPU on host1x address space */
  55. #define TEGRA186_SID_RCE_1X 0x2b
  56. /* APE DMA clients */
  57. #define TEGRA186_SID_APE_3 0x2c
  58. /* camera RTCPU running on APE */
  59. #define TEGRA186_SID_APE_CAM 0x2d
  60. #define TEGRA186_SID_APE_CAM_1X 0x2e
  61. /*
  62. * The BPMP has its SID value hardcoded in the firmware. Changing it requires
  63. * considerable effort.
  64. */
  65. #define TEGRA186_SID_BPMP 0x32
  66. /* for SMMU tests */
  67. #define TEGRA186_SID_SMMU_TEST 0x33
  68. /* host1x virtualization channels */
  69. #define TEGRA186_SID_HOST1X_CTX0 0x38
  70. #define TEGRA186_SID_HOST1X_CTX1 0x39
  71. #define TEGRA186_SID_HOST1X_CTX2 0x3a
  72. #define TEGRA186_SID_HOST1X_CTX3 0x3b
  73. #define TEGRA186_SID_HOST1X_CTX4 0x3c
  74. #define TEGRA186_SID_HOST1X_CTX5 0x3d
  75. #define TEGRA186_SID_HOST1X_CTX6 0x3e
  76. #define TEGRA186_SID_HOST1X_CTX7 0x3f
  77. /* host1x command buffers */
  78. #define TEGRA186_SID_HOST1X_VM0 0x40
  79. #define TEGRA186_SID_HOST1X_VM1 0x41
  80. #define TEGRA186_SID_HOST1X_VM2 0x42
  81. #define TEGRA186_SID_HOST1X_VM3 0x43
  82. #define TEGRA186_SID_HOST1X_VM4 0x44
  83. #define TEGRA186_SID_HOST1X_VM5 0x45
  84. #define TEGRA186_SID_HOST1X_VM6 0x46
  85. #define TEGRA186_SID_HOST1X_VM7 0x47
  86. /* SE data buffers */
  87. #define TEGRA186_SID_SE_VM0 0x48
  88. #define TEGRA186_SID_SE_VM1 0x49
  89. #define TEGRA186_SID_SE_VM2 0x4a
  90. #define TEGRA186_SID_SE_VM3 0x4b
  91. #define TEGRA186_SID_SE_VM4 0x4c
  92. #define TEGRA186_SID_SE_VM5 0x4d
  93. #define TEGRA186_SID_SE_VM6 0x4e
  94. #define TEGRA186_SID_SE_VM7 0x4f
  95. #endif