dsp_spos_scb_lib.c 48 KB

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  1. /*
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. *
  17. */
  18. /*
  19. * 2002-07 Benny Sjostrand benny@hostmobility.com
  20. */
  21. #include <linux/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include "cs46xx.h"
  31. #include "cs46xx_lib.h"
  32. #include "dsp_spos.h"
  33. struct proc_scb_info {
  34. struct dsp_scb_descriptor * scb_desc;
  35. struct snd_cs46xx *chip;
  36. };
  37. static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
  38. {
  39. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  40. int symbol_index = (int)(symbol - ins->symbol_table.symbols);
  41. if (snd_BUG_ON(ins->symbol_table.nsymbols <= 0))
  42. return;
  43. if (snd_BUG_ON(symbol_index < 0 ||
  44. symbol_index >= ins->symbol_table.nsymbols))
  45. return;
  46. ins->symbol_table.symbols[symbol_index].deleted = 1;
  47. if (symbol_index < ins->symbol_table.highest_frag_index) {
  48. ins->symbol_table.highest_frag_index = symbol_index;
  49. }
  50. if (symbol_index == ins->symbol_table.nsymbols - 1)
  51. ins->symbol_table.nsymbols --;
  52. if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
  53. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  54. }
  55. }
  56. #ifdef CONFIG_SND_PROC_FS
  57. static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
  58. struct snd_info_buffer *buffer)
  59. {
  60. struct proc_scb_info * scb_info = entry->private_data;
  61. struct dsp_scb_descriptor * scb = scb_info->scb_desc;
  62. struct snd_cs46xx *chip = scb_info->chip;
  63. int j,col;
  64. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  65. mutex_lock(&chip->spos_mutex);
  66. snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
  67. for (col = 0,j = 0;j < 0x10; j++,col++) {
  68. if (col == 4) {
  69. snd_iprintf(buffer,"\n");
  70. col = 0;
  71. }
  72. snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
  73. }
  74. snd_iprintf(buffer,"\n");
  75. if (scb->parent_scb_ptr != NULL) {
  76. snd_iprintf(buffer,"parent [%s:%04x] ",
  77. scb->parent_scb_ptr->scb_name,
  78. scb->parent_scb_ptr->address);
  79. } else snd_iprintf(buffer,"parent [none] ");
  80. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  81. scb->sub_list_ptr->scb_name,
  82. scb->sub_list_ptr->address,
  83. scb->next_scb_ptr->scb_name,
  84. scb->next_scb_ptr->address,
  85. scb->task_entry->symbol_name,
  86. scb->task_entry->address);
  87. snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
  88. mutex_unlock(&chip->spos_mutex);
  89. }
  90. #endif
  91. static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  92. {
  93. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  94. if ( scb->parent_scb_ptr ) {
  95. /* unlink parent SCB */
  96. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr != scb &&
  97. scb->parent_scb_ptr->next_scb_ptr != scb))
  98. return;
  99. if (scb->parent_scb_ptr->sub_list_ptr == scb) {
  100. if (scb->next_scb_ptr == ins->the_null_scb) {
  101. /* last and only node in parent sublist */
  102. scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
  103. if (scb->sub_list_ptr != ins->the_null_scb) {
  104. scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  105. }
  106. scb->sub_list_ptr = ins->the_null_scb;
  107. } else {
  108. /* first node in parent sublist */
  109. scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
  110. if (scb->next_scb_ptr != ins->the_null_scb) {
  111. /* update next node parent ptr. */
  112. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  113. }
  114. scb->next_scb_ptr = ins->the_null_scb;
  115. }
  116. } else {
  117. scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
  118. if (scb->next_scb_ptr != ins->the_null_scb) {
  119. /* update next node parent ptr. */
  120. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  121. }
  122. scb->next_scb_ptr = ins->the_null_scb;
  123. }
  124. /* update parent first entry in DSP RAM */
  125. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  126. /* then update entry in DSP RAM */
  127. cs46xx_dsp_spos_update_scb(chip,scb);
  128. scb->parent_scb_ptr = NULL;
  129. }
  130. }
  131. static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
  132. int dword_count)
  133. {
  134. void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
  135. int i;
  136. for (i = 0; i < dword_count ; ++i ) {
  137. writel(0, dst);
  138. dst += 4;
  139. }
  140. }
  141. void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  142. {
  143. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  144. unsigned long flags;
  145. /* check integrety */
  146. if (snd_BUG_ON(scb->index < 0 ||
  147. scb->index >= ins->nscb ||
  148. (ins->scbs + scb->index) != scb))
  149. return;
  150. #if 0
  151. /* can't remove a SCB with childs before
  152. removing childs first */
  153. if (snd_BUG_ON(scb->sub_list_ptr != ins->the_null_scb ||
  154. scb->next_scb_ptr != ins->the_null_scb))
  155. goto _end;
  156. #endif
  157. spin_lock_irqsave(&chip->reg_lock, flags);
  158. _dsp_unlink_scb (chip,scb);
  159. spin_unlock_irqrestore(&chip->reg_lock, flags);
  160. cs46xx_dsp_proc_free_scb_desc(scb);
  161. if (snd_BUG_ON(!scb->scb_symbol))
  162. return;
  163. remove_symbol (chip,scb->scb_symbol);
  164. ins->scbs[scb->index].deleted = 1;
  165. #ifdef CONFIG_PM_SLEEP
  166. kfree(ins->scbs[scb->index].data);
  167. ins->scbs[scb->index].data = NULL;
  168. #endif
  169. if (scb->index < ins->scb_highest_frag_index)
  170. ins->scb_highest_frag_index = scb->index;
  171. if (scb->index == ins->nscb - 1) {
  172. ins->nscb --;
  173. }
  174. if (ins->scb_highest_frag_index > ins->nscb) {
  175. ins->scb_highest_frag_index = ins->nscb;
  176. }
  177. #if 0
  178. /* !!!! THIS IS A PIECE OF SHIT MADE BY ME !!! */
  179. for(i = scb->index + 1;i < ins->nscb; ++i) {
  180. ins->scbs[i - 1].index = i - 1;
  181. }
  182. #endif
  183. }
  184. #ifdef CONFIG_SND_PROC_FS
  185. void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
  186. {
  187. if (scb->proc_info) {
  188. struct proc_scb_info * scb_info = scb->proc_info->private_data;
  189. struct snd_cs46xx *chip = scb_info->chip;
  190. dev_dbg(chip->card->dev,
  191. "cs46xx_dsp_proc_free_scb_desc: freeing %s\n",
  192. scb->scb_name);
  193. snd_info_free_entry(scb->proc_info);
  194. scb->proc_info = NULL;
  195. kfree (scb_info);
  196. }
  197. }
  198. void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
  199. struct dsp_scb_descriptor * scb)
  200. {
  201. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  202. struct snd_info_entry * entry;
  203. struct proc_scb_info * scb_info;
  204. /* register to proc */
  205. if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
  206. scb->proc_info == NULL) {
  207. if ((entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
  208. ins->proc_dsp_dir)) != NULL) {
  209. scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
  210. if (!scb_info) {
  211. snd_info_free_entry(entry);
  212. entry = NULL;
  213. goto out;
  214. }
  215. scb_info->chip = chip;
  216. scb_info->scb_desc = scb;
  217. entry->content = SNDRV_INFO_CONTENT_TEXT;
  218. entry->private_data = scb_info;
  219. entry->mode = S_IFREG | 0644;
  220. entry->c.text.read = cs46xx_dsp_proc_scb_info_read;
  221. if (snd_info_register(entry) < 0) {
  222. snd_info_free_entry(entry);
  223. kfree (scb_info);
  224. entry = NULL;
  225. }
  226. }
  227. out:
  228. scb->proc_info = entry;
  229. }
  230. }
  231. #endif /* CONFIG_SND_PROC_FS */
  232. static struct dsp_scb_descriptor *
  233. _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
  234. struct dsp_symbol_entry * task_entry,
  235. struct dsp_scb_descriptor * parent_scb,
  236. int scb_child_type)
  237. {
  238. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  239. struct dsp_scb_descriptor * scb;
  240. unsigned long flags;
  241. if (snd_BUG_ON(!ins->the_null_scb))
  242. return NULL;
  243. /* fill the data that will be wroten to DSP */
  244. scb_data[SCBsubListPtr] =
  245. (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
  246. scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
  247. scb_data[SCBfuncEntryPtr] |= task_entry->address;
  248. dev_dbg(chip->card->dev, "dsp_spos: creating SCB <%s>\n", name);
  249. scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
  250. scb->sub_list_ptr = ins->the_null_scb;
  251. scb->next_scb_ptr = ins->the_null_scb;
  252. scb->parent_scb_ptr = parent_scb;
  253. scb->task_entry = task_entry;
  254. /* update parent SCB */
  255. if (scb->parent_scb_ptr) {
  256. #if 0
  257. dev_dbg(chip->card->dev,
  258. "scb->parent_scb_ptr = %s\n",
  259. scb->parent_scb_ptr->scb_name);
  260. dev_dbg(chip->card->dev,
  261. "scb->parent_scb_ptr->next_scb_ptr = %s\n",
  262. scb->parent_scb_ptr->next_scb_ptr->scb_name);
  263. dev_dbg(chip->card->dev,
  264. "scb->parent_scb_ptr->sub_list_ptr = %s\n",
  265. scb->parent_scb_ptr->sub_list_ptr->scb_name);
  266. #endif
  267. /* link to parent SCB */
  268. if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
  269. if (snd_BUG_ON(scb->parent_scb_ptr->next_scb_ptr !=
  270. ins->the_null_scb))
  271. return NULL;
  272. scb->parent_scb_ptr->next_scb_ptr = scb;
  273. } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
  274. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr !=
  275. ins->the_null_scb))
  276. return NULL;
  277. scb->parent_scb_ptr->sub_list_ptr = scb;
  278. } else {
  279. snd_BUG();
  280. }
  281. spin_lock_irqsave(&chip->reg_lock, flags);
  282. /* update entry in DSP RAM */
  283. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  284. spin_unlock_irqrestore(&chip->reg_lock, flags);
  285. }
  286. cs46xx_dsp_proc_register_scb_desc (chip,scb);
  287. return scb;
  288. }
  289. static struct dsp_scb_descriptor *
  290. cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
  291. u32 dest, char * task_entry_name,
  292. struct dsp_scb_descriptor * parent_scb,
  293. int scb_child_type)
  294. {
  295. struct dsp_symbol_entry * task_entry;
  296. task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
  297. SYMBOL_CODE);
  298. if (task_entry == NULL) {
  299. dev_err(chip->card->dev,
  300. "dsp_spos: symbol %s not found\n", task_entry_name);
  301. return NULL;
  302. }
  303. return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
  304. parent_scb,scb_child_type);
  305. }
  306. struct dsp_scb_descriptor *
  307. cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
  308. {
  309. struct dsp_scb_descriptor * scb;
  310. struct dsp_timing_master_scb timing_master_scb = {
  311. { 0,
  312. 0,
  313. 0,
  314. 0
  315. },
  316. { 0,
  317. 0,
  318. 0,
  319. 0,
  320. 0
  321. },
  322. 0,0,
  323. 0,NULL_SCB_ADDR,
  324. 0,0, /* extraSampleAccum:TMreserved */
  325. 0,0, /* codecFIFOptr:codecFIFOsyncd */
  326. 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
  327. 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
  328. 0x00060000 /* nSampPerFrmQ15 */
  329. };
  330. scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
  331. TIMINGMASTER_SCB_ADDR,
  332. "TIMINGMASTER",NULL,SCB_NO_PARENT);
  333. return scb;
  334. }
  335. struct dsp_scb_descriptor *
  336. cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
  337. u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
  338. u32 dest, struct dsp_scb_descriptor * parent_scb,
  339. int scb_child_type)
  340. {
  341. struct dsp_scb_descriptor * scb;
  342. struct dsp_codec_output_scb codec_out_scb = {
  343. { 0,
  344. 0,
  345. 0,
  346. 0
  347. },
  348. {
  349. 0,
  350. 0,
  351. 0,
  352. 0,
  353. 0
  354. },
  355. 0,0,
  356. 0,NULL_SCB_ADDR,
  357. 0, /* COstrmRsConfig */
  358. 0, /* COstrmBufPtr */
  359. channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
  360. 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
  361. 0,child_scb_addr /* COreserved - need child scb to work with rom code */
  362. };
  363. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
  364. dest,"S16_CODECOUTPUTTASK",parent_scb,
  365. scb_child_type);
  366. return scb;
  367. }
  368. struct dsp_scb_descriptor *
  369. cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
  370. u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
  371. u32 dest, struct dsp_scb_descriptor * parent_scb,
  372. int scb_child_type)
  373. {
  374. struct dsp_scb_descriptor * scb;
  375. struct dsp_codec_input_scb codec_input_scb = {
  376. { 0,
  377. 0,
  378. 0,
  379. 0
  380. },
  381. {
  382. 0,
  383. 0,
  384. 0,
  385. 0,
  386. 0
  387. },
  388. #if 0 /* cs4620 */
  389. SyncIOSCB,NULL_SCB_ADDR
  390. #else
  391. 0 , 0,
  392. #endif
  393. 0,0,
  394. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
  395. sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
  396. channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
  397. link input slot 3 :rightChanINdisp=""slot 4 */
  398. 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
  399. because AC97 is already 20 bits */
  400. 0x80008000 /* ??clw cwcgame.scb has 0 */
  401. };
  402. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
  403. dest,"S16_CODECINPUTTASK",parent_scb,
  404. scb_child_type);
  405. return scb;
  406. }
  407. static struct dsp_scb_descriptor *
  408. cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
  409. u16 sample_buffer_addr, u32 dest,
  410. int virtual_channel, u32 playback_hw_addr,
  411. struct dsp_scb_descriptor * parent_scb,
  412. int scb_child_type)
  413. {
  414. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  415. struct dsp_scb_descriptor * scb;
  416. struct dsp_generic_scb pcm_reader_scb = {
  417. /*
  418. Play DMA Task xfers data from host buffer to SP buffer
  419. init/runtime variables:
  420. PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
  421. DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
  422. DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
  423. DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
  424. DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
  425. DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
  426. DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
  427. DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
  428. DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
  429. ? Other combinations possible from:
  430. DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
  431. DMA_RQ_C2_AC_NONE 0x00000000L
  432. DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
  433. DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
  434. DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
  435. DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
  436. HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
  437. aligned to dword boundary
  438. */
  439. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  440. { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
  441. DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
  442. DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
  443. DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
  444. DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
  445. 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
  446. /* Barnette said that is what we should use since */
  447. /* we are not running in optimized mode? */
  448. DMA_RQ_C2_AC_NONE +
  449. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
  450. /* buffer (on host) crosses half-way point */
  451. virtual_channel, /* Play DMA channel arbitrarily set to 0 */
  452. playback_hw_addr, /* HostBuffAddr (source) */
  453. DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
  454. sample_buffer_addr /* SP Buffer Address (destination) */
  455. },
  456. /* Scatter/gather DMA requestor extension (5 ints) */
  457. {
  458. 0,
  459. 0,
  460. 0,
  461. 0,
  462. 0
  463. },
  464. /* Sublist pointer & next stream control block (SCB) link. */
  465. NULL_SCB_ADDR,NULL_SCB_ADDR,
  466. /* Pointer to this tasks parameter block & stream function pointer */
  467. 0,NULL_SCB_ADDR,
  468. /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
  469. /* for incoming streams, or basicReq.saw, for outgoing streams) */
  470. RSCONFIG_DMA_ENABLE + /* enable DMA */
  471. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
  472. /* uses it for some reason */
  473. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
  474. RSCONFIG_SAMPLE_16STEREO +
  475. RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
  476. /* Stream sample pointer & MAC-unit mode for this stream */
  477. (sample_buffer_addr << 0x10),
  478. /* Fractional increment per output sample in the input sample buffer */
  479. 0,
  480. {
  481. /* Standard stereo volume control
  482. default muted */
  483. 0xffff,0xffff,
  484. 0xffff,0xffff
  485. }
  486. };
  487. if (ins->null_algorithm == NULL) {
  488. ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
  489. SYMBOL_CODE);
  490. if (ins->null_algorithm == NULL) {
  491. dev_err(chip->card->dev,
  492. "dsp_spos: symbol NULLALGORITHM not found\n");
  493. return NULL;
  494. }
  495. }
  496. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
  497. dest,ins->null_algorithm,parent_scb,
  498. scb_child_type);
  499. return scb;
  500. }
  501. #define GOF_PER_SEC 200
  502. struct dsp_scb_descriptor *
  503. cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
  504. int rate,
  505. u16 src_buffer_addr,
  506. u16 src_delay_buffer_addr, u32 dest,
  507. struct dsp_scb_descriptor * parent_scb,
  508. int scb_child_type,
  509. int pass_through)
  510. {
  511. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  512. struct dsp_scb_descriptor * scb;
  513. unsigned int tmp1, tmp2;
  514. unsigned int phiIncr;
  515. unsigned int correctionPerGOF, correctionPerSec;
  516. dev_dbg(chip->card->dev, "dsp_spos: setting %s rate to %u\n",
  517. scb_name, rate);
  518. /*
  519. * Compute the values used to drive the actual sample rate conversion.
  520. * The following formulas are being computed, using inline assembly
  521. * since we need to use 64 bit arithmetic to compute the values:
  522. *
  523. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  524. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  525. * GOF_PER_SEC)
  526. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  527. * GOF_PER_SEC * correctionPerGOF
  528. *
  529. * i.e.
  530. *
  531. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  532. * correctionPerGOF:correctionPerSec =
  533. * dividend:remainder(ulOther / GOF_PER_SEC)
  534. */
  535. tmp1 = rate << 16;
  536. phiIncr = tmp1 / 48000;
  537. tmp1 -= phiIncr * 48000;
  538. tmp1 <<= 10;
  539. phiIncr <<= 10;
  540. tmp2 = tmp1 / 48000;
  541. phiIncr += tmp2;
  542. tmp1 -= tmp2 * 48000;
  543. correctionPerGOF = tmp1 / GOF_PER_SEC;
  544. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  545. correctionPerSec = tmp1;
  546. {
  547. struct dsp_src_task_scb src_task_scb = {
  548. 0x0028,0x00c8,
  549. 0x5555,0x0000,
  550. 0x0000,0x0000,
  551. src_buffer_addr,1,
  552. correctionPerGOF,correctionPerSec,
  553. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  554. 0x0000,src_delay_buffer_addr,
  555. 0x0,
  556. 0x080,(src_delay_buffer_addr + (24 * 4)),
  557. 0,0, /* next_scb, sub_list_ptr */
  558. 0,0, /* entry, this_spb */
  559. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  560. src_buffer_addr << 0x10,
  561. phiIncr,
  562. {
  563. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
  564. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
  565. }
  566. };
  567. if (ins->s16_up == NULL) {
  568. ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
  569. SYMBOL_CODE);
  570. if (ins->s16_up == NULL) {
  571. dev_err(chip->card->dev,
  572. "dsp_spos: symbol S16_UPSRC not found\n");
  573. return NULL;
  574. }
  575. }
  576. /* clear buffers */
  577. _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
  578. _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
  579. if (pass_through) {
  580. /* wont work with any other rate than
  581. the native DSP rate */
  582. snd_BUG_ON(rate != 48000);
  583. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  584. dest,"DMAREADER",parent_scb,
  585. scb_child_type);
  586. } else {
  587. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  588. dest,ins->s16_up,parent_scb,
  589. scb_child_type);
  590. }
  591. }
  592. return scb;
  593. }
  594. #if 0 /* not used */
  595. struct dsp_scb_descriptor *
  596. cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
  597. u16 buffer_addr, u32 dest,
  598. struct dsp_scb_descriptor * parent_scb,
  599. int scb_child_type) {
  600. struct dsp_scb_descriptor * scb;
  601. struct dsp_filter_scb filter_scb = {
  602. .a0_right = 0x41a9,
  603. .a0_left = 0x41a9,
  604. .a1_right = 0xb8e4,
  605. .a1_left = 0xb8e4,
  606. .a2_right = 0x3e55,
  607. .a2_left = 0x3e55,
  608. .filter_unused3 = 0x0000,
  609. .filter_unused2 = 0x0000,
  610. .output_buf_ptr = buffer_addr,
  611. .init = 0x000,
  612. .prev_sample_output1 = 0x00000000,
  613. .prev_sample_output2 = 0x00000000,
  614. .prev_sample_input1 = 0x00000000,
  615. .prev_sample_input2 = 0x00000000,
  616. .next_scb_ptr = 0x0000,
  617. .sub_list_ptr = 0x0000,
  618. .entry_point = 0x0000,
  619. .spb_ptr = 0x0000,
  620. .b0_right = 0x0e38,
  621. .b0_left = 0x0e38,
  622. .b1_right = 0x1c71,
  623. .b1_left = 0x1c71,
  624. .b2_right = 0x0e38,
  625. .b2_left = 0x0e38,
  626. };
  627. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
  628. dest,"FILTERTASK",parent_scb,
  629. scb_child_type);
  630. return scb;
  631. }
  632. #endif /* not used */
  633. struct dsp_scb_descriptor *
  634. cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
  635. u16 mix_buffer_addr, u32 dest,
  636. struct dsp_scb_descriptor * parent_scb,
  637. int scb_child_type)
  638. {
  639. struct dsp_scb_descriptor * scb;
  640. struct dsp_mix_only_scb master_mix_scb = {
  641. /* 0 */ { 0,
  642. /* 1 */ 0,
  643. /* 2 */ mix_buffer_addr,
  644. /* 3 */ 0
  645. /* */ },
  646. {
  647. /* 4 */ 0,
  648. /* 5 */ 0,
  649. /* 6 */ 0,
  650. /* 7 */ 0,
  651. /* 8 */ 0x00000080
  652. },
  653. /* 9 */ 0,0,
  654. /* A */ 0,0,
  655. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  656. /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
  657. /* D */ 0,
  658. {
  659. /* E */ 0x8000,0x8000,
  660. /* F */ 0x8000,0x8000
  661. }
  662. };
  663. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
  664. dest,"S16_MIX",parent_scb,
  665. scb_child_type);
  666. return scb;
  667. }
  668. struct dsp_scb_descriptor *
  669. cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
  670. u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
  671. struct dsp_scb_descriptor * parent_scb,
  672. int scb_child_type)
  673. {
  674. struct dsp_scb_descriptor * scb;
  675. struct dsp_mix2_ostream_scb mix2_ostream_scb = {
  676. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  677. {
  678. DMA_RQ_C1_SOURCE_MOD64 +
  679. DMA_RQ_C1_DEST_ON_HOST +
  680. DMA_RQ_C1_DEST_MOD1024 +
  681. DMA_RQ_C1_WRITEBACK_SRC_FLAG +
  682. DMA_RQ_C1_WRITEBACK_DEST_FLAG +
  683. 15,
  684. DMA_RQ_C2_AC_NONE +
  685. DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
  686. CS46XX_DSP_CAPTURE_CHANNEL,
  687. DMA_RQ_SD_SP_SAMPLE_ADDR +
  688. mix_buffer_addr,
  689. 0x0
  690. },
  691. { 0, 0, 0, 0, 0, },
  692. 0,0,
  693. 0,writeback_spb,
  694. RSCONFIG_DMA_ENABLE +
  695. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
  696. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
  697. RSCONFIG_DMA_TO_HOST +
  698. RSCONFIG_SAMPLE_16STEREO +
  699. RSCONFIG_MODULO_64,
  700. (mix_buffer_addr + (32 * 4)) << 0x10,
  701. 1,0,
  702. 0x0001,0x0080,
  703. 0xFFFF,0
  704. };
  705. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
  706. dest,"S16_MIX_TO_OSTREAM",parent_scb,
  707. scb_child_type);
  708. return scb;
  709. }
  710. struct dsp_scb_descriptor *
  711. cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
  712. u16 vari_buffer_addr0,
  713. u16 vari_buffer_addr1,
  714. u32 dest,
  715. struct dsp_scb_descriptor * parent_scb,
  716. int scb_child_type)
  717. {
  718. struct dsp_scb_descriptor * scb;
  719. struct dsp_vari_decimate_scb vari_decimate_scb = {
  720. 0x0028,0x00c8,
  721. 0x5555,0x0000,
  722. 0x0000,0x0000,
  723. vari_buffer_addr0,vari_buffer_addr1,
  724. 0x0028,0x00c8,
  725. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
  726. 0xFF800000,
  727. 0,
  728. 0x0080,vari_buffer_addr1 + (25 * 4),
  729. 0,0,
  730. 0,0,
  731. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  732. vari_buffer_addr0 << 0x10,
  733. 0x04000000,
  734. {
  735. 0x8000,0x8000,
  736. 0xFFFF,0xFFFF
  737. }
  738. };
  739. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
  740. dest,"VARIDECIMATE",parent_scb,
  741. scb_child_type);
  742. return scb;
  743. }
  744. static struct dsp_scb_descriptor *
  745. cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  746. struct dsp_scb_descriptor * input_scb,
  747. struct dsp_scb_descriptor * parent_scb,
  748. int scb_child_type)
  749. {
  750. struct dsp_scb_descriptor * scb;
  751. struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
  752. { 0,
  753. 0,
  754. 0,
  755. 0
  756. },
  757. {
  758. 0,
  759. 0,
  760. 0,
  761. 0,
  762. 0
  763. },
  764. 0,0,
  765. 0,0,
  766. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
  767. 0,
  768. /* 0xD */ 0,input_scb->address,
  769. {
  770. /* 0xE */ 0x8000,0x8000,
  771. /* 0xF */ 0x8000,0x8000
  772. }
  773. };
  774. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
  775. dest,"PCMSERIALINPUTTASK",parent_scb,
  776. scb_child_type);
  777. return scb;
  778. }
  779. static struct dsp_scb_descriptor *
  780. cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  781. u16 hfg_scb_address,
  782. u16 asynch_buffer_address,
  783. struct dsp_scb_descriptor * parent_scb,
  784. int scb_child_type)
  785. {
  786. struct dsp_scb_descriptor * scb;
  787. struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
  788. 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
  789. 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
  790. /* : Max delta 25 dwords == 100 bytes */
  791. 0,hfg_scb_address, /* Point to HFG task SCB */
  792. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  793. 0, /* Initialize accumulated Phi to 0 */
  794. 0,0x2aab, /* Const 1/3 */
  795. {
  796. 0, /* Define the unused elements */
  797. 0,
  798. 0
  799. },
  800. 0,0,
  801. 0,dest + AFGTxAccumPhi,
  802. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
  803. (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
  804. to the producer pointer */
  805. /* There is no correct initial value, it will depend upon the detected
  806. rate etc */
  807. 0x18000000, /* Phi increment for approx 32k operation */
  808. 0x8000,0x8000, /* Volume controls are unused at this time */
  809. 0x8000,0x8000
  810. };
  811. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
  812. dest,"ASYNCHFGTXCODE",parent_scb,
  813. scb_child_type);
  814. return scb;
  815. }
  816. struct dsp_scb_descriptor *
  817. cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  818. u16 hfg_scb_address,
  819. u16 asynch_buffer_address,
  820. struct dsp_scb_descriptor * parent_scb,
  821. int scb_child_type)
  822. {
  823. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  824. struct dsp_scb_descriptor * scb;
  825. struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
  826. 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
  827. 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
  828. /* : Max delta 25 dwords == 100 bytes */
  829. 0,hfg_scb_address, /* Point to HFG task SCB */
  830. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  831. {
  832. 0, /* Define the unused elements */
  833. 0,
  834. 0,
  835. 0,
  836. 0
  837. },
  838. 0,0,
  839. 0,dest,
  840. RSCONFIG_MODULO_128 |
  841. RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
  842. ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
  843. synchrinized to the producer pointer */
  844. /* There is no correct initial value, it will depend upon the detected
  845. rate etc */
  846. 0x18000000,
  847. /* Set IEC958 input volume */
  848. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  849. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  850. };
  851. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
  852. dest,"ASYNCHFGRXCODE",parent_scb,
  853. scb_child_type);
  854. return scb;
  855. }
  856. #if 0 /* not used */
  857. struct dsp_scb_descriptor *
  858. cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  859. u16 snoop_buffer_address,
  860. struct dsp_scb_descriptor * snoop_scb,
  861. struct dsp_scb_descriptor * parent_scb,
  862. int scb_child_type)
  863. {
  864. struct dsp_scb_descriptor * scb;
  865. struct dsp_output_snoop_scb output_snoop_scb = {
  866. { 0, /* not used. Zero */
  867. 0,
  868. 0,
  869. 0,
  870. },
  871. {
  872. 0, /* not used. Zero */
  873. 0,
  874. 0,
  875. 0,
  876. 0
  877. },
  878. 0,0,
  879. 0,0,
  880. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  881. snoop_buffer_address << 0x10,
  882. 0,0,
  883. 0,
  884. 0,snoop_scb->address
  885. };
  886. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
  887. dest,"OUTPUTSNOOP",parent_scb,
  888. scb_child_type);
  889. return scb;
  890. }
  891. #endif /* not used */
  892. struct dsp_scb_descriptor *
  893. cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  894. struct dsp_scb_descriptor * parent_scb,
  895. int scb_child_type)
  896. {
  897. struct dsp_scb_descriptor * scb;
  898. struct dsp_spio_write_scb spio_write_scb = {
  899. 0,0, /* SPIOWAddress2:SPIOWAddress1; */
  900. 0, /* SPIOWData1; */
  901. 0, /* SPIOWData2; */
  902. 0,0, /* SPIOWAddress4:SPIOWAddress3; */
  903. 0, /* SPIOWData3; */
  904. 0, /* SPIOWData4; */
  905. 0,0, /* SPIOWDataPtr:Unused1; */
  906. { 0,0 }, /* Unused2[2]; */
  907. 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
  908. 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
  909. {
  910. 0,
  911. 0,
  912. 0,
  913. 0,
  914. 0 /* Unused3[5]; */
  915. }
  916. };
  917. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
  918. dest,"SPIOWRITE",parent_scb,
  919. scb_child_type);
  920. return scb;
  921. }
  922. struct dsp_scb_descriptor *
  923. cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  924. u16 snoop_buffer_address,
  925. struct dsp_scb_descriptor * snoop_scb,
  926. struct dsp_scb_descriptor * parent_scb,
  927. int scb_child_type)
  928. {
  929. struct dsp_scb_descriptor * scb;
  930. struct dsp_magic_snoop_task magic_snoop_scb = {
  931. /* 0 */ 0, /* i0 */
  932. /* 1 */ 0, /* i1 */
  933. /* 2 */ snoop_buffer_address << 0x10,
  934. /* 3 */ 0,snoop_scb->address,
  935. /* 4 */ 0, /* i3 */
  936. /* 5 */ 0, /* i4 */
  937. /* 6 */ 0, /* i5 */
  938. /* 7 */ 0, /* i6 */
  939. /* 8 */ 0, /* i7 */
  940. /* 9 */ 0,0, /* next_scb, sub_list_ptr */
  941. /* A */ 0,0, /* entry_point, this_ptr */
  942. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  943. /* C */ snoop_buffer_address << 0x10,
  944. /* D */ 0,
  945. /* E */ { 0x8000,0x8000,
  946. /* F */ 0xffff,0xffff
  947. }
  948. };
  949. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
  950. dest,"MAGICSNOOPTASK",parent_scb,
  951. scb_child_type);
  952. return scb;
  953. }
  954. static struct dsp_scb_descriptor *
  955. find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
  956. {
  957. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  958. struct dsp_scb_descriptor * scb = from;
  959. while (scb->next_scb_ptr != ins->the_null_scb) {
  960. if (snd_BUG_ON(!scb->next_scb_ptr))
  961. return NULL;
  962. scb = scb->next_scb_ptr;
  963. }
  964. return scb;
  965. }
  966. static u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
  967. 0x0600, /* 1 */
  968. 0x1500, /* 2 */
  969. 0x1580, /* 3 */
  970. 0x1600, /* 4 */
  971. 0x1680, /* 5 */
  972. 0x1700, /* 6 */
  973. 0x1780, /* 7 */
  974. 0x1800, /* 8 */
  975. 0x1880, /* 9 */
  976. 0x1900, /* 10 */
  977. 0x1980, /* 11 */
  978. 0x1A00, /* 12 */
  979. 0x1A80, /* 13 */
  980. 0x1B00, /* 14 */
  981. 0x1B80, /* 15 */
  982. 0x1C00, /* 16 */
  983. 0x1C80, /* 17 */
  984. 0x1D00, /* 18 */
  985. 0x1D80, /* 19 */
  986. 0x1E00, /* 20 */
  987. 0x1E80, /* 21 */
  988. 0x1F00, /* 22 */
  989. 0x1F80, /* 23 */
  990. 0x2000, /* 24 */
  991. 0x2080, /* 25 */
  992. 0x2100, /* 26 */
  993. 0x2180, /* 27 */
  994. 0x2200, /* 28 */
  995. 0x2280, /* 29 */
  996. 0x2300, /* 30 */
  997. 0x2380, /* 31 */
  998. 0x2400, /* 32 */
  999. };
  1000. static u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
  1001. 0x2B80,
  1002. 0x2BA0,
  1003. 0x2BC0,
  1004. 0x2BE0,
  1005. 0x2D00,
  1006. 0x2D20,
  1007. 0x2D40,
  1008. 0x2D60,
  1009. 0x2D80,
  1010. 0x2DA0,
  1011. 0x2DC0,
  1012. 0x2DE0,
  1013. 0x2E00,
  1014. 0x2E20
  1015. };
  1016. static u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
  1017. 0x2480,
  1018. 0x2500,
  1019. 0x2580,
  1020. 0x2600,
  1021. 0x2680,
  1022. 0x2700,
  1023. 0x2780,
  1024. 0x2800,
  1025. 0x2880,
  1026. 0x2900,
  1027. 0x2980,
  1028. 0x2A00,
  1029. 0x2A80,
  1030. 0x2B00
  1031. };
  1032. struct dsp_pcm_channel_descriptor *
  1033. cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
  1034. u32 sample_rate, void * private_data,
  1035. u32 hw_dma_addr,
  1036. int pcm_channel_id)
  1037. {
  1038. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1039. struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
  1040. struct dsp_scb_descriptor * src_parent_scb = NULL;
  1041. /* struct dsp_scb_descriptor * pcm_parent_scb; */
  1042. char scb_name[DSP_MAX_SCB_NAME];
  1043. int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
  1044. unsigned long flags;
  1045. switch (pcm_channel_id) {
  1046. case DSP_PCM_MAIN_CHANNEL:
  1047. mixer_scb = ins->master_mix_scb;
  1048. break;
  1049. case DSP_PCM_REAR_CHANNEL:
  1050. mixer_scb = ins->rear_mix_scb;
  1051. break;
  1052. case DSP_PCM_CENTER_LFE_CHANNEL:
  1053. mixer_scb = ins->center_lfe_mix_scb;
  1054. break;
  1055. case DSP_PCM_S71_CHANNEL:
  1056. /* TODO */
  1057. snd_BUG();
  1058. break;
  1059. case DSP_IEC958_CHANNEL:
  1060. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1061. return NULL;
  1062. mixer_scb = ins->asynch_tx_scb;
  1063. /* if sample rate is set to 48khz we pass
  1064. the Sample Rate Converted (which could
  1065. alter the raw data stream ...) */
  1066. if (sample_rate == 48000) {
  1067. dev_dbg(chip->card->dev, "IEC958 pass through\n");
  1068. /* Hack to bypass creating a new SRC */
  1069. pass_through = 1;
  1070. }
  1071. break;
  1072. default:
  1073. snd_BUG();
  1074. return NULL;
  1075. }
  1076. /* default sample rate is 44100 */
  1077. if (!sample_rate) sample_rate = 44100;
  1078. /* search for a already created SRC SCB with the same sample rate */
  1079. for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
  1080. (pcm_index == -1 || src_scb == NULL); ++i) {
  1081. /* virtual channel reserved
  1082. for capture */
  1083. if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
  1084. if (ins->pcm_channels[i].active) {
  1085. if (!src_scb &&
  1086. ins->pcm_channels[i].sample_rate == sample_rate &&
  1087. ins->pcm_channels[i].mixer_scb == mixer_scb) {
  1088. src_scb = ins->pcm_channels[i].src_scb;
  1089. ins->pcm_channels[i].src_scb->ref_count ++;
  1090. src_index = ins->pcm_channels[i].src_slot;
  1091. }
  1092. } else if (pcm_index == -1) {
  1093. pcm_index = i;
  1094. }
  1095. }
  1096. if (pcm_index == -1) {
  1097. dev_err(chip->card->dev, "dsp_spos: no free PCM channel\n");
  1098. return NULL;
  1099. }
  1100. if (src_scb == NULL) {
  1101. if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
  1102. dev_err(chip->card->dev,
  1103. "dsp_spos: to many SRC instances\n!");
  1104. return NULL;
  1105. }
  1106. /* find a free slot */
  1107. for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
  1108. if (ins->src_scb_slots[i] == 0) {
  1109. src_index = i;
  1110. ins->src_scb_slots[i] = 1;
  1111. break;
  1112. }
  1113. }
  1114. if (snd_BUG_ON(src_index == -1))
  1115. return NULL;
  1116. /* we need to create a new SRC SCB */
  1117. if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
  1118. src_parent_scb = mixer_scb;
  1119. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1120. } else {
  1121. src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
  1122. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1123. }
  1124. snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
  1125. dev_dbg(chip->card->dev,
  1126. "dsp_spos: creating SRC \"%s\"\n", scb_name);
  1127. src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
  1128. sample_rate,
  1129. src_output_buffer_addr[src_index],
  1130. src_delay_buffer_addr[src_index],
  1131. /* 0x400 - 0x600 source SCBs */
  1132. 0x400 + (src_index * 0x10) ,
  1133. src_parent_scb,
  1134. insert_point,
  1135. pass_through);
  1136. if (!src_scb) {
  1137. dev_err(chip->card->dev,
  1138. "dsp_spos: failed to create SRCtaskSCB\n");
  1139. return NULL;
  1140. }
  1141. /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
  1142. ins->nsrc_scb ++;
  1143. }
  1144. snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
  1145. dev_dbg(chip->card->dev, "dsp_spos: creating PCM \"%s\" (%d)\n",
  1146. scb_name, pcm_channel_id);
  1147. pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
  1148. pcm_reader_buffer_addr[pcm_index],
  1149. /* 0x200 - 400 PCMreader SCBs */
  1150. (pcm_index * 0x10) + 0x200,
  1151. pcm_index, /* virtual channel 0-31 */
  1152. hw_dma_addr, /* pcm hw addr */
  1153. NULL, /* parent SCB ptr */
  1154. 0 /* insert point */
  1155. );
  1156. if (!pcm_scb) {
  1157. dev_err(chip->card->dev,
  1158. "dsp_spos: failed to create PCMreaderSCB\n");
  1159. return NULL;
  1160. }
  1161. spin_lock_irqsave(&chip->reg_lock, flags);
  1162. ins->pcm_channels[pcm_index].sample_rate = sample_rate;
  1163. ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
  1164. ins->pcm_channels[pcm_index].src_scb = src_scb;
  1165. ins->pcm_channels[pcm_index].unlinked = 1;
  1166. ins->pcm_channels[pcm_index].private_data = private_data;
  1167. ins->pcm_channels[pcm_index].src_slot = src_index;
  1168. ins->pcm_channels[pcm_index].active = 1;
  1169. ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
  1170. ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
  1171. ins->npcm_channels ++;
  1172. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1173. return (ins->pcm_channels + pcm_index);
  1174. }
  1175. int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
  1176. struct dsp_pcm_channel_descriptor * pcm_channel,
  1177. int period_size)
  1178. {
  1179. u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
  1180. temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
  1181. switch (period_size) {
  1182. case 2048:
  1183. temp |= DMA_RQ_C1_SOURCE_MOD1024;
  1184. break;
  1185. case 1024:
  1186. temp |= DMA_RQ_C1_SOURCE_MOD512;
  1187. break;
  1188. case 512:
  1189. temp |= DMA_RQ_C1_SOURCE_MOD256;
  1190. break;
  1191. case 256:
  1192. temp |= DMA_RQ_C1_SOURCE_MOD128;
  1193. break;
  1194. case 128:
  1195. temp |= DMA_RQ_C1_SOURCE_MOD64;
  1196. break;
  1197. case 64:
  1198. temp |= DMA_RQ_C1_SOURCE_MOD32;
  1199. break;
  1200. case 32:
  1201. temp |= DMA_RQ_C1_SOURCE_MOD16;
  1202. break;
  1203. default:
  1204. dev_dbg(chip->card->dev,
  1205. "period size (%d) not supported by HW\n", period_size);
  1206. return -EINVAL;
  1207. }
  1208. snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
  1209. return 0;
  1210. }
  1211. int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
  1212. int period_size)
  1213. {
  1214. u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
  1215. temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
  1216. switch (period_size) {
  1217. case 2048:
  1218. temp |= DMA_RQ_C1_DEST_MOD1024;
  1219. break;
  1220. case 1024:
  1221. temp |= DMA_RQ_C1_DEST_MOD512;
  1222. break;
  1223. case 512:
  1224. temp |= DMA_RQ_C1_DEST_MOD256;
  1225. break;
  1226. case 256:
  1227. temp |= DMA_RQ_C1_DEST_MOD128;
  1228. break;
  1229. case 128:
  1230. temp |= DMA_RQ_C1_DEST_MOD64;
  1231. break;
  1232. case 64:
  1233. temp |= DMA_RQ_C1_DEST_MOD32;
  1234. break;
  1235. case 32:
  1236. temp |= DMA_RQ_C1_DEST_MOD16;
  1237. break;
  1238. default:
  1239. dev_dbg(chip->card->dev,
  1240. "period size (%d) not supported by HW\n", period_size);
  1241. return -EINVAL;
  1242. }
  1243. snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
  1244. return 0;
  1245. }
  1246. void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
  1247. struct dsp_pcm_channel_descriptor * pcm_channel)
  1248. {
  1249. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1250. unsigned long flags;
  1251. if (snd_BUG_ON(!pcm_channel->active ||
  1252. ins->npcm_channels <= 0 ||
  1253. pcm_channel->src_scb->ref_count <= 0))
  1254. return;
  1255. spin_lock_irqsave(&chip->reg_lock, flags);
  1256. pcm_channel->unlinked = 1;
  1257. pcm_channel->active = 0;
  1258. pcm_channel->private_data = NULL;
  1259. pcm_channel->src_scb->ref_count --;
  1260. ins->npcm_channels --;
  1261. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1262. cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
  1263. if (!pcm_channel->src_scb->ref_count) {
  1264. cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
  1265. if (snd_BUG_ON(pcm_channel->src_slot < 0 ||
  1266. pcm_channel->src_slot >= DSP_MAX_SRC_NR))
  1267. return;
  1268. ins->src_scb_slots[pcm_channel->src_slot] = 0;
  1269. ins->nsrc_scb --;
  1270. }
  1271. }
  1272. int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
  1273. struct dsp_pcm_channel_descriptor * pcm_channel)
  1274. {
  1275. unsigned long flags;
  1276. if (snd_BUG_ON(!pcm_channel->active ||
  1277. chip->dsp_spos_instance->npcm_channels <= 0))
  1278. return -EIO;
  1279. spin_lock_irqsave(&chip->reg_lock, flags);
  1280. if (pcm_channel->unlinked) {
  1281. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1282. return -EIO;
  1283. }
  1284. pcm_channel->unlinked = 1;
  1285. _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
  1286. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1287. return 0;
  1288. }
  1289. int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
  1290. struct dsp_pcm_channel_descriptor * pcm_channel)
  1291. {
  1292. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1293. struct dsp_scb_descriptor * parent_scb;
  1294. struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
  1295. unsigned long flags;
  1296. spin_lock_irqsave(&chip->reg_lock, flags);
  1297. if (pcm_channel->unlinked == 0) {
  1298. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1299. return -EIO;
  1300. }
  1301. parent_scb = src_scb;
  1302. if (src_scb->sub_list_ptr != ins->the_null_scb) {
  1303. src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
  1304. pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
  1305. }
  1306. src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
  1307. snd_BUG_ON(pcm_channel->pcm_reader_scb->parent_scb_ptr);
  1308. pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
  1309. /* update SCB entry in DSP RAM */
  1310. cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
  1311. /* update parent SCB entry */
  1312. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1313. pcm_channel->unlinked = 0;
  1314. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1315. return 0;
  1316. }
  1317. struct dsp_scb_descriptor *
  1318. cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
  1319. u16 addr, char * scb_name)
  1320. {
  1321. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1322. struct dsp_scb_descriptor * parent;
  1323. struct dsp_scb_descriptor * pcm_input;
  1324. int insert_point;
  1325. if (snd_BUG_ON(!ins->record_mixer_scb))
  1326. return NULL;
  1327. if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
  1328. parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
  1329. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1330. } else {
  1331. parent = ins->record_mixer_scb;
  1332. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1333. }
  1334. pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
  1335. source, parent,
  1336. insert_point);
  1337. return pcm_input;
  1338. }
  1339. int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1340. {
  1341. unsigned long flags;
  1342. if (snd_BUG_ON(!src->parent_scb_ptr))
  1343. return -EINVAL;
  1344. /* mute SCB */
  1345. cs46xx_dsp_scb_set_volume (chip,src,0,0);
  1346. spin_lock_irqsave(&chip->reg_lock, flags);
  1347. _dsp_unlink_scb (chip,src);
  1348. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1349. return 0;
  1350. }
  1351. int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1352. {
  1353. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1354. struct dsp_scb_descriptor * parent_scb;
  1355. if (snd_BUG_ON(src->parent_scb_ptr))
  1356. return -EINVAL;
  1357. if (snd_BUG_ON(!ins->master_mix_scb))
  1358. return -EINVAL;
  1359. if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
  1360. parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
  1361. parent_scb->next_scb_ptr = src;
  1362. } else {
  1363. parent_scb = ins->master_mix_scb;
  1364. parent_scb->sub_list_ptr = src;
  1365. }
  1366. src->parent_scb_ptr = parent_scb;
  1367. /* update entry in DSP RAM */
  1368. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1369. return 0;
  1370. }
  1371. int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
  1372. {
  1373. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1374. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1375. cs46xx_dsp_enable_spdif_hw (chip);
  1376. }
  1377. /* dont touch anything if SPDIF is open */
  1378. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1379. /* when cs46xx_iec958_post_close(...) is called it
  1380. will call this function if necessary depending on
  1381. this bit */
  1382. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1383. return -EBUSY;
  1384. }
  1385. if (snd_BUG_ON(ins->asynch_tx_scb))
  1386. return -EINVAL;
  1387. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr !=
  1388. ins->the_null_scb))
  1389. return -EINVAL;
  1390. /* reset output snooper sample buffer pointer */
  1391. snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
  1392. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
  1393. /* The asynch. transfer task */
  1394. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1395. SPDIFO_SCB_INST,
  1396. SPDIFO_IP_OUTPUT_BUFFER1,
  1397. ins->master_mix_scb,
  1398. SCB_ON_PARENT_NEXT_SCB);
  1399. if (!ins->asynch_tx_scb) return -ENOMEM;
  1400. ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
  1401. PCMSERIALINII_SCB_ADDR,
  1402. ins->ref_snoop_scb,
  1403. ins->asynch_tx_scb,
  1404. SCB_ON_PARENT_SUBLIST_SCB);
  1405. if (!ins->spdif_pcm_input_scb) return -ENOMEM;
  1406. /* monitor state */
  1407. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1408. return 0;
  1409. }
  1410. int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
  1411. {
  1412. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1413. /* dont touch anything if SPDIF is open */
  1414. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1415. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1416. return -EBUSY;
  1417. }
  1418. /* check integrety */
  1419. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1420. return -EINVAL;
  1421. if (snd_BUG_ON(!ins->spdif_pcm_input_scb))
  1422. return -EINVAL;
  1423. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr != ins->asynch_tx_scb))
  1424. return -EINVAL;
  1425. if (snd_BUG_ON(ins->asynch_tx_scb->parent_scb_ptr !=
  1426. ins->master_mix_scb))
  1427. return -EINVAL;
  1428. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1429. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1430. ins->spdif_pcm_input_scb = NULL;
  1431. ins->asynch_tx_scb = NULL;
  1432. /* clear buffer to prevent any undesired noise */
  1433. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1434. /* monitor state */
  1435. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1436. return 0;
  1437. }
  1438. int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
  1439. {
  1440. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1441. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1442. /* remove AsynchFGTxSCB and PCMSerialInput_II */
  1443. cs46xx_dsp_disable_spdif_out (chip);
  1444. /* save state */
  1445. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1446. }
  1447. /* if not enabled already */
  1448. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1449. cs46xx_dsp_enable_spdif_hw (chip);
  1450. }
  1451. /* Create the asynch. transfer task for playback */
  1452. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1453. SPDIFO_SCB_INST,
  1454. SPDIFO_IP_OUTPUT_BUFFER1,
  1455. ins->master_mix_scb,
  1456. SCB_ON_PARENT_NEXT_SCB);
  1457. /* set spdif channel status value for streaming */
  1458. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
  1459. ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1460. return 0;
  1461. }
  1462. int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
  1463. {
  1464. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1465. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1466. return -EINVAL;
  1467. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1468. /* restore settings */
  1469. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1470. /* deallocate stuff */
  1471. if (ins->spdif_pcm_input_scb != NULL) {
  1472. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1473. ins->spdif_pcm_input_scb = NULL;
  1474. }
  1475. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1476. ins->asynch_tx_scb = NULL;
  1477. /* clear buffer to prevent any undesired noise */
  1478. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1479. /* restore state */
  1480. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1481. cs46xx_dsp_enable_spdif_out (chip);
  1482. }
  1483. return 0;
  1484. }