spl_ark1668.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <spl.h>
  4. #include <asm/arch/timer.h>
  5. #include <asm/arch/ark1668-sysreg.h>
  6. #include <asm/arch/ark-common.h>
  7. #include <asm-generic/gpio.h>
  8. #define CPUPLL_CLK 696
  9. #define AUDPLL_CLK 426
  10. #define SYSPLL_CLK 330
  11. static void switch_to_main_crystal_osc(void)
  12. {
  13. unsigned int val;
  14. /* set syspll */
  15. write_sys_reg(read_sys_reg(SYS_SYSPLL_CFG) & ~(1 << 14), SYS_SYSPLL_CFG);
  16. timer_delay_us(10);
  17. write_sys_reg(read_sys_reg(SYS_PLLRFCK_CTL) | (1 << 3), SYS_PLLRFCK_CTL);
  18. val = (SYSPLL_CLK / 6) | (0x1C << 8) | (1 << 14) | (1 << 15);
  19. write_sys_reg(val, SYS_SYSPLL_CFG);
  20. /* set audpll */
  21. write_sys_reg(read_sys_reg(SYS_AUDPLL_CFG) & ~(1 << 14), SYS_AUDPLL_CFG);
  22. timer_delay_us(10);
  23. write_sys_reg(read_sys_reg(SYS_PLLRFCK_CTL) | (1 << 6), SYS_PLLRFCK_CTL);
  24. val = (AUDPLL_CLK / 6) | (0x1C << 8) | (1 << 14) | (1 << 15);
  25. write_sys_reg(val, SYS_AUDPLL_CFG);
  26. /* set cpupll */
  27. write_sys_reg(read_sys_reg(SYS_CPUPLL_CFG) & ~(1 << 14), SYS_CPUPLL_CFG);
  28. timer_delay_us(10);
  29. write_sys_reg(read_sys_reg(SYS_PLLRFCK_CTL) | (1 << 0), SYS_PLLRFCK_CTL);
  30. val = (CPUPLL_CLK / 6) | (0x1C << 8) | (1 << 14) | (1 << 15);
  31. write_sys_reg(val, SYS_CPUPLL_CFG);
  32. timer_delay_us(6000);
  33. /* set system clock */
  34. val = read_sys_reg(SYS_CLK_SEL);
  35. val &= ~0x7ffff;
  36. val |= (1 << 18) | (0 << 16) | (1 << 13) | (1 << 9) | (2 << 6) | (1 << 2) | 1;
  37. write_sys_reg(val, SYS_CLK_SEL);
  38. timer_delay_us(10);
  39. /* set ddr3 clock */
  40. val = read_sys_reg(SYS_DEVICE_CLK_CFG3);
  41. val &= ~(0x7f << 18);
  42. val |= (2 << 18); //select audpll
  43. write_sys_reg(val, SYS_DEVICE_CLK_CFG3);
  44. timer_delay_us(10);
  45. /* cpu clock switch to cpupll */
  46. val = read_sys_reg(SYS_CLK_SEL);;
  47. val &= ~(0x7 << 19);
  48. write_sys_reg(val, SYS_CLK_SEL);
  49. timer_delay_us(10);
  50. }
  51. void board_init_f(ulong dummy)
  52. {
  53. write_sys_reg(0, SYS_IO_DRIVER01);
  54. write_sys_reg(0, SYS_IO_DRIVER02);
  55. timer_init_24M();
  56. write_sys_reg(read_sys_reg(SYS_DDR_IO_CFG) & ~7, SYS_DDR_IO_CFG);
  57. gpio_direction_output(8, 0);
  58. udelay(1);
  59. switch_to_main_crystal_osc();
  60. timer_init();
  61. board_early_init_f();
  62. preloader_console_init();
  63. mem_init();
  64. }