sun8i-de2.txt 1.1 KB

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  1. Allwinner Display Engine 2.0 Clock Control Binding
  2. --------------------------------------------------
  3. Required properties :
  4. - compatible: must contain one of the following compatibles:
  5. - "allwinner,sun8i-a83t-de2-clk"
  6. - "allwinner,sun8i-h3-de2-clk"
  7. - "allwinner,sun8i-v3s-de2-clk"
  8. - "allwinner,sun50i-a64-de2-clk"
  9. - "allwinner,sun50i-h5-de2-clk"
  10. - reg: Must contain the registers base address and length
  11. - clocks: phandle to the clocks feeding the display engine subsystem.
  12. Three are needed:
  13. - "mod": the display engine module clock (on A83T it's the DE PLL)
  14. - "bus": the bus clock for the whole display engine subsystem
  15. - clock-names: Must contain the clock names described just above
  16. - resets: phandle to the reset control for the display engine subsystem.
  17. - #clock-cells : must contain 1
  18. - #reset-cells : must contain 1
  19. Example:
  20. de2_clocks: clock@1000000 {
  21. compatible = "allwinner,sun8i-h3-de2-clk";
  22. reg = <0x01000000 0x100000>;
  23. clocks = <&ccu CLK_BUS_DE>,
  24. <&ccu CLK_DE>;
  25. clock-names = "bus",
  26. "mod";
  27. resets = <&ccu RST_BUS_DE>;
  28. #clock-cells = <1>;
  29. #reset-cells = <1>;
  30. };