bcm_sf2.txt 5.0 KB

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  1. Broadcom Starfighter 2 Ethernet switch driver
  2. =============================================
  3. Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
  4. deployed in the following products:
  5. - xDSL gateways such as BCM63138
  6. - streaming/multimedia Set Top Box such as BCM7445
  7. - Cable Modem/residential gateways such as BCM7145/BCM3390
  8. The switch is typically deployed in a configuration involving between 5 to 13
  9. ports, offering a range of built-in and customizable interfaces:
  10. - single integrated Gigabit PHY
  11. - quad integrated Gigabit PHY
  12. - quad external Gigabit PHY w/ MDIO multiplexer
  13. - integrated MoCA PHY
  14. - several external MII/RevMII/GMII/RGMII interfaces
  15. The switch also supports specific congestion control features which allow MoCA
  16. fail-over not to lose packets during a MoCA role re-election, as well as out of
  17. band back-pressure to the host CPU network interface when downstream interfaces
  18. are connected at a lower speed.
  19. The switch hardware block is typically interfaced using MMIO accesses and
  20. contains a bunch of sub-blocks/registers:
  21. * SWITCH_CORE: common switch registers
  22. * SWITCH_REG: external interfaces switch register
  23. * SWITCH_MDIO: external MDIO bus controller (there is another one in SWITCH_CORE,
  24. which is used for indirect PHY accesses)
  25. * SWITCH_INDIR_RW: 64-bits wide register helper block
  26. * SWITCH_INTRL2_0/1: Level-2 interrupt controllers
  27. * SWITCH_ACB: Admission control block
  28. * SWITCH_FCB: Fail-over control block
  29. Implementation details
  30. ======================
  31. The driver is located in drivers/net/dsa/bcm_sf2.c and is implemented as a DSA
  32. driver; see Documentation/networking/dsa/dsa.txt for details on the subsystem
  33. and what it provides.
  34. The SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag
  35. which gets inserted by the switch for every packet forwarded to the CPU
  36. interface, conversely, the CPU network interface should insert a similar tag for
  37. packets entering the CPU port. The tag format is described in
  38. net/dsa/tag_brcm.c.
  39. Overall, the SF2 driver is a fairly regular DSA driver; there are a few
  40. specifics covered below.
  41. Device Tree probing
  42. -------------------
  43. The DSA platform device driver is probed using a specific compatible string
  44. provided in net/dsa/dsa.c. The reason for that is because the DSA subsystem gets
  45. registered as a platform device driver currently. DSA will provide the needed
  46. device_node pointers which are then accessible by the switch driver setup
  47. function to setup resources such as register ranges and interrupts. This
  48. currently works very well because none of the of_* functions utilized by the
  49. driver require a struct device to be bound to a struct device_node, but things
  50. may change in the future.
  51. MDIO indirect accesses
  52. ----------------------
  53. Due to a limitation in how Broadcom switches have been designed, external
  54. Broadcom switches connected to a SF2 require the use of the DSA slave MDIO bus
  55. in order to properly configure them. By default, the SF2 pseudo-PHY address, and
  56. an external switch pseudo-PHY address will both be snooping for incoming MDIO
  57. transactions, since they are at the same address (30), resulting in some kind of
  58. "double" programming. Using DSA, and setting ds->phys_mii_mask accordingly, we
  59. selectively divert reads and writes towards external Broadcom switches
  60. pseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a
  61. configurable pseudo-PHY address which circumvents the initial design limitation.
  62. Multimedia over CoAxial (MoCA) interfaces
  63. -----------------------------------------
  64. MoCA interfaces are fairly specific and require the use of a firmware blob which
  65. gets loaded onto the MoCA processor(s) for packet processing. The switch
  66. hardware contains logic which will assert/de-assert link states accordingly for
  67. the MoCA interface whenever the MoCA coaxial cable gets disconnected or the
  68. firmware gets reloaded. The SF2 driver relies on such events to properly set its
  69. MoCA interface carrier state and properly report this to the networking stack.
  70. The MoCA interfaces are supported using the PHY library's fixed PHY/emulated PHY
  71. device and the switch driver registers a fixed_link_update callback for such
  72. PHYs which reflects the link state obtained from the interrupt handler.
  73. Power Management
  74. ----------------
  75. Whenever possible, the SF2 driver tries to minimize the overall switch power
  76. consumption by applying a combination of:
  77. - turning off internal buffers/memories
  78. - disabling packet processing logic
  79. - putting integrated PHYs in IDDQ/low-power
  80. - reducing the switch core clock based on the active port count
  81. - enabling and advertising EEE
  82. - turning off RGMII data processing logic when the link goes down
  83. Wake-on-LAN
  84. -----------
  85. Wake-on-LAN is currently implemented by utilizing the host processor Ethernet
  86. MAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection
  87. between the user request and the supported host Ethernet interface WoL
  88. capabilities is done and the intersection result gets configured. During
  89. system-wide suspend/resume, only ports not participating in Wake-on-LAN are
  90. disabled.