max30102.c 16 KB

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  1. /*
  2. * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
  3. *
  4. * Copyright (C) 2017 Matt Ranostay <matt@ranostay.consulting>
  5. *
  6. * Support for MAX30105 optical particle sensor
  7. * Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * 7-bit I2C chip address: 0x57
  20. * TODO: proximity power saving feature
  21. */
  22. #include <linux/module.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/err.h>
  27. #include <linux/irq.h>
  28. #include <linux/i2c.h>
  29. #include <linux/mutex.h>
  30. #include <linux/of.h>
  31. #include <linux/regmap.h>
  32. #include <linux/iio/iio.h>
  33. #include <linux/iio/buffer.h>
  34. #include <linux/iio/kfifo_buf.h>
  35. #define MAX30102_REGMAP_NAME "max30102_regmap"
  36. #define MAX30102_DRV_NAME "max30102"
  37. #define MAX30102_PART_NUMBER 0x15
  38. enum max30102_chip_id {
  39. max30102,
  40. max30105,
  41. };
  42. enum max3012_led_idx {
  43. MAX30102_LED_RED,
  44. MAX30102_LED_IR,
  45. MAX30105_LED_GREEN,
  46. };
  47. #define MAX30102_REG_INT_STATUS 0x00
  48. #define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0)
  49. #define MAX30102_REG_INT_STATUS_PROX_INT BIT(4)
  50. #define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5)
  51. #define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6)
  52. #define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7)
  53. #define MAX30102_REG_INT_ENABLE 0x02
  54. #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4)
  55. #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5)
  56. #define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6)
  57. #define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7)
  58. #define MAX30102_REG_INT_ENABLE_MASK 0xf0
  59. #define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4
  60. #define MAX30102_REG_FIFO_WR_PTR 0x04
  61. #define MAX30102_REG_FIFO_OVR_CTR 0x05
  62. #define MAX30102_REG_FIFO_RD_PTR 0x06
  63. #define MAX30102_REG_FIFO_DATA 0x07
  64. #define MAX30102_REG_FIFO_DATA_BYTES 3
  65. #define MAX30102_REG_FIFO_CONFIG 0x08
  66. #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1)
  67. #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5
  68. #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0)
  69. #define MAX30102_REG_MODE_CONFIG 0x09
  70. #define MAX30102_REG_MODE_CONFIG_MODE_NONE 0x00
  71. #define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */
  72. #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */
  73. #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
  74. #define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)
  75. #define MAX30102_REG_MODE_CONFIG_PWR BIT(7)
  76. #define MAX30102_REG_MODE_CONTROL_SLOT21 0x11 /* multi-LED control */
  77. #define MAX30102_REG_MODE_CONTROL_SLOT43 0x12
  78. #define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))
  79. #define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT 4
  80. #define MAX30102_REG_SPO2_CONFIG 0x0a
  81. #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03
  82. #define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03
  83. #define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07
  84. #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2
  85. #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0)
  86. #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5
  87. #define MAX30102_REG_RED_LED_CONFIG 0x0c
  88. #define MAX30102_REG_IR_LED_CONFIG 0x0d
  89. #define MAX30105_REG_GREEN_LED_CONFIG 0x0e
  90. #define MAX30102_REG_TEMP_CONFIG 0x21
  91. #define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0)
  92. #define MAX30102_REG_TEMP_INTEGER 0x1f
  93. #define MAX30102_REG_TEMP_FRACTION 0x20
  94. #define MAX30102_REG_REV_ID 0xfe
  95. #define MAX30102_REG_PART_ID 0xff
  96. struct max30102_data {
  97. struct i2c_client *client;
  98. struct iio_dev *indio_dev;
  99. struct mutex lock;
  100. struct regmap *regmap;
  101. enum max30102_chip_id chip_id;
  102. u8 buffer[12];
  103. __be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
  104. };
  105. static const struct regmap_config max30102_regmap_config = {
  106. .name = MAX30102_REGMAP_NAME,
  107. .reg_bits = 8,
  108. .val_bits = 8,
  109. };
  110. static const unsigned long max30102_scan_masks[] = {
  111. BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
  112. 0
  113. };
  114. static const unsigned long max30105_scan_masks[] = {
  115. BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
  116. BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
  117. BIT(MAX30105_LED_GREEN),
  118. 0
  119. };
  120. #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
  121. .type = IIO_INTENSITY, \
  122. .channel2 = _mod, \
  123. .modified = 1, \
  124. .scan_index = _si, \
  125. .scan_type = { \
  126. .sign = 'u', \
  127. .shift = 8, \
  128. .realbits = 18, \
  129. .storagebits = 32, \
  130. .endianness = IIO_BE, \
  131. }, \
  132. }
  133. static const struct iio_chan_spec max30102_channels[] = {
  134. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
  135. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
  136. {
  137. .type = IIO_TEMP,
  138. .info_mask_separate =
  139. BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
  140. .scan_index = -1,
  141. },
  142. };
  143. static const struct iio_chan_spec max30105_channels[] = {
  144. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
  145. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
  146. MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
  147. {
  148. .type = IIO_TEMP,
  149. .info_mask_separate =
  150. BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
  151. .scan_index = -1,
  152. },
  153. };
  154. static int max30102_set_power(struct max30102_data *data, bool en)
  155. {
  156. return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
  157. MAX30102_REG_MODE_CONFIG_PWR,
  158. en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
  159. }
  160. static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
  161. {
  162. u8 reg = mode;
  163. if (!en)
  164. reg |= MAX30102_REG_MODE_CONFIG_PWR;
  165. return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
  166. MAX30102_REG_MODE_CONFIG_PWR |
  167. MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
  168. }
  169. #define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
  170. ((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
  171. static int max30102_buffer_postenable(struct iio_dev *indio_dev)
  172. {
  173. struct max30102_data *data = iio_priv(indio_dev);
  174. int ret;
  175. u8 reg;
  176. switch (*indio_dev->active_scan_mask) {
  177. case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
  178. reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
  179. break;
  180. case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
  181. BIT(MAX30105_LED_GREEN):
  182. ret = regmap_update_bits(data->regmap,
  183. MAX30102_REG_MODE_CONTROL_SLOT21,
  184. MAX30102_REG_MODE_CONTROL_SLOT_MASK,
  185. MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
  186. if (ret)
  187. return ret;
  188. ret = regmap_update_bits(data->regmap,
  189. MAX30102_REG_MODE_CONTROL_SLOT43,
  190. MAX30102_REG_MODE_CONTROL_SLOT_MASK,
  191. MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
  192. if (ret)
  193. return ret;
  194. reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
  195. break;
  196. default:
  197. return -EINVAL;
  198. }
  199. return max30102_set_powermode(data, reg, true);
  200. }
  201. static int max30102_buffer_predisable(struct iio_dev *indio_dev)
  202. {
  203. struct max30102_data *data = iio_priv(indio_dev);
  204. return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
  205. false);
  206. }
  207. static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
  208. .postenable = max30102_buffer_postenable,
  209. .predisable = max30102_buffer_predisable,
  210. };
  211. static inline int max30102_fifo_count(struct max30102_data *data)
  212. {
  213. unsigned int val;
  214. int ret;
  215. ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
  216. if (ret)
  217. return ret;
  218. /* FIFO has one sample slot left */
  219. if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
  220. return 1;
  221. return 0;
  222. }
  223. #define MAX30102_COPY_DATA(i) \
  224. memcpy(&data->processed_buffer[(i)], \
  225. &buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
  226. MAX30102_REG_FIFO_DATA_BYTES)
  227. static int max30102_read_measurement(struct max30102_data *data,
  228. unsigned int measurements)
  229. {
  230. int ret;
  231. u8 *buffer = (u8 *) &data->buffer;
  232. ret = i2c_smbus_read_i2c_block_data(data->client,
  233. MAX30102_REG_FIFO_DATA,
  234. measurements *
  235. MAX30102_REG_FIFO_DATA_BYTES,
  236. buffer);
  237. switch (measurements) {
  238. case 3:
  239. MAX30102_COPY_DATA(2);
  240. case 2: /* fall-through */
  241. MAX30102_COPY_DATA(1);
  242. case 1: /* fall-through */
  243. MAX30102_COPY_DATA(0);
  244. break;
  245. default:
  246. return -EINVAL;
  247. }
  248. return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
  249. 0 : -EINVAL;
  250. }
  251. static irqreturn_t max30102_interrupt_handler(int irq, void *private)
  252. {
  253. struct iio_dev *indio_dev = private;
  254. struct max30102_data *data = iio_priv(indio_dev);
  255. unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
  256. indio_dev->masklength);
  257. int ret, cnt = 0;
  258. mutex_lock(&data->lock);
  259. while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
  260. ret = max30102_read_measurement(data, measurements);
  261. if (ret)
  262. break;
  263. iio_push_to_buffers(data->indio_dev, data->processed_buffer);
  264. cnt--;
  265. }
  266. mutex_unlock(&data->lock);
  267. return IRQ_HANDLED;
  268. }
  269. static int max30102_get_current_idx(unsigned int val, int *reg)
  270. {
  271. /* each step is 0.200 mA */
  272. *reg = val / 200;
  273. return *reg > 0xff ? -EINVAL : 0;
  274. }
  275. static int max30102_led_init(struct max30102_data *data)
  276. {
  277. struct device *dev = &data->client->dev;
  278. struct device_node *np = dev->of_node;
  279. unsigned int val;
  280. int reg, ret;
  281. ret = of_property_read_u32(np, "maxim,red-led-current-microamp", &val);
  282. if (ret) {
  283. dev_info(dev, "no red-led-current-microamp set\n");
  284. /* Default to 7 mA RED LED */
  285. val = 7000;
  286. }
  287. ret = max30102_get_current_idx(val, &reg);
  288. if (ret) {
  289. dev_err(dev, "invalid RED LED current setting %d\n", val);
  290. return ret;
  291. }
  292. ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
  293. if (ret)
  294. return ret;
  295. if (data->chip_id == max30105) {
  296. ret = of_property_read_u32(np,
  297. "maxim,green-led-current-microamp", &val);
  298. if (ret) {
  299. dev_info(dev, "no green-led-current-microamp set\n");
  300. /* Default to 7 mA green LED */
  301. val = 7000;
  302. }
  303. ret = max30102_get_current_idx(val, &reg);
  304. if (ret) {
  305. dev_err(dev, "invalid green LED current setting %d\n",
  306. val);
  307. return ret;
  308. }
  309. ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
  310. reg);
  311. if (ret)
  312. return ret;
  313. }
  314. ret = of_property_read_u32(np, "maxim,ir-led-current-microamp", &val);
  315. if (ret) {
  316. dev_info(dev, "no ir-led-current-microamp set\n");
  317. /* Default to 7 mA IR LED */
  318. val = 7000;
  319. }
  320. ret = max30102_get_current_idx(val, &reg);
  321. if (ret) {
  322. dev_err(dev, "invalid IR LED current setting %d\n", val);
  323. return ret;
  324. }
  325. return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
  326. }
  327. static int max30102_chip_init(struct max30102_data *data)
  328. {
  329. int ret;
  330. /* setup LED current settings */
  331. ret = max30102_led_init(data);
  332. if (ret)
  333. return ret;
  334. /* configure 18-bit HR + SpO2 readings at 400Hz */
  335. ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
  336. (MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
  337. << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
  338. (MAX30102_REG_SPO2_CONFIG_SR_400HZ
  339. << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
  340. MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
  341. if (ret)
  342. return ret;
  343. /* average 4 samples + generate FIFO interrupt */
  344. ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
  345. (MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
  346. << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
  347. MAX30102_REG_FIFO_CONFIG_AFULL);
  348. if (ret)
  349. return ret;
  350. /* enable FIFO interrupt */
  351. return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
  352. MAX30102_REG_INT_ENABLE_MASK,
  353. MAX30102_REG_INT_ENABLE_FIFO_EN);
  354. }
  355. static int max30102_read_temp(struct max30102_data *data, int *val)
  356. {
  357. int ret;
  358. unsigned int reg;
  359. ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
  360. if (ret < 0)
  361. return ret;
  362. *val = reg << 4;
  363. ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
  364. if (ret < 0)
  365. return ret;
  366. *val |= reg & 0xf;
  367. *val = sign_extend32(*val, 11);
  368. return 0;
  369. }
  370. static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
  371. {
  372. int ret;
  373. if (en) {
  374. ret = max30102_set_power(data, true);
  375. if (ret)
  376. return ret;
  377. }
  378. /* start acquisition */
  379. ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
  380. MAX30102_REG_TEMP_CONFIG_TEMP_EN,
  381. MAX30102_REG_TEMP_CONFIG_TEMP_EN);
  382. if (ret)
  383. goto out;
  384. msleep(35);
  385. ret = max30102_read_temp(data, val);
  386. out:
  387. if (en)
  388. max30102_set_power(data, false);
  389. return ret;
  390. }
  391. static int max30102_read_raw(struct iio_dev *indio_dev,
  392. struct iio_chan_spec const *chan,
  393. int *val, int *val2, long mask)
  394. {
  395. struct max30102_data *data = iio_priv(indio_dev);
  396. int ret = -EINVAL;
  397. switch (mask) {
  398. case IIO_CHAN_INFO_RAW:
  399. /*
  400. * Temperature reading can only be acquired when not in
  401. * shutdown; leave shutdown briefly when buffer not running
  402. */
  403. mutex_lock(&indio_dev->mlock);
  404. if (!iio_buffer_enabled(indio_dev))
  405. ret = max30102_get_temp(data, val, true);
  406. else
  407. ret = max30102_get_temp(data, val, false);
  408. mutex_unlock(&indio_dev->mlock);
  409. if (ret)
  410. return ret;
  411. ret = IIO_VAL_INT;
  412. break;
  413. case IIO_CHAN_INFO_SCALE:
  414. *val = 1000; /* 62.5 */
  415. *val2 = 16;
  416. ret = IIO_VAL_FRACTIONAL;
  417. break;
  418. }
  419. return ret;
  420. }
  421. static const struct iio_info max30102_info = {
  422. .read_raw = max30102_read_raw,
  423. };
  424. static int max30102_probe(struct i2c_client *client,
  425. const struct i2c_device_id *id)
  426. {
  427. struct max30102_data *data;
  428. struct iio_buffer *buffer;
  429. struct iio_dev *indio_dev;
  430. int ret;
  431. unsigned int reg;
  432. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  433. if (!indio_dev)
  434. return -ENOMEM;
  435. buffer = devm_iio_kfifo_allocate(&client->dev);
  436. if (!buffer)
  437. return -ENOMEM;
  438. iio_device_attach_buffer(indio_dev, buffer);
  439. indio_dev->name = MAX30102_DRV_NAME;
  440. indio_dev->info = &max30102_info;
  441. indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
  442. indio_dev->setup_ops = &max30102_buffer_setup_ops;
  443. indio_dev->dev.parent = &client->dev;
  444. data = iio_priv(indio_dev);
  445. data->indio_dev = indio_dev;
  446. data->client = client;
  447. data->chip_id = id->driver_data;
  448. mutex_init(&data->lock);
  449. i2c_set_clientdata(client, indio_dev);
  450. switch (data->chip_id) {
  451. case max30105:
  452. indio_dev->channels = max30105_channels;
  453. indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
  454. indio_dev->available_scan_masks = max30105_scan_masks;
  455. break;
  456. case max30102:
  457. indio_dev->channels = max30102_channels;
  458. indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
  459. indio_dev->available_scan_masks = max30102_scan_masks;
  460. break;
  461. default:
  462. return -ENODEV;
  463. }
  464. data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
  465. if (IS_ERR(data->regmap)) {
  466. dev_err(&client->dev, "regmap initialization failed\n");
  467. return PTR_ERR(data->regmap);
  468. }
  469. /* check part ID */
  470. ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
  471. if (ret)
  472. return ret;
  473. if (reg != MAX30102_PART_NUMBER)
  474. return -ENODEV;
  475. /* show revision ID */
  476. ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
  477. if (ret)
  478. return ret;
  479. dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
  480. /* clear mode setting, chip shutdown */
  481. ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
  482. false);
  483. if (ret)
  484. return ret;
  485. ret = max30102_chip_init(data);
  486. if (ret)
  487. return ret;
  488. if (client->irq <= 0) {
  489. dev_err(&client->dev, "no valid irq defined\n");
  490. return -EINVAL;
  491. }
  492. ret = devm_request_threaded_irq(&client->dev, client->irq,
  493. NULL, max30102_interrupt_handler,
  494. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  495. "max30102_irq", indio_dev);
  496. if (ret) {
  497. dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
  498. return ret;
  499. }
  500. return iio_device_register(indio_dev);
  501. }
  502. static int max30102_remove(struct i2c_client *client)
  503. {
  504. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  505. struct max30102_data *data = iio_priv(indio_dev);
  506. iio_device_unregister(indio_dev);
  507. max30102_set_power(data, false);
  508. return 0;
  509. }
  510. static const struct i2c_device_id max30102_id[] = {
  511. { "max30102", max30102 },
  512. { "max30105", max30105 },
  513. {}
  514. };
  515. MODULE_DEVICE_TABLE(i2c, max30102_id);
  516. static const struct of_device_id max30102_dt_ids[] = {
  517. { .compatible = "maxim,max30102" },
  518. { .compatible = "maxim,max30105" },
  519. { }
  520. };
  521. MODULE_DEVICE_TABLE(of, max30102_dt_ids);
  522. static struct i2c_driver max30102_driver = {
  523. .driver = {
  524. .name = MAX30102_DRV_NAME,
  525. .of_match_table = of_match_ptr(max30102_dt_ids),
  526. },
  527. .probe = max30102_probe,
  528. .remove = max30102_remove,
  529. .id_table = max30102_id,
  530. };
  531. module_i2c_driver(max30102_driver);
  532. MODULE_AUTHOR("Matt Ranostay <matt@ranostay.consulting>");
  533. MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
  534. MODULE_LICENSE("GPL");