ufshcd.c 218 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver Core
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2013 Samsung India Software Operations
  6. * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  7. *
  8. * Authors:
  9. * Santosh Yaraganavi <santosh.sy@samsung.com>
  10. * Vinayak Holikatti <h.vinayak@samsung.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version 2
  15. * of the License, or (at your option) any later version.
  16. * See the COPYING file in the top-level directory or visit
  17. * <http://www.gnu.org/licenses/gpl-2.0.html>
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * This program is provided "AS IS" and "WITH ALL FAULTS" and
  25. * without warranty of any kind. You are solely responsible for
  26. * determining the appropriateness of using and distributing
  27. * the program and assume all risks associated with your exercise
  28. * of rights with respect to the program, including but not limited
  29. * to infringement of third party rights, the risks and costs of
  30. * program errors, damage to or loss of data, programs or equipment,
  31. * and unavailability or interruption of operations. Under no
  32. * circumstances will the contributor of this Program be liable for
  33. * any damages of any kind arising from your use or distribution of
  34. * this program.
  35. *
  36. * The Linux Foundation chooses to take subject only to the GPLv2
  37. * license terms, and distributes only under these terms.
  38. */
  39. #include <linux/async.h>
  40. #include <linux/devfreq.h>
  41. #include <linux/nls.h>
  42. #include <linux/of.h>
  43. #include <linux/bitfield.h>
  44. #include "ufshcd.h"
  45. #include "ufs_quirks.h"
  46. #include "unipro.h"
  47. #include "ufs-sysfs.h"
  48. #define CREATE_TRACE_POINTS
  49. #include <trace/events/ufs.h>
  50. #define UFSHCD_REQ_SENSE_SIZE 18
  51. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  52. UTP_TASK_REQ_COMPL |\
  53. UFSHCD_ERROR_MASK)
  54. /* UIC command timeout, unit: ms */
  55. #define UIC_CMD_TIMEOUT 500
  56. /* NOP OUT retries waiting for NOP IN response */
  57. #define NOP_OUT_RETRIES 10
  58. /* Timeout after 30 msecs if NOP OUT hangs without response */
  59. #define NOP_OUT_TIMEOUT 30 /* msecs */
  60. /* Query request retries */
  61. #define QUERY_REQ_RETRIES 3
  62. /* Query request timeout */
  63. #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  64. /* Task management command timeout */
  65. #define TM_CMD_TIMEOUT 100 /* msecs */
  66. /* maximum number of retries for a general UIC command */
  67. #define UFS_UIC_COMMAND_RETRIES 3
  68. /* maximum number of link-startup retries */
  69. #define DME_LINKSTARTUP_RETRIES 3
  70. /* Maximum retries for Hibern8 enter */
  71. #define UIC_HIBERN8_ENTER_RETRIES 3
  72. /* maximum number of reset retries before giving up */
  73. #define MAX_HOST_RESET_RETRIES 5
  74. /* Expose the flag value from utp_upiu_query.value */
  75. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  76. /* Interrupt aggregation default timeout, unit: 40us */
  77. #define INT_AGGR_DEF_TO 0x02
  78. #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
  79. ({ \
  80. int _ret; \
  81. if (_on) \
  82. _ret = ufshcd_enable_vreg(_dev, _vreg); \
  83. else \
  84. _ret = ufshcd_disable_vreg(_dev, _vreg); \
  85. _ret; \
  86. })
  87. #define ufshcd_hex_dump(prefix_str, buf, len) do { \
  88. size_t __len = (len); \
  89. print_hex_dump(KERN_ERR, prefix_str, \
  90. __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
  91. 16, 4, buf, __len, false); \
  92. } while (0)
  93. int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
  94. const char *prefix)
  95. {
  96. u32 *regs;
  97. size_t pos;
  98. if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
  99. return -EINVAL;
  100. regs = kzalloc(len, GFP_KERNEL);
  101. if (!regs)
  102. return -ENOMEM;
  103. for (pos = 0; pos < len; pos += 4)
  104. regs[pos / 4] = ufshcd_readl(hba, offset + pos);
  105. ufshcd_hex_dump(prefix, regs, len);
  106. kfree(regs);
  107. return 0;
  108. }
  109. EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
  110. enum {
  111. UFSHCD_MAX_CHANNEL = 0,
  112. UFSHCD_MAX_ID = 1,
  113. UFSHCD_CMD_PER_LUN = 32,
  114. UFSHCD_CAN_QUEUE = 32,
  115. };
  116. /* UFSHCD states */
  117. enum {
  118. UFSHCD_STATE_RESET,
  119. UFSHCD_STATE_ERROR,
  120. UFSHCD_STATE_OPERATIONAL,
  121. UFSHCD_STATE_EH_SCHEDULED,
  122. };
  123. /* UFSHCD error handling flags */
  124. enum {
  125. UFSHCD_EH_IN_PROGRESS = (1 << 0),
  126. };
  127. /* UFSHCD UIC layer error flags */
  128. enum {
  129. UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
  130. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
  131. UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
  132. UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
  133. UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
  134. UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
  135. };
  136. #define ufshcd_set_eh_in_progress(h) \
  137. ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
  138. #define ufshcd_eh_in_progress(h) \
  139. ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
  140. #define ufshcd_clear_eh_in_progress(h) \
  141. ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
  142. #define ufshcd_set_ufs_dev_active(h) \
  143. ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
  144. #define ufshcd_set_ufs_dev_sleep(h) \
  145. ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
  146. #define ufshcd_set_ufs_dev_poweroff(h) \
  147. ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
  148. #define ufshcd_is_ufs_dev_active(h) \
  149. ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
  150. #define ufshcd_is_ufs_dev_sleep(h) \
  151. ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
  152. #define ufshcd_is_ufs_dev_poweroff(h) \
  153. ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
  154. struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
  155. {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  156. {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  157. {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  158. {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  159. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  160. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
  161. };
  162. static inline enum ufs_dev_pwr_mode
  163. ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
  164. {
  165. return ufs_pm_lvl_states[lvl].dev_state;
  166. }
  167. static inline enum uic_link_state
  168. ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
  169. {
  170. return ufs_pm_lvl_states[lvl].link_state;
  171. }
  172. static inline enum ufs_pm_level
  173. ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
  174. enum uic_link_state link_state)
  175. {
  176. enum ufs_pm_level lvl;
  177. for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
  178. if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
  179. (ufs_pm_lvl_states[lvl].link_state == link_state))
  180. return lvl;
  181. }
  182. /* if no match found, return the level 0 */
  183. return UFS_PM_LVL_0;
  184. }
  185. static struct ufs_dev_fix ufs_fixups[] = {
  186. /* UFS cards deviations table */
  187. UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
  188. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  189. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  190. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  191. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
  192. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  193. UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
  194. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  195. UFS_DEVICE_NO_FASTAUTO),
  196. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  197. UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
  198. UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
  199. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  200. UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
  201. UFS_DEVICE_QUIRK_PA_TACTIVATE),
  202. UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
  203. UFS_DEVICE_QUIRK_PA_TACTIVATE),
  204. UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
  205. UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
  206. UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
  207. UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
  208. UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
  209. END_FIX
  210. };
  211. static void ufshcd_tmc_handler(struct ufs_hba *hba);
  212. static void ufshcd_async_scan(void *data, async_cookie_t cookie);
  213. static int ufshcd_reset_and_restore(struct ufs_hba *hba);
  214. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
  215. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
  216. static void ufshcd_hba_exit(struct ufs_hba *hba);
  217. static int ufshcd_probe_hba(struct ufs_hba *hba);
  218. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  219. bool skip_ref_clk);
  220. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
  221. static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
  222. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
  223. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
  224. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
  225. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
  226. static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
  227. static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
  228. static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
  229. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
  230. static irqreturn_t ufshcd_intr(int irq, void *__hba);
  231. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  232. struct ufs_pa_layer_attr *pwr_mode);
  233. static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
  234. {
  235. return tag >= 0 && tag < hba->nutrs;
  236. }
  237. static inline int ufshcd_enable_irq(struct ufs_hba *hba)
  238. {
  239. int ret = 0;
  240. if (!hba->is_irq_enabled) {
  241. ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
  242. hba);
  243. if (ret)
  244. dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
  245. __func__, ret);
  246. hba->is_irq_enabled = true;
  247. }
  248. return ret;
  249. }
  250. static inline void ufshcd_disable_irq(struct ufs_hba *hba)
  251. {
  252. if (hba->is_irq_enabled) {
  253. free_irq(hba->irq, hba);
  254. hba->is_irq_enabled = false;
  255. }
  256. }
  257. static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
  258. {
  259. if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
  260. scsi_unblock_requests(hba->host);
  261. }
  262. static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
  263. {
  264. if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
  265. scsi_block_requests(hba->host);
  266. }
  267. /* replace non-printable or non-ASCII characters with spaces */
  268. static inline void ufshcd_remove_non_printable(char *val)
  269. {
  270. if (!val)
  271. return;
  272. if (*val < 0x20 || *val > 0x7e)
  273. *val = ' ';
  274. }
  275. static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
  276. const char *str)
  277. {
  278. struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
  279. trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
  280. }
  281. static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
  282. const char *str)
  283. {
  284. struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
  285. trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
  286. }
  287. static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
  288. const char *str)
  289. {
  290. struct utp_task_req_desc *descp;
  291. struct utp_upiu_task_req *task_req;
  292. int off = (int)tag - hba->nutrs;
  293. descp = &hba->utmrdl_base_addr[off];
  294. task_req = (struct utp_upiu_task_req *)descp->task_req_upiu;
  295. trace_ufshcd_upiu(dev_name(hba->dev), str, &task_req->header,
  296. &task_req->input_param1);
  297. }
  298. static void ufshcd_add_command_trace(struct ufs_hba *hba,
  299. unsigned int tag, const char *str)
  300. {
  301. sector_t lba = -1;
  302. u8 opcode = 0;
  303. u32 intr, doorbell;
  304. struct ufshcd_lrb *lrbp = &hba->lrb[tag];
  305. struct scsi_cmnd *cmd = lrbp->cmd;
  306. int transfer_len = -1;
  307. if (!trace_ufshcd_command_enabled()) {
  308. /* trace UPIU W/O tracing command */
  309. if (cmd)
  310. ufshcd_add_cmd_upiu_trace(hba, tag, str);
  311. return;
  312. }
  313. if (cmd) { /* data phase exists */
  314. /* trace UPIU also */
  315. ufshcd_add_cmd_upiu_trace(hba, tag, str);
  316. opcode = cmd->cmnd[0];
  317. if ((opcode == READ_10) || (opcode == WRITE_10)) {
  318. /*
  319. * Currently we only fully trace read(10) and write(10)
  320. * commands
  321. */
  322. if (cmd->request && cmd->request->bio)
  323. lba = cmd->request->bio->bi_iter.bi_sector;
  324. transfer_len = be32_to_cpu(
  325. lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
  326. }
  327. }
  328. intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  329. doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  330. trace_ufshcd_command(dev_name(hba->dev), str, tag,
  331. doorbell, transfer_len, intr, lba, opcode);
  332. }
  333. static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
  334. {
  335. struct ufs_clk_info *clki;
  336. struct list_head *head = &hba->clk_list_head;
  337. if (list_empty(head))
  338. return;
  339. list_for_each_entry(clki, head, list) {
  340. if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
  341. clki->max_freq)
  342. dev_err(hba->dev, "clk: %s, rate: %u\n",
  343. clki->name, clki->curr_freq);
  344. }
  345. }
  346. static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
  347. struct ufs_uic_err_reg_hist *err_hist, char *err_name)
  348. {
  349. int i;
  350. for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
  351. int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
  352. if (err_hist->reg[p] == 0)
  353. continue;
  354. dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
  355. err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
  356. }
  357. }
  358. static void ufshcd_print_host_regs(struct ufs_hba *hba)
  359. {
  360. ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
  361. dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
  362. hba->ufs_version, hba->capabilities);
  363. dev_err(hba->dev,
  364. "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
  365. (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
  366. dev_err(hba->dev,
  367. "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
  368. ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
  369. hba->ufs_stats.hibern8_exit_cnt);
  370. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
  371. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
  372. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
  373. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
  374. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
  375. ufshcd_print_clk_freqs(hba);
  376. if (hba->vops && hba->vops->dbg_register_dump)
  377. hba->vops->dbg_register_dump(hba);
  378. }
  379. static
  380. void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
  381. {
  382. struct ufshcd_lrb *lrbp;
  383. int prdt_length;
  384. int tag;
  385. for_each_set_bit(tag, &bitmap, hba->nutrs) {
  386. lrbp = &hba->lrb[tag];
  387. dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
  388. tag, ktime_to_us(lrbp->issue_time_stamp));
  389. dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
  390. tag, ktime_to_us(lrbp->compl_time_stamp));
  391. dev_err(hba->dev,
  392. "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
  393. tag, (u64)lrbp->utrd_dma_addr);
  394. ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
  395. sizeof(struct utp_transfer_req_desc));
  396. dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
  397. (u64)lrbp->ucd_req_dma_addr);
  398. ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
  399. sizeof(struct utp_upiu_req));
  400. dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
  401. (u64)lrbp->ucd_rsp_dma_addr);
  402. ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
  403. sizeof(struct utp_upiu_rsp));
  404. prdt_length = le16_to_cpu(
  405. lrbp->utr_descriptor_ptr->prd_table_length);
  406. dev_err(hba->dev,
  407. "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
  408. tag, prdt_length,
  409. (u64)lrbp->ucd_prdt_dma_addr);
  410. if (pr_prdt)
  411. ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
  412. sizeof(struct ufshcd_sg_entry) * prdt_length);
  413. }
  414. }
  415. static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
  416. {
  417. struct utp_task_req_desc *tmrdp;
  418. int tag;
  419. for_each_set_bit(tag, &bitmap, hba->nutmrs) {
  420. tmrdp = &hba->utmrdl_base_addr[tag];
  421. dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
  422. ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
  423. sizeof(struct request_desc_header));
  424. dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
  425. tag);
  426. ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
  427. sizeof(struct utp_upiu_req));
  428. dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
  429. tag);
  430. ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
  431. sizeof(struct utp_task_req_desc));
  432. }
  433. }
  434. static void ufshcd_print_host_state(struct ufs_hba *hba)
  435. {
  436. dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
  437. dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
  438. hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
  439. dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
  440. hba->saved_err, hba->saved_uic_err);
  441. dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
  442. hba->curr_dev_pwr_mode, hba->uic_link_state);
  443. dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
  444. hba->pm_op_in_progress, hba->is_sys_suspended);
  445. dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
  446. hba->auto_bkops_enabled, hba->host->host_self_blocked);
  447. dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
  448. dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
  449. hba->eh_flags, hba->req_abort_count);
  450. dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
  451. hba->capabilities, hba->caps);
  452. dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
  453. hba->dev_quirks);
  454. }
  455. /**
  456. * ufshcd_print_pwr_info - print power params as saved in hba
  457. * power info
  458. * @hba: per-adapter instance
  459. */
  460. static void ufshcd_print_pwr_info(struct ufs_hba *hba)
  461. {
  462. static const char * const names[] = {
  463. "INVALID MODE",
  464. "FAST MODE",
  465. "SLOW_MODE",
  466. "INVALID MODE",
  467. "FASTAUTO_MODE",
  468. "SLOWAUTO_MODE",
  469. "INVALID MODE",
  470. };
  471. dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
  472. __func__,
  473. hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
  474. hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
  475. names[hba->pwr_info.pwr_rx],
  476. names[hba->pwr_info.pwr_tx],
  477. hba->pwr_info.hs_rate);
  478. }
  479. /*
  480. * ufshcd_wait_for_register - wait for register value to change
  481. * @hba - per-adapter interface
  482. * @reg - mmio register offset
  483. * @mask - mask to apply to read register value
  484. * @val - wait condition
  485. * @interval_us - polling interval in microsecs
  486. * @timeout_ms - timeout in millisecs
  487. * @can_sleep - perform sleep or just spin
  488. *
  489. * Returns -ETIMEDOUT on error, zero on success
  490. */
  491. int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  492. u32 val, unsigned long interval_us,
  493. unsigned long timeout_ms, bool can_sleep)
  494. {
  495. int err = 0;
  496. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  497. /* ignore bits that we don't intend to wait on */
  498. val = val & mask;
  499. while ((ufshcd_readl(hba, reg) & mask) != val) {
  500. if (can_sleep)
  501. usleep_range(interval_us, interval_us + 50);
  502. else
  503. udelay(interval_us);
  504. if (time_after(jiffies, timeout)) {
  505. if ((ufshcd_readl(hba, reg) & mask) != val)
  506. err = -ETIMEDOUT;
  507. break;
  508. }
  509. }
  510. return err;
  511. }
  512. /**
  513. * ufshcd_get_intr_mask - Get the interrupt bit mask
  514. * @hba: Pointer to adapter instance
  515. *
  516. * Returns interrupt bit mask per version
  517. */
  518. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  519. {
  520. u32 intr_mask = 0;
  521. switch (hba->ufs_version) {
  522. case UFSHCI_VERSION_10:
  523. intr_mask = INTERRUPT_MASK_ALL_VER_10;
  524. break;
  525. case UFSHCI_VERSION_11:
  526. case UFSHCI_VERSION_20:
  527. intr_mask = INTERRUPT_MASK_ALL_VER_11;
  528. break;
  529. case UFSHCI_VERSION_21:
  530. default:
  531. intr_mask = INTERRUPT_MASK_ALL_VER_21;
  532. break;
  533. }
  534. return intr_mask;
  535. }
  536. /**
  537. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  538. * @hba: Pointer to adapter instance
  539. *
  540. * Returns UFSHCI version supported by the controller
  541. */
  542. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  543. {
  544. if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
  545. return ufshcd_vops_get_ufs_hci_version(hba);
  546. return ufshcd_readl(hba, REG_UFS_VERSION);
  547. }
  548. /**
  549. * ufshcd_is_device_present - Check if any device connected to
  550. * the host controller
  551. * @hba: pointer to adapter instance
  552. *
  553. * Returns true if device present, false if no device detected
  554. */
  555. static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
  556. {
  557. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  558. DEVICE_PRESENT) ? true : false;
  559. }
  560. /**
  561. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  562. * @lrbp: pointer to local command reference block
  563. *
  564. * This function is used to get the OCS field from UTRD
  565. * Returns the OCS field in the UTRD
  566. */
  567. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  568. {
  569. return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
  570. }
  571. /**
  572. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  573. * @task_req_descp: pointer to utp_task_req_desc structure
  574. *
  575. * This function is used to get the OCS field from UTMRD
  576. * Returns the OCS field in the UTMRD
  577. */
  578. static inline int
  579. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  580. {
  581. return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
  582. }
  583. /**
  584. * ufshcd_get_tm_free_slot - get a free slot for task management request
  585. * @hba: per adapter instance
  586. * @free_slot: pointer to variable with available slot value
  587. *
  588. * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
  589. * Returns 0 if free slot is not available, else return 1 with tag value
  590. * in @free_slot.
  591. */
  592. static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
  593. {
  594. int tag;
  595. bool ret = false;
  596. if (!free_slot)
  597. goto out;
  598. do {
  599. tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
  600. if (tag >= hba->nutmrs)
  601. goto out;
  602. } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
  603. *free_slot = tag;
  604. ret = true;
  605. out:
  606. return ret;
  607. }
  608. static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
  609. {
  610. clear_bit_unlock(slot, &hba->tm_slots_in_use);
  611. }
  612. /**
  613. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  614. * @hba: per adapter instance
  615. * @pos: position of the bit to be cleared
  616. */
  617. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  618. {
  619. if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
  620. ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  621. else
  622. ufshcd_writel(hba, ~(1 << pos),
  623. REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  624. }
  625. /**
  626. * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
  627. * @hba: per adapter instance
  628. * @pos: position of the bit to be cleared
  629. */
  630. static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
  631. {
  632. if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
  633. ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
  634. else
  635. ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
  636. }
  637. /**
  638. * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
  639. * @hba: per adapter instance
  640. * @tag: position of the bit to be cleared
  641. */
  642. static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
  643. {
  644. __clear_bit(tag, &hba->outstanding_reqs);
  645. }
  646. /**
  647. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  648. * @reg: Register value of host controller status
  649. *
  650. * Returns integer, 0 on Success and positive value if failed
  651. */
  652. static inline int ufshcd_get_lists_status(u32 reg)
  653. {
  654. return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
  655. }
  656. /**
  657. * ufshcd_get_uic_cmd_result - Get the UIC command result
  658. * @hba: Pointer to adapter instance
  659. *
  660. * This function gets the result of UIC command completion
  661. * Returns 0 on success, non zero value on error
  662. */
  663. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  664. {
  665. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  666. MASK_UIC_COMMAND_RESULT;
  667. }
  668. /**
  669. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  670. * @hba: Pointer to adapter instance
  671. *
  672. * This function gets UIC command argument3
  673. * Returns 0 on success, non zero value on error
  674. */
  675. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  676. {
  677. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  678. }
  679. /**
  680. * ufshcd_get_req_rsp - returns the TR response transaction type
  681. * @ucd_rsp_ptr: pointer to response UPIU
  682. */
  683. static inline int
  684. ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  685. {
  686. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  687. }
  688. /**
  689. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  690. * @ucd_rsp_ptr: pointer to response UPIU
  691. *
  692. * This function gets the response status and scsi_status from response UPIU
  693. * Returns the response result code.
  694. */
  695. static inline int
  696. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  697. {
  698. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  699. }
  700. /*
  701. * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
  702. * from response UPIU
  703. * @ucd_rsp_ptr: pointer to response UPIU
  704. *
  705. * Return the data segment length.
  706. */
  707. static inline unsigned int
  708. ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
  709. {
  710. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  711. MASK_RSP_UPIU_DATA_SEG_LEN;
  712. }
  713. /**
  714. * ufshcd_is_exception_event - Check if the device raised an exception event
  715. * @ucd_rsp_ptr: pointer to response UPIU
  716. *
  717. * The function checks if the device raised an exception event indicated in
  718. * the Device Information field of response UPIU.
  719. *
  720. * Returns true if exception is raised, false otherwise.
  721. */
  722. static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
  723. {
  724. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  725. MASK_RSP_EXCEPTION_EVENT ? true : false;
  726. }
  727. /**
  728. * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
  729. * @hba: per adapter instance
  730. */
  731. static inline void
  732. ufshcd_reset_intr_aggr(struct ufs_hba *hba)
  733. {
  734. ufshcd_writel(hba, INT_AGGR_ENABLE |
  735. INT_AGGR_COUNTER_AND_TIMER_RESET,
  736. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  737. }
  738. /**
  739. * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
  740. * @hba: per adapter instance
  741. * @cnt: Interrupt aggregation counter threshold
  742. * @tmout: Interrupt aggregation timeout value
  743. */
  744. static inline void
  745. ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
  746. {
  747. ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
  748. INT_AGGR_COUNTER_THLD_VAL(cnt) |
  749. INT_AGGR_TIMEOUT_VAL(tmout),
  750. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  751. }
  752. /**
  753. * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
  754. * @hba: per adapter instance
  755. */
  756. static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
  757. {
  758. ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  759. }
  760. /**
  761. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  762. * When run-stop registers are set to 1, it indicates the
  763. * host controller that it can process the requests
  764. * @hba: per adapter instance
  765. */
  766. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  767. {
  768. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  769. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  770. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  771. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  772. }
  773. /**
  774. * ufshcd_hba_start - Start controller initialization sequence
  775. * @hba: per adapter instance
  776. */
  777. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  778. {
  779. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  780. }
  781. /**
  782. * ufshcd_is_hba_active - Get controller state
  783. * @hba: per adapter instance
  784. *
  785. * Returns false if controller is active, true otherwise
  786. */
  787. static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
  788. {
  789. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
  790. ? false : true;
  791. }
  792. u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
  793. {
  794. /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
  795. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  796. (hba->ufs_version == UFSHCI_VERSION_11))
  797. return UFS_UNIPRO_VER_1_41;
  798. else
  799. return UFS_UNIPRO_VER_1_6;
  800. }
  801. EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
  802. static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
  803. {
  804. /*
  805. * If both host and device support UniPro ver1.6 or later, PA layer
  806. * parameters tuning happens during link startup itself.
  807. *
  808. * We can manually tune PA layer parameters if either host or device
  809. * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
  810. * logic simple, we will only do manual tuning if local unipro version
  811. * doesn't support ver1.6 or later.
  812. */
  813. if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
  814. return true;
  815. else
  816. return false;
  817. }
  818. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
  819. {
  820. int ret = 0;
  821. struct ufs_clk_info *clki;
  822. struct list_head *head = &hba->clk_list_head;
  823. ktime_t start = ktime_get();
  824. bool clk_state_changed = false;
  825. if (list_empty(head))
  826. goto out;
  827. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
  828. if (ret)
  829. return ret;
  830. list_for_each_entry(clki, head, list) {
  831. if (!IS_ERR_OR_NULL(clki->clk)) {
  832. if (scale_up && clki->max_freq) {
  833. if (clki->curr_freq == clki->max_freq)
  834. continue;
  835. clk_state_changed = true;
  836. ret = clk_set_rate(clki->clk, clki->max_freq);
  837. if (ret) {
  838. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  839. __func__, clki->name,
  840. clki->max_freq, ret);
  841. break;
  842. }
  843. trace_ufshcd_clk_scaling(dev_name(hba->dev),
  844. "scaled up", clki->name,
  845. clki->curr_freq,
  846. clki->max_freq);
  847. clki->curr_freq = clki->max_freq;
  848. } else if (!scale_up && clki->min_freq) {
  849. if (clki->curr_freq == clki->min_freq)
  850. continue;
  851. clk_state_changed = true;
  852. ret = clk_set_rate(clki->clk, clki->min_freq);
  853. if (ret) {
  854. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  855. __func__, clki->name,
  856. clki->min_freq, ret);
  857. break;
  858. }
  859. trace_ufshcd_clk_scaling(dev_name(hba->dev),
  860. "scaled down", clki->name,
  861. clki->curr_freq,
  862. clki->min_freq);
  863. clki->curr_freq = clki->min_freq;
  864. }
  865. }
  866. dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
  867. clki->name, clk_get_rate(clki->clk));
  868. }
  869. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
  870. out:
  871. if (clk_state_changed)
  872. trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
  873. (scale_up ? "up" : "down"),
  874. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  875. return ret;
  876. }
  877. /**
  878. * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
  879. * @hba: per adapter instance
  880. * @scale_up: True if scaling up and false if scaling down
  881. *
  882. * Returns true if scaling is required, false otherwise.
  883. */
  884. static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
  885. bool scale_up)
  886. {
  887. struct ufs_clk_info *clki;
  888. struct list_head *head = &hba->clk_list_head;
  889. if (list_empty(head))
  890. return false;
  891. list_for_each_entry(clki, head, list) {
  892. if (!IS_ERR_OR_NULL(clki->clk)) {
  893. if (scale_up && clki->max_freq) {
  894. if (clki->curr_freq == clki->max_freq)
  895. continue;
  896. return true;
  897. } else if (!scale_up && clki->min_freq) {
  898. if (clki->curr_freq == clki->min_freq)
  899. continue;
  900. return true;
  901. }
  902. }
  903. }
  904. return false;
  905. }
  906. static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
  907. u64 wait_timeout_us)
  908. {
  909. unsigned long flags;
  910. int ret = 0;
  911. u32 tm_doorbell;
  912. u32 tr_doorbell;
  913. bool timeout = false, do_last_check = false;
  914. ktime_t start;
  915. ufshcd_hold(hba, false);
  916. spin_lock_irqsave(hba->host->host_lock, flags);
  917. /*
  918. * Wait for all the outstanding tasks/transfer requests.
  919. * Verify by checking the doorbell registers are clear.
  920. */
  921. start = ktime_get();
  922. do {
  923. if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
  924. ret = -EBUSY;
  925. goto out;
  926. }
  927. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  928. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  929. if (!tm_doorbell && !tr_doorbell) {
  930. timeout = false;
  931. break;
  932. } else if (do_last_check) {
  933. break;
  934. }
  935. spin_unlock_irqrestore(hba->host->host_lock, flags);
  936. schedule();
  937. if (ktime_to_us(ktime_sub(ktime_get(), start)) >
  938. wait_timeout_us) {
  939. timeout = true;
  940. /*
  941. * We might have scheduled out for long time so make
  942. * sure to check if doorbells are cleared by this time
  943. * or not.
  944. */
  945. do_last_check = true;
  946. }
  947. spin_lock_irqsave(hba->host->host_lock, flags);
  948. } while (tm_doorbell || tr_doorbell);
  949. if (timeout) {
  950. dev_err(hba->dev,
  951. "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
  952. __func__, tm_doorbell, tr_doorbell);
  953. ret = -EBUSY;
  954. }
  955. out:
  956. spin_unlock_irqrestore(hba->host->host_lock, flags);
  957. ufshcd_release(hba);
  958. return ret;
  959. }
  960. /**
  961. * ufshcd_scale_gear - scale up/down UFS gear
  962. * @hba: per adapter instance
  963. * @scale_up: True for scaling up gear and false for scaling down
  964. *
  965. * Returns 0 for success,
  966. * Returns -EBUSY if scaling can't happen at this time
  967. * Returns non-zero for any other errors
  968. */
  969. static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
  970. {
  971. #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
  972. int ret = 0;
  973. struct ufs_pa_layer_attr new_pwr_info;
  974. if (scale_up) {
  975. memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
  976. sizeof(struct ufs_pa_layer_attr));
  977. } else {
  978. memcpy(&new_pwr_info, &hba->pwr_info,
  979. sizeof(struct ufs_pa_layer_attr));
  980. if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
  981. || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
  982. /* save the current power mode */
  983. memcpy(&hba->clk_scaling.saved_pwr_info.info,
  984. &hba->pwr_info,
  985. sizeof(struct ufs_pa_layer_attr));
  986. /* scale down gear */
  987. new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
  988. new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
  989. }
  990. }
  991. /* check if the power mode needs to be changed or not? */
  992. ret = ufshcd_change_power_mode(hba, &new_pwr_info);
  993. if (ret)
  994. dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
  995. __func__, ret,
  996. hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
  997. new_pwr_info.gear_tx, new_pwr_info.gear_rx);
  998. return ret;
  999. }
  1000. static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
  1001. {
  1002. #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
  1003. int ret = 0;
  1004. /*
  1005. * make sure that there are no outstanding requests when
  1006. * clock scaling is in progress
  1007. */
  1008. ufshcd_scsi_block_requests(hba);
  1009. down_write(&hba->clk_scaling_lock);
  1010. if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
  1011. ret = -EBUSY;
  1012. up_write(&hba->clk_scaling_lock);
  1013. ufshcd_scsi_unblock_requests(hba);
  1014. }
  1015. return ret;
  1016. }
  1017. static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
  1018. {
  1019. up_write(&hba->clk_scaling_lock);
  1020. ufshcd_scsi_unblock_requests(hba);
  1021. }
  1022. /**
  1023. * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
  1024. * @hba: per adapter instance
  1025. * @scale_up: True for scaling up and false for scalin down
  1026. *
  1027. * Returns 0 for success,
  1028. * Returns -EBUSY if scaling can't happen at this time
  1029. * Returns non-zero for any other errors
  1030. */
  1031. static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
  1032. {
  1033. int ret = 0;
  1034. /* let's not get into low power until clock scaling is completed */
  1035. ufshcd_hold(hba, false);
  1036. ret = ufshcd_clock_scaling_prepare(hba);
  1037. if (ret)
  1038. return ret;
  1039. /* scale down the gear before scaling down clocks */
  1040. if (!scale_up) {
  1041. ret = ufshcd_scale_gear(hba, false);
  1042. if (ret)
  1043. goto out;
  1044. }
  1045. ret = ufshcd_scale_clks(hba, scale_up);
  1046. if (ret) {
  1047. if (!scale_up)
  1048. ufshcd_scale_gear(hba, true);
  1049. goto out;
  1050. }
  1051. /* scale up the gear after scaling up clocks */
  1052. if (scale_up) {
  1053. ret = ufshcd_scale_gear(hba, true);
  1054. if (ret) {
  1055. ufshcd_scale_clks(hba, false);
  1056. goto out;
  1057. }
  1058. }
  1059. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
  1060. out:
  1061. ufshcd_clock_scaling_unprepare(hba);
  1062. ufshcd_release(hba);
  1063. return ret;
  1064. }
  1065. static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
  1066. {
  1067. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1068. clk_scaling.suspend_work);
  1069. unsigned long irq_flags;
  1070. spin_lock_irqsave(hba->host->host_lock, irq_flags);
  1071. if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
  1072. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1073. return;
  1074. }
  1075. hba->clk_scaling.is_suspended = true;
  1076. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1077. __ufshcd_suspend_clkscaling(hba);
  1078. }
  1079. static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
  1080. {
  1081. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1082. clk_scaling.resume_work);
  1083. unsigned long irq_flags;
  1084. spin_lock_irqsave(hba->host->host_lock, irq_flags);
  1085. if (!hba->clk_scaling.is_suspended) {
  1086. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1087. return;
  1088. }
  1089. hba->clk_scaling.is_suspended = false;
  1090. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1091. devfreq_resume_device(hba->devfreq);
  1092. }
  1093. static int ufshcd_devfreq_target(struct device *dev,
  1094. unsigned long *freq, u32 flags)
  1095. {
  1096. int ret = 0;
  1097. struct ufs_hba *hba = dev_get_drvdata(dev);
  1098. ktime_t start;
  1099. bool scale_up, sched_clk_scaling_suspend_work = false;
  1100. struct list_head *clk_list = &hba->clk_list_head;
  1101. struct ufs_clk_info *clki;
  1102. unsigned long irq_flags;
  1103. if (!ufshcd_is_clkscaling_supported(hba))
  1104. return -EINVAL;
  1105. spin_lock_irqsave(hba->host->host_lock, irq_flags);
  1106. if (ufshcd_eh_in_progress(hba)) {
  1107. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1108. return 0;
  1109. }
  1110. if (!hba->clk_scaling.active_reqs)
  1111. sched_clk_scaling_suspend_work = true;
  1112. if (list_empty(clk_list)) {
  1113. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1114. goto out;
  1115. }
  1116. clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
  1117. scale_up = (*freq == clki->max_freq) ? true : false;
  1118. if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
  1119. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1120. ret = 0;
  1121. goto out; /* no state change required */
  1122. }
  1123. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1124. pm_runtime_get_noresume(hba->dev);
  1125. if (!pm_runtime_active(hba->dev)) {
  1126. pm_runtime_put_noidle(hba->dev);
  1127. ret = -EAGAIN;
  1128. goto out;
  1129. }
  1130. start = ktime_get();
  1131. ret = ufshcd_devfreq_scale(hba, scale_up);
  1132. pm_runtime_put(hba->dev);
  1133. trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
  1134. (scale_up ? "up" : "down"),
  1135. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  1136. out:
  1137. if (sched_clk_scaling_suspend_work)
  1138. queue_work(hba->clk_scaling.workq,
  1139. &hba->clk_scaling.suspend_work);
  1140. return ret;
  1141. }
  1142. static int ufshcd_devfreq_get_dev_status(struct device *dev,
  1143. struct devfreq_dev_status *stat)
  1144. {
  1145. struct ufs_hba *hba = dev_get_drvdata(dev);
  1146. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  1147. unsigned long flags;
  1148. if (!ufshcd_is_clkscaling_supported(hba))
  1149. return -EINVAL;
  1150. memset(stat, 0, sizeof(*stat));
  1151. spin_lock_irqsave(hba->host->host_lock, flags);
  1152. if (!scaling->window_start_t)
  1153. goto start_window;
  1154. if (scaling->is_busy_started)
  1155. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  1156. scaling->busy_start_t));
  1157. stat->total_time = jiffies_to_usecs((long)jiffies -
  1158. (long)scaling->window_start_t);
  1159. stat->busy_time = scaling->tot_busy_t;
  1160. start_window:
  1161. scaling->window_start_t = jiffies;
  1162. scaling->tot_busy_t = 0;
  1163. if (hba->outstanding_reqs) {
  1164. scaling->busy_start_t = ktime_get();
  1165. scaling->is_busy_started = true;
  1166. } else {
  1167. scaling->busy_start_t = 0;
  1168. scaling->is_busy_started = false;
  1169. }
  1170. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1171. return 0;
  1172. }
  1173. static struct devfreq_dev_profile ufs_devfreq_profile = {
  1174. .polling_ms = 100,
  1175. .target = ufshcd_devfreq_target,
  1176. .get_dev_status = ufshcd_devfreq_get_dev_status,
  1177. };
  1178. static int ufshcd_devfreq_init(struct ufs_hba *hba)
  1179. {
  1180. struct list_head *clk_list = &hba->clk_list_head;
  1181. struct ufs_clk_info *clki;
  1182. struct devfreq *devfreq;
  1183. int ret;
  1184. /* Skip devfreq if we don't have any clocks in the list */
  1185. if (list_empty(clk_list))
  1186. return 0;
  1187. clki = list_first_entry(clk_list, struct ufs_clk_info, list);
  1188. dev_pm_opp_add(hba->dev, clki->min_freq, 0);
  1189. dev_pm_opp_add(hba->dev, clki->max_freq, 0);
  1190. devfreq = devfreq_add_device(hba->dev,
  1191. &ufs_devfreq_profile,
  1192. DEVFREQ_GOV_SIMPLE_ONDEMAND,
  1193. NULL);
  1194. if (IS_ERR(devfreq)) {
  1195. ret = PTR_ERR(devfreq);
  1196. dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
  1197. dev_pm_opp_remove(hba->dev, clki->min_freq);
  1198. dev_pm_opp_remove(hba->dev, clki->max_freq);
  1199. return ret;
  1200. }
  1201. hba->devfreq = devfreq;
  1202. return 0;
  1203. }
  1204. static void ufshcd_devfreq_remove(struct ufs_hba *hba)
  1205. {
  1206. struct list_head *clk_list = &hba->clk_list_head;
  1207. struct ufs_clk_info *clki;
  1208. if (!hba->devfreq)
  1209. return;
  1210. devfreq_remove_device(hba->devfreq);
  1211. hba->devfreq = NULL;
  1212. clki = list_first_entry(clk_list, struct ufs_clk_info, list);
  1213. dev_pm_opp_remove(hba->dev, clki->min_freq);
  1214. dev_pm_opp_remove(hba->dev, clki->max_freq);
  1215. }
  1216. static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
  1217. {
  1218. unsigned long flags;
  1219. devfreq_suspend_device(hba->devfreq);
  1220. spin_lock_irqsave(hba->host->host_lock, flags);
  1221. hba->clk_scaling.window_start_t = 0;
  1222. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1223. }
  1224. static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
  1225. {
  1226. unsigned long flags;
  1227. bool suspend = false;
  1228. if (!ufshcd_is_clkscaling_supported(hba))
  1229. return;
  1230. spin_lock_irqsave(hba->host->host_lock, flags);
  1231. if (!hba->clk_scaling.is_suspended) {
  1232. suspend = true;
  1233. hba->clk_scaling.is_suspended = true;
  1234. }
  1235. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1236. if (suspend)
  1237. __ufshcd_suspend_clkscaling(hba);
  1238. }
  1239. static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
  1240. {
  1241. unsigned long flags;
  1242. bool resume = false;
  1243. if (!ufshcd_is_clkscaling_supported(hba))
  1244. return;
  1245. spin_lock_irqsave(hba->host->host_lock, flags);
  1246. if (hba->clk_scaling.is_suspended) {
  1247. resume = true;
  1248. hba->clk_scaling.is_suspended = false;
  1249. }
  1250. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1251. if (resume)
  1252. devfreq_resume_device(hba->devfreq);
  1253. }
  1254. static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
  1255. struct device_attribute *attr, char *buf)
  1256. {
  1257. struct ufs_hba *hba = dev_get_drvdata(dev);
  1258. return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
  1259. }
  1260. static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
  1261. struct device_attribute *attr, const char *buf, size_t count)
  1262. {
  1263. struct ufs_hba *hba = dev_get_drvdata(dev);
  1264. u32 value;
  1265. int err;
  1266. if (kstrtou32(buf, 0, &value))
  1267. return -EINVAL;
  1268. value = !!value;
  1269. if (value == hba->clk_scaling.is_allowed)
  1270. goto out;
  1271. pm_runtime_get_sync(hba->dev);
  1272. ufshcd_hold(hba, false);
  1273. cancel_work_sync(&hba->clk_scaling.suspend_work);
  1274. cancel_work_sync(&hba->clk_scaling.resume_work);
  1275. hba->clk_scaling.is_allowed = value;
  1276. if (value) {
  1277. ufshcd_resume_clkscaling(hba);
  1278. } else {
  1279. ufshcd_suspend_clkscaling(hba);
  1280. err = ufshcd_devfreq_scale(hba, true);
  1281. if (err)
  1282. dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
  1283. __func__, err);
  1284. }
  1285. ufshcd_release(hba);
  1286. pm_runtime_put_sync(hba->dev);
  1287. out:
  1288. return count;
  1289. }
  1290. static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
  1291. {
  1292. hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
  1293. hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
  1294. sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
  1295. hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
  1296. hba->clk_scaling.enable_attr.attr.mode = 0644;
  1297. if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
  1298. dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
  1299. }
  1300. static void ufshcd_ungate_work(struct work_struct *work)
  1301. {
  1302. int ret;
  1303. unsigned long flags;
  1304. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1305. clk_gating.ungate_work);
  1306. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  1307. spin_lock_irqsave(hba->host->host_lock, flags);
  1308. if (hba->clk_gating.state == CLKS_ON) {
  1309. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1310. goto unblock_reqs;
  1311. }
  1312. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1313. ufshcd_setup_clocks(hba, true);
  1314. /* Exit from hibern8 */
  1315. if (ufshcd_can_hibern8_during_gating(hba)) {
  1316. /* Prevent gating in this path */
  1317. hba->clk_gating.is_suspended = true;
  1318. if (ufshcd_is_link_hibern8(hba)) {
  1319. ret = ufshcd_uic_hibern8_exit(hba);
  1320. if (ret)
  1321. dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
  1322. __func__, ret);
  1323. else
  1324. ufshcd_set_link_active(hba);
  1325. }
  1326. hba->clk_gating.is_suspended = false;
  1327. }
  1328. unblock_reqs:
  1329. ufshcd_scsi_unblock_requests(hba);
  1330. }
  1331. /**
  1332. * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
  1333. * Also, exit from hibern8 mode and set the link as active.
  1334. * @hba: per adapter instance
  1335. * @async: This indicates whether caller should ungate clocks asynchronously.
  1336. */
  1337. int ufshcd_hold(struct ufs_hba *hba, bool async)
  1338. {
  1339. int rc = 0;
  1340. bool flush_result;
  1341. unsigned long flags;
  1342. if (!ufshcd_is_clkgating_allowed(hba))
  1343. goto out;
  1344. spin_lock_irqsave(hba->host->host_lock, flags);
  1345. hba->clk_gating.active_reqs++;
  1346. if (ufshcd_eh_in_progress(hba)) {
  1347. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1348. return 0;
  1349. }
  1350. start:
  1351. switch (hba->clk_gating.state) {
  1352. case CLKS_ON:
  1353. /*
  1354. * Wait for the ungate work to complete if in progress.
  1355. * Though the clocks may be in ON state, the link could
  1356. * still be in hibner8 state if hibern8 is allowed
  1357. * during clock gating.
  1358. * Make sure we exit hibern8 state also in addition to
  1359. * clocks being ON.
  1360. */
  1361. if (ufshcd_can_hibern8_during_gating(hba) &&
  1362. ufshcd_is_link_hibern8(hba)) {
  1363. if (async) {
  1364. rc = -EAGAIN;
  1365. hba->clk_gating.active_reqs--;
  1366. break;
  1367. }
  1368. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1369. flush_result = flush_work(&hba->clk_gating.ungate_work);
  1370. if (hba->clk_gating.is_suspended && !flush_result)
  1371. goto out;
  1372. spin_lock_irqsave(hba->host->host_lock, flags);
  1373. goto start;
  1374. }
  1375. break;
  1376. case REQ_CLKS_OFF:
  1377. if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
  1378. hba->clk_gating.state = CLKS_ON;
  1379. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1380. hba->clk_gating.state);
  1381. break;
  1382. }
  1383. /*
  1384. * If we are here, it means gating work is either done or
  1385. * currently running. Hence, fall through to cancel gating
  1386. * work and to enable clocks.
  1387. */
  1388. case CLKS_OFF:
  1389. hba->clk_gating.state = REQ_CLKS_ON;
  1390. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1391. hba->clk_gating.state);
  1392. if (queue_work(hba->clk_gating.clk_gating_workq,
  1393. &hba->clk_gating.ungate_work))
  1394. ufshcd_scsi_block_requests(hba);
  1395. /*
  1396. * fall through to check if we should wait for this
  1397. * work to be done or not.
  1398. */
  1399. case REQ_CLKS_ON:
  1400. if (async) {
  1401. rc = -EAGAIN;
  1402. hba->clk_gating.active_reqs--;
  1403. break;
  1404. }
  1405. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1406. flush_work(&hba->clk_gating.ungate_work);
  1407. /* Make sure state is CLKS_ON before returning */
  1408. spin_lock_irqsave(hba->host->host_lock, flags);
  1409. goto start;
  1410. default:
  1411. dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
  1412. __func__, hba->clk_gating.state);
  1413. break;
  1414. }
  1415. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1416. out:
  1417. return rc;
  1418. }
  1419. EXPORT_SYMBOL_GPL(ufshcd_hold);
  1420. static void ufshcd_gate_work(struct work_struct *work)
  1421. {
  1422. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1423. clk_gating.gate_work.work);
  1424. unsigned long flags;
  1425. spin_lock_irqsave(hba->host->host_lock, flags);
  1426. /*
  1427. * In case you are here to cancel this work the gating state
  1428. * would be marked as REQ_CLKS_ON. In this case save time by
  1429. * skipping the gating work and exit after changing the clock
  1430. * state to CLKS_ON.
  1431. */
  1432. if (hba->clk_gating.is_suspended ||
  1433. (hba->clk_gating.state == REQ_CLKS_ON)) {
  1434. hba->clk_gating.state = CLKS_ON;
  1435. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1436. hba->clk_gating.state);
  1437. goto rel_lock;
  1438. }
  1439. if (hba->clk_gating.active_reqs
  1440. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  1441. || hba->lrb_in_use || hba->outstanding_tasks
  1442. || hba->active_uic_cmd || hba->uic_async_done)
  1443. goto rel_lock;
  1444. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1445. /* put the link into hibern8 mode before turning off clocks */
  1446. if (ufshcd_can_hibern8_during_gating(hba)) {
  1447. if (ufshcd_uic_hibern8_enter(hba)) {
  1448. hba->clk_gating.state = CLKS_ON;
  1449. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1450. hba->clk_gating.state);
  1451. goto out;
  1452. }
  1453. ufshcd_set_link_hibern8(hba);
  1454. }
  1455. if (!ufshcd_is_link_active(hba))
  1456. ufshcd_setup_clocks(hba, false);
  1457. else
  1458. /* If link is active, device ref_clk can't be switched off */
  1459. __ufshcd_setup_clocks(hba, false, true);
  1460. /*
  1461. * In case you are here to cancel this work the gating state
  1462. * would be marked as REQ_CLKS_ON. In this case keep the state
  1463. * as REQ_CLKS_ON which would anyway imply that clocks are off
  1464. * and a request to turn them on is pending. By doing this way,
  1465. * we keep the state machine in tact and this would ultimately
  1466. * prevent from doing cancel work multiple times when there are
  1467. * new requests arriving before the current cancel work is done.
  1468. */
  1469. spin_lock_irqsave(hba->host->host_lock, flags);
  1470. if (hba->clk_gating.state == REQ_CLKS_OFF) {
  1471. hba->clk_gating.state = CLKS_OFF;
  1472. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1473. hba->clk_gating.state);
  1474. }
  1475. rel_lock:
  1476. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1477. out:
  1478. return;
  1479. }
  1480. /* host lock must be held before calling this variant */
  1481. static void __ufshcd_release(struct ufs_hba *hba)
  1482. {
  1483. if (!ufshcd_is_clkgating_allowed(hba))
  1484. return;
  1485. hba->clk_gating.active_reqs--;
  1486. if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
  1487. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  1488. || hba->lrb_in_use || hba->outstanding_tasks
  1489. || hba->active_uic_cmd || hba->uic_async_done
  1490. || ufshcd_eh_in_progress(hba))
  1491. return;
  1492. hba->clk_gating.state = REQ_CLKS_OFF;
  1493. trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
  1494. queue_delayed_work(hba->clk_gating.clk_gating_workq,
  1495. &hba->clk_gating.gate_work,
  1496. msecs_to_jiffies(hba->clk_gating.delay_ms));
  1497. }
  1498. void ufshcd_release(struct ufs_hba *hba)
  1499. {
  1500. unsigned long flags;
  1501. spin_lock_irqsave(hba->host->host_lock, flags);
  1502. __ufshcd_release(hba);
  1503. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1504. }
  1505. EXPORT_SYMBOL_GPL(ufshcd_release);
  1506. static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
  1507. struct device_attribute *attr, char *buf)
  1508. {
  1509. struct ufs_hba *hba = dev_get_drvdata(dev);
  1510. return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
  1511. }
  1512. static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
  1513. struct device_attribute *attr, const char *buf, size_t count)
  1514. {
  1515. struct ufs_hba *hba = dev_get_drvdata(dev);
  1516. unsigned long flags, value;
  1517. if (kstrtoul(buf, 0, &value))
  1518. return -EINVAL;
  1519. spin_lock_irqsave(hba->host->host_lock, flags);
  1520. hba->clk_gating.delay_ms = value;
  1521. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1522. return count;
  1523. }
  1524. static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
  1525. struct device_attribute *attr, char *buf)
  1526. {
  1527. struct ufs_hba *hba = dev_get_drvdata(dev);
  1528. return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
  1529. }
  1530. static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
  1531. struct device_attribute *attr, const char *buf, size_t count)
  1532. {
  1533. struct ufs_hba *hba = dev_get_drvdata(dev);
  1534. unsigned long flags;
  1535. u32 value;
  1536. if (kstrtou32(buf, 0, &value))
  1537. return -EINVAL;
  1538. value = !!value;
  1539. if (value == hba->clk_gating.is_enabled)
  1540. goto out;
  1541. if (value) {
  1542. ufshcd_release(hba);
  1543. } else {
  1544. spin_lock_irqsave(hba->host->host_lock, flags);
  1545. hba->clk_gating.active_reqs++;
  1546. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1547. }
  1548. hba->clk_gating.is_enabled = value;
  1549. out:
  1550. return count;
  1551. }
  1552. static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
  1553. {
  1554. char wq_name[sizeof("ufs_clkscaling_00")];
  1555. if (!ufshcd_is_clkscaling_supported(hba))
  1556. return;
  1557. INIT_WORK(&hba->clk_scaling.suspend_work,
  1558. ufshcd_clk_scaling_suspend_work);
  1559. INIT_WORK(&hba->clk_scaling.resume_work,
  1560. ufshcd_clk_scaling_resume_work);
  1561. snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
  1562. hba->host->host_no);
  1563. hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
  1564. ufshcd_clkscaling_init_sysfs(hba);
  1565. }
  1566. static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
  1567. {
  1568. if (!ufshcd_is_clkscaling_supported(hba))
  1569. return;
  1570. destroy_workqueue(hba->clk_scaling.workq);
  1571. ufshcd_devfreq_remove(hba);
  1572. }
  1573. static void ufshcd_init_clk_gating(struct ufs_hba *hba)
  1574. {
  1575. char wq_name[sizeof("ufs_clk_gating_00")];
  1576. if (!ufshcd_is_clkgating_allowed(hba))
  1577. return;
  1578. hba->clk_gating.delay_ms = 150;
  1579. INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
  1580. INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
  1581. snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
  1582. hba->host->host_no);
  1583. hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
  1584. WQ_MEM_RECLAIM);
  1585. hba->clk_gating.is_enabled = true;
  1586. hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
  1587. hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
  1588. sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
  1589. hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
  1590. hba->clk_gating.delay_attr.attr.mode = 0644;
  1591. if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
  1592. dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
  1593. hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
  1594. hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
  1595. sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
  1596. hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
  1597. hba->clk_gating.enable_attr.attr.mode = 0644;
  1598. if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
  1599. dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
  1600. }
  1601. static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
  1602. {
  1603. if (!ufshcd_is_clkgating_allowed(hba))
  1604. return;
  1605. device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
  1606. device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
  1607. cancel_work_sync(&hba->clk_gating.ungate_work);
  1608. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  1609. destroy_workqueue(hba->clk_gating.clk_gating_workq);
  1610. }
  1611. /* Must be called with host lock acquired */
  1612. static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
  1613. {
  1614. bool queue_resume_work = false;
  1615. if (!ufshcd_is_clkscaling_supported(hba))
  1616. return;
  1617. if (!hba->clk_scaling.active_reqs++)
  1618. queue_resume_work = true;
  1619. if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
  1620. return;
  1621. if (queue_resume_work)
  1622. queue_work(hba->clk_scaling.workq,
  1623. &hba->clk_scaling.resume_work);
  1624. if (!hba->clk_scaling.window_start_t) {
  1625. hba->clk_scaling.window_start_t = jiffies;
  1626. hba->clk_scaling.tot_busy_t = 0;
  1627. hba->clk_scaling.is_busy_started = false;
  1628. }
  1629. if (!hba->clk_scaling.is_busy_started) {
  1630. hba->clk_scaling.busy_start_t = ktime_get();
  1631. hba->clk_scaling.is_busy_started = true;
  1632. }
  1633. }
  1634. static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
  1635. {
  1636. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  1637. if (!ufshcd_is_clkscaling_supported(hba))
  1638. return;
  1639. if (!hba->outstanding_reqs && scaling->is_busy_started) {
  1640. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  1641. scaling->busy_start_t));
  1642. scaling->busy_start_t = 0;
  1643. scaling->is_busy_started = false;
  1644. }
  1645. }
  1646. /**
  1647. * ufshcd_send_command - Send SCSI or device management commands
  1648. * @hba: per adapter instance
  1649. * @task_tag: Task tag of the command
  1650. */
  1651. static inline
  1652. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  1653. {
  1654. hba->lrb[task_tag].issue_time_stamp = ktime_get();
  1655. hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
  1656. ufshcd_add_command_trace(hba, task_tag, "send");
  1657. ufshcd_clk_scaling_start_busy(hba);
  1658. __set_bit(task_tag, &hba->outstanding_reqs);
  1659. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  1660. /* Make sure that doorbell is committed immediately */
  1661. wmb();
  1662. }
  1663. /**
  1664. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  1665. * @lrbp: pointer to local reference block
  1666. */
  1667. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  1668. {
  1669. int len;
  1670. if (lrbp->sense_buffer &&
  1671. ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
  1672. int len_to_copy;
  1673. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
  1674. len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
  1675. memcpy(lrbp->sense_buffer,
  1676. lrbp->ucd_rsp_ptr->sr.sense_data,
  1677. min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
  1678. }
  1679. }
  1680. /**
  1681. * ufshcd_copy_query_response() - Copy the Query Response and the data
  1682. * descriptor
  1683. * @hba: per adapter instance
  1684. * @lrbp: pointer to local reference block
  1685. */
  1686. static
  1687. int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1688. {
  1689. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  1690. memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  1691. /* Get the descriptor */
  1692. if (hba->dev_cmd.query.descriptor &&
  1693. lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  1694. u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
  1695. GENERAL_UPIU_REQUEST_SIZE;
  1696. u16 resp_len;
  1697. u16 buf_len;
  1698. /* data segment length */
  1699. resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
  1700. MASK_QUERY_DATA_SEG_LEN;
  1701. buf_len = be16_to_cpu(
  1702. hba->dev_cmd.query.request.upiu_req.length);
  1703. if (likely(buf_len >= resp_len)) {
  1704. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  1705. } else {
  1706. dev_warn(hba->dev,
  1707. "%s: Response size is bigger than buffer",
  1708. __func__);
  1709. return -EINVAL;
  1710. }
  1711. }
  1712. return 0;
  1713. }
  1714. /**
  1715. * ufshcd_hba_capabilities - Read controller capabilities
  1716. * @hba: per adapter instance
  1717. */
  1718. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  1719. {
  1720. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  1721. /* nutrs and nutmrs are 0 based values */
  1722. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  1723. hba->nutmrs =
  1724. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  1725. }
  1726. /**
  1727. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  1728. * to accept UIC commands
  1729. * @hba: per adapter instance
  1730. * Return true on success, else false
  1731. */
  1732. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  1733. {
  1734. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  1735. return true;
  1736. else
  1737. return false;
  1738. }
  1739. /**
  1740. * ufshcd_get_upmcrs - Get the power mode change request status
  1741. * @hba: Pointer to adapter instance
  1742. *
  1743. * This function gets the UPMCRS field of HCS register
  1744. * Returns value of UPMCRS field
  1745. */
  1746. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  1747. {
  1748. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  1749. }
  1750. /**
  1751. * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
  1752. * @hba: per adapter instance
  1753. * @uic_cmd: UIC command
  1754. *
  1755. * Mutex must be held.
  1756. */
  1757. static inline void
  1758. ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  1759. {
  1760. WARN_ON(hba->active_uic_cmd);
  1761. hba->active_uic_cmd = uic_cmd;
  1762. /* Write Args */
  1763. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  1764. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  1765. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  1766. /* Write UIC Cmd */
  1767. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  1768. REG_UIC_COMMAND);
  1769. }
  1770. /**
  1771. * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
  1772. * @hba: per adapter instance
  1773. * @uic_cmd: UIC command
  1774. *
  1775. * Must be called with mutex held.
  1776. * Returns 0 only if success.
  1777. */
  1778. static int
  1779. ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  1780. {
  1781. int ret;
  1782. unsigned long flags;
  1783. if (wait_for_completion_timeout(&uic_cmd->done,
  1784. msecs_to_jiffies(UIC_CMD_TIMEOUT)))
  1785. ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
  1786. else
  1787. ret = -ETIMEDOUT;
  1788. spin_lock_irqsave(hba->host->host_lock, flags);
  1789. hba->active_uic_cmd = NULL;
  1790. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1791. return ret;
  1792. }
  1793. /**
  1794. * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  1795. * @hba: per adapter instance
  1796. * @uic_cmd: UIC command
  1797. * @completion: initialize the completion only if this is set to true
  1798. *
  1799. * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
  1800. * with mutex held and host_lock locked.
  1801. * Returns 0 only if success.
  1802. */
  1803. static int
  1804. __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
  1805. bool completion)
  1806. {
  1807. if (!ufshcd_ready_for_uic_cmd(hba)) {
  1808. dev_err(hba->dev,
  1809. "Controller not ready to accept UIC commands\n");
  1810. return -EIO;
  1811. }
  1812. if (completion)
  1813. init_completion(&uic_cmd->done);
  1814. ufshcd_dispatch_uic_cmd(hba, uic_cmd);
  1815. return 0;
  1816. }
  1817. /**
  1818. * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  1819. * @hba: per adapter instance
  1820. * @uic_cmd: UIC command
  1821. *
  1822. * Returns 0 only if success.
  1823. */
  1824. static int
  1825. ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  1826. {
  1827. int ret;
  1828. unsigned long flags;
  1829. ufshcd_hold(hba, false);
  1830. mutex_lock(&hba->uic_cmd_mutex);
  1831. ufshcd_add_delay_before_dme_cmd(hba);
  1832. spin_lock_irqsave(hba->host->host_lock, flags);
  1833. ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
  1834. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1835. if (!ret)
  1836. ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
  1837. mutex_unlock(&hba->uic_cmd_mutex);
  1838. ufshcd_release(hba);
  1839. return ret;
  1840. }
  1841. /**
  1842. * ufshcd_map_sg - Map scatter-gather list to prdt
  1843. * @hba: per adapter instance
  1844. * @lrbp: pointer to local reference block
  1845. *
  1846. * Returns 0 in case of success, non-zero value in case of failure
  1847. */
  1848. static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1849. {
  1850. struct ufshcd_sg_entry *prd_table;
  1851. struct scatterlist *sg;
  1852. struct scsi_cmnd *cmd;
  1853. int sg_segments;
  1854. int i;
  1855. cmd = lrbp->cmd;
  1856. sg_segments = scsi_dma_map(cmd);
  1857. if (sg_segments < 0)
  1858. return sg_segments;
  1859. if (sg_segments) {
  1860. if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
  1861. lrbp->utr_descriptor_ptr->prd_table_length =
  1862. cpu_to_le16((u16)(sg_segments *
  1863. sizeof(struct ufshcd_sg_entry)));
  1864. else
  1865. lrbp->utr_descriptor_ptr->prd_table_length =
  1866. cpu_to_le16((u16) (sg_segments));
  1867. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  1868. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  1869. prd_table[i].size =
  1870. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  1871. prd_table[i].base_addr =
  1872. cpu_to_le32(lower_32_bits(sg->dma_address));
  1873. prd_table[i].upper_addr =
  1874. cpu_to_le32(upper_32_bits(sg->dma_address));
  1875. prd_table[i].reserved = 0;
  1876. }
  1877. } else {
  1878. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  1879. }
  1880. return 0;
  1881. }
  1882. /**
  1883. * ufshcd_enable_intr - enable interrupts
  1884. * @hba: per adapter instance
  1885. * @intrs: interrupt bits
  1886. */
  1887. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  1888. {
  1889. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  1890. if (hba->ufs_version == UFSHCI_VERSION_10) {
  1891. u32 rw;
  1892. rw = set & INTERRUPT_MASK_RW_VER_10;
  1893. set = rw | ((set ^ intrs) & intrs);
  1894. } else {
  1895. set |= intrs;
  1896. }
  1897. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  1898. }
  1899. /**
  1900. * ufshcd_disable_intr - disable interrupts
  1901. * @hba: per adapter instance
  1902. * @intrs: interrupt bits
  1903. */
  1904. static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
  1905. {
  1906. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  1907. if (hba->ufs_version == UFSHCI_VERSION_10) {
  1908. u32 rw;
  1909. rw = (set & INTERRUPT_MASK_RW_VER_10) &
  1910. ~(intrs & INTERRUPT_MASK_RW_VER_10);
  1911. set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
  1912. } else {
  1913. set &= ~intrs;
  1914. }
  1915. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  1916. }
  1917. /**
  1918. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  1919. * descriptor according to request
  1920. * @lrbp: pointer to local reference block
  1921. * @upiu_flags: flags required in the header
  1922. * @cmd_dir: requests data direction
  1923. */
  1924. static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
  1925. u32 *upiu_flags, enum dma_data_direction cmd_dir)
  1926. {
  1927. struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
  1928. u32 data_direction;
  1929. u32 dword_0;
  1930. if (cmd_dir == DMA_FROM_DEVICE) {
  1931. data_direction = UTP_DEVICE_TO_HOST;
  1932. *upiu_flags = UPIU_CMD_FLAGS_READ;
  1933. } else if (cmd_dir == DMA_TO_DEVICE) {
  1934. data_direction = UTP_HOST_TO_DEVICE;
  1935. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  1936. } else {
  1937. data_direction = UTP_NO_DATA_TRANSFER;
  1938. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  1939. }
  1940. dword_0 = data_direction | (lrbp->command_type
  1941. << UPIU_COMMAND_TYPE_OFFSET);
  1942. if (lrbp->intr_cmd)
  1943. dword_0 |= UTP_REQ_DESC_INT_CMD;
  1944. /* Transfer request descriptor header fields */
  1945. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  1946. /* dword_1 is reserved, hence it is set to 0 */
  1947. req_desc->header.dword_1 = 0;
  1948. /*
  1949. * assigning invalid value for command status. Controller
  1950. * updates OCS on command completion, with the command
  1951. * status
  1952. */
  1953. req_desc->header.dword_2 =
  1954. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  1955. /* dword_3 is reserved, hence it is set to 0 */
  1956. req_desc->header.dword_3 = 0;
  1957. req_desc->prd_table_length = 0;
  1958. }
  1959. /**
  1960. * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
  1961. * for scsi commands
  1962. * @lrbp: local reference block pointer
  1963. * @upiu_flags: flags
  1964. */
  1965. static
  1966. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1967. {
  1968. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1969. unsigned short cdb_len;
  1970. /* command descriptor fields */
  1971. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1972. UPIU_TRANSACTION_COMMAND, upiu_flags,
  1973. lrbp->lun, lrbp->task_tag);
  1974. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1975. UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  1976. /* Total EHS length and Data segment length will be zero */
  1977. ucd_req_ptr->header.dword_2 = 0;
  1978. ucd_req_ptr->sc.exp_data_transfer_len =
  1979. cpu_to_be32(lrbp->cmd->sdb.length);
  1980. cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
  1981. memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
  1982. memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
  1983. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1984. }
  1985. /**
  1986. * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
  1987. * for query requsts
  1988. * @hba: UFS hba
  1989. * @lrbp: local reference block pointer
  1990. * @upiu_flags: flags
  1991. */
  1992. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  1993. struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1994. {
  1995. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1996. struct ufs_query *query = &hba->dev_cmd.query;
  1997. u16 len = be16_to_cpu(query->request.upiu_req.length);
  1998. u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
  1999. /* Query request header */
  2000. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  2001. UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
  2002. lrbp->lun, lrbp->task_tag);
  2003. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  2004. 0, query->request.query_func, 0, 0);
  2005. /* Data segment length only need for WRITE_DESC */
  2006. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  2007. ucd_req_ptr->header.dword_2 =
  2008. UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
  2009. else
  2010. ucd_req_ptr->header.dword_2 = 0;
  2011. /* Copy the Query Request buffer as is */
  2012. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
  2013. QUERY_OSF_SIZE);
  2014. /* Copy the Descriptor */
  2015. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  2016. memcpy(descp, query->descriptor, len);
  2017. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  2018. }
  2019. static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
  2020. {
  2021. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  2022. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  2023. /* command descriptor fields */
  2024. ucd_req_ptr->header.dword_0 =
  2025. UPIU_HEADER_DWORD(
  2026. UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
  2027. /* clear rest of the fields of basic header */
  2028. ucd_req_ptr->header.dword_1 = 0;
  2029. ucd_req_ptr->header.dword_2 = 0;
  2030. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  2031. }
  2032. /**
  2033. * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
  2034. * for Device Management Purposes
  2035. * @hba: per adapter instance
  2036. * @lrbp: pointer to local reference block
  2037. */
  2038. static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2039. {
  2040. u32 upiu_flags;
  2041. int ret = 0;
  2042. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  2043. (hba->ufs_version == UFSHCI_VERSION_11))
  2044. lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
  2045. else
  2046. lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
  2047. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
  2048. if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
  2049. ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
  2050. else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
  2051. ufshcd_prepare_utp_nop_upiu(lrbp);
  2052. else
  2053. ret = -EINVAL;
  2054. return ret;
  2055. }
  2056. /**
  2057. * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
  2058. * for SCSI Purposes
  2059. * @hba: per adapter instance
  2060. * @lrbp: pointer to local reference block
  2061. */
  2062. static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2063. {
  2064. u32 upiu_flags;
  2065. int ret = 0;
  2066. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  2067. (hba->ufs_version == UFSHCI_VERSION_11))
  2068. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  2069. else
  2070. lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
  2071. if (likely(lrbp->cmd)) {
  2072. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
  2073. lrbp->cmd->sc_data_direction);
  2074. ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
  2075. } else {
  2076. ret = -EINVAL;
  2077. }
  2078. return ret;
  2079. }
  2080. /**
  2081. * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
  2082. * @upiu_wlun_id: UPIU W-LUN id
  2083. *
  2084. * Returns SCSI W-LUN id
  2085. */
  2086. static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
  2087. {
  2088. return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
  2089. }
  2090. /**
  2091. * ufshcd_queuecommand - main entry point for SCSI requests
  2092. * @host: SCSI host pointer
  2093. * @cmd: command from SCSI Midlayer
  2094. *
  2095. * Returns 0 for success, non-zero in case of failure
  2096. */
  2097. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  2098. {
  2099. struct ufshcd_lrb *lrbp;
  2100. struct ufs_hba *hba;
  2101. unsigned long flags;
  2102. int tag;
  2103. int err = 0;
  2104. hba = shost_priv(host);
  2105. tag = cmd->request->tag;
  2106. if (!ufshcd_valid_tag(hba, tag)) {
  2107. dev_err(hba->dev,
  2108. "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
  2109. __func__, tag, cmd, cmd->request);
  2110. BUG();
  2111. }
  2112. if (!down_read_trylock(&hba->clk_scaling_lock))
  2113. return SCSI_MLQUEUE_HOST_BUSY;
  2114. spin_lock_irqsave(hba->host->host_lock, flags);
  2115. switch (hba->ufshcd_state) {
  2116. case UFSHCD_STATE_OPERATIONAL:
  2117. break;
  2118. case UFSHCD_STATE_EH_SCHEDULED:
  2119. case UFSHCD_STATE_RESET:
  2120. err = SCSI_MLQUEUE_HOST_BUSY;
  2121. goto out_unlock;
  2122. case UFSHCD_STATE_ERROR:
  2123. set_host_byte(cmd, DID_ERROR);
  2124. cmd->scsi_done(cmd);
  2125. goto out_unlock;
  2126. default:
  2127. dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
  2128. __func__, hba->ufshcd_state);
  2129. set_host_byte(cmd, DID_BAD_TARGET);
  2130. cmd->scsi_done(cmd);
  2131. goto out_unlock;
  2132. }
  2133. /* if error handling is in progress, don't issue commands */
  2134. if (ufshcd_eh_in_progress(hba)) {
  2135. set_host_byte(cmd, DID_ERROR);
  2136. cmd->scsi_done(cmd);
  2137. goto out_unlock;
  2138. }
  2139. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2140. hba->req_abort_count = 0;
  2141. /* acquire the tag to make sure device cmds don't use it */
  2142. if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
  2143. /*
  2144. * Dev manage command in progress, requeue the command.
  2145. * Requeuing the command helps in cases where the request *may*
  2146. * find different tag instead of waiting for dev manage command
  2147. * completion.
  2148. */
  2149. err = SCSI_MLQUEUE_HOST_BUSY;
  2150. goto out;
  2151. }
  2152. err = ufshcd_hold(hba, true);
  2153. if (err) {
  2154. err = SCSI_MLQUEUE_HOST_BUSY;
  2155. clear_bit_unlock(tag, &hba->lrb_in_use);
  2156. goto out;
  2157. }
  2158. WARN_ON(hba->clk_gating.state != CLKS_ON);
  2159. lrbp = &hba->lrb[tag];
  2160. WARN_ON(lrbp->cmd);
  2161. lrbp->cmd = cmd;
  2162. lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
  2163. lrbp->sense_buffer = cmd->sense_buffer;
  2164. lrbp->task_tag = tag;
  2165. lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
  2166. lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
  2167. lrbp->req_abort_skip = false;
  2168. ufshcd_comp_scsi_upiu(hba, lrbp);
  2169. err = ufshcd_map_sg(hba, lrbp);
  2170. if (err) {
  2171. ufshcd_release(hba);
  2172. lrbp->cmd = NULL;
  2173. clear_bit_unlock(tag, &hba->lrb_in_use);
  2174. goto out;
  2175. }
  2176. /* Make sure descriptors are ready before ringing the doorbell */
  2177. wmb();
  2178. /* issue command to the controller */
  2179. spin_lock_irqsave(hba->host->host_lock, flags);
  2180. ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
  2181. ufshcd_send_command(hba, tag);
  2182. out_unlock:
  2183. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2184. out:
  2185. up_read(&hba->clk_scaling_lock);
  2186. return err;
  2187. }
  2188. static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
  2189. struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
  2190. {
  2191. lrbp->cmd = NULL;
  2192. lrbp->sense_bufflen = 0;
  2193. lrbp->sense_buffer = NULL;
  2194. lrbp->task_tag = tag;
  2195. lrbp->lun = 0; /* device management cmd is not specific to any LUN */
  2196. lrbp->intr_cmd = true; /* No interrupt aggregation */
  2197. hba->dev_cmd.type = cmd_type;
  2198. return ufshcd_comp_devman_upiu(hba, lrbp);
  2199. }
  2200. static int
  2201. ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
  2202. {
  2203. int err = 0;
  2204. unsigned long flags;
  2205. u32 mask = 1 << tag;
  2206. /* clear outstanding transaction before retry */
  2207. spin_lock_irqsave(hba->host->host_lock, flags);
  2208. ufshcd_utrl_clear(hba, tag);
  2209. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2210. /*
  2211. * wait for for h/w to clear corresponding bit in door-bell.
  2212. * max. wait is 1 sec.
  2213. */
  2214. err = ufshcd_wait_for_register(hba,
  2215. REG_UTP_TRANSFER_REQ_DOOR_BELL,
  2216. mask, ~mask, 1000, 1000, true);
  2217. return err;
  2218. }
  2219. static int
  2220. ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2221. {
  2222. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  2223. /* Get the UPIU response */
  2224. query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
  2225. UPIU_RSP_CODE_OFFSET;
  2226. return query_res->response;
  2227. }
  2228. /**
  2229. * ufshcd_dev_cmd_completion() - handles device management command responses
  2230. * @hba: per adapter instance
  2231. * @lrbp: pointer to local reference block
  2232. */
  2233. static int
  2234. ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2235. {
  2236. int resp;
  2237. int err = 0;
  2238. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
  2239. resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  2240. switch (resp) {
  2241. case UPIU_TRANSACTION_NOP_IN:
  2242. if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
  2243. err = -EINVAL;
  2244. dev_err(hba->dev, "%s: unexpected response %x\n",
  2245. __func__, resp);
  2246. }
  2247. break;
  2248. case UPIU_TRANSACTION_QUERY_RSP:
  2249. err = ufshcd_check_query_response(hba, lrbp);
  2250. if (!err)
  2251. err = ufshcd_copy_query_response(hba, lrbp);
  2252. break;
  2253. case UPIU_TRANSACTION_REJECT_UPIU:
  2254. /* TODO: handle Reject UPIU Response */
  2255. err = -EPERM;
  2256. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  2257. __func__);
  2258. break;
  2259. default:
  2260. err = -EINVAL;
  2261. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  2262. __func__, resp);
  2263. break;
  2264. }
  2265. return err;
  2266. }
  2267. static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
  2268. struct ufshcd_lrb *lrbp, int max_timeout)
  2269. {
  2270. int err = 0;
  2271. unsigned long time_left;
  2272. unsigned long flags;
  2273. time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
  2274. msecs_to_jiffies(max_timeout));
  2275. /* Make sure descriptors are ready before ringing the doorbell */
  2276. wmb();
  2277. spin_lock_irqsave(hba->host->host_lock, flags);
  2278. hba->dev_cmd.complete = NULL;
  2279. if (likely(time_left)) {
  2280. err = ufshcd_get_tr_ocs(lrbp);
  2281. if (!err)
  2282. err = ufshcd_dev_cmd_completion(hba, lrbp);
  2283. }
  2284. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2285. if (!time_left) {
  2286. err = -ETIMEDOUT;
  2287. dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
  2288. __func__, lrbp->task_tag);
  2289. if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
  2290. /* successfully cleared the command, retry if needed */
  2291. err = -EAGAIN;
  2292. /*
  2293. * in case of an error, after clearing the doorbell,
  2294. * we also need to clear the outstanding_request
  2295. * field in hba
  2296. */
  2297. ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
  2298. }
  2299. return err;
  2300. }
  2301. /**
  2302. * ufshcd_get_dev_cmd_tag - Get device management command tag
  2303. * @hba: per-adapter instance
  2304. * @tag_out: pointer to variable with available slot value
  2305. *
  2306. * Get a free slot and lock it until device management command
  2307. * completes.
  2308. *
  2309. * Returns false if free slot is unavailable for locking, else
  2310. * return true with tag value in @tag.
  2311. */
  2312. static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
  2313. {
  2314. int tag;
  2315. bool ret = false;
  2316. unsigned long tmp;
  2317. if (!tag_out)
  2318. goto out;
  2319. do {
  2320. tmp = ~hba->lrb_in_use;
  2321. tag = find_last_bit(&tmp, hba->nutrs);
  2322. if (tag >= hba->nutrs)
  2323. goto out;
  2324. } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
  2325. *tag_out = tag;
  2326. ret = true;
  2327. out:
  2328. return ret;
  2329. }
  2330. static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
  2331. {
  2332. clear_bit_unlock(tag, &hba->lrb_in_use);
  2333. }
  2334. /**
  2335. * ufshcd_exec_dev_cmd - API for sending device management requests
  2336. * @hba: UFS hba
  2337. * @cmd_type: specifies the type (NOP, Query...)
  2338. * @timeout: time in seconds
  2339. *
  2340. * NOTE: Since there is only one available tag for device management commands,
  2341. * it is expected you hold the hba->dev_cmd.lock mutex.
  2342. */
  2343. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
  2344. enum dev_cmd_type cmd_type, int timeout)
  2345. {
  2346. struct ufshcd_lrb *lrbp;
  2347. int err;
  2348. int tag;
  2349. struct completion wait;
  2350. unsigned long flags;
  2351. down_read(&hba->clk_scaling_lock);
  2352. /*
  2353. * Get free slot, sleep if slots are unavailable.
  2354. * Even though we use wait_event() which sleeps indefinitely,
  2355. * the maximum wait time is bounded by SCSI request timeout.
  2356. */
  2357. wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
  2358. init_completion(&wait);
  2359. lrbp = &hba->lrb[tag];
  2360. WARN_ON(lrbp->cmd);
  2361. err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
  2362. if (unlikely(err))
  2363. goto out_put_tag;
  2364. hba->dev_cmd.complete = &wait;
  2365. ufshcd_add_query_upiu_trace(hba, tag, "query_send");
  2366. /* Make sure descriptors are ready before ringing the doorbell */
  2367. wmb();
  2368. spin_lock_irqsave(hba->host->host_lock, flags);
  2369. ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
  2370. ufshcd_send_command(hba, tag);
  2371. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2372. err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
  2373. ufshcd_add_query_upiu_trace(hba, tag,
  2374. err ? "query_complete_err" : "query_complete");
  2375. out_put_tag:
  2376. ufshcd_put_dev_cmd_tag(hba, tag);
  2377. wake_up(&hba->dev_cmd.tag_wq);
  2378. up_read(&hba->clk_scaling_lock);
  2379. return err;
  2380. }
  2381. /**
  2382. * ufshcd_init_query() - init the query response and request parameters
  2383. * @hba: per-adapter instance
  2384. * @request: address of the request pointer to be initialized
  2385. * @response: address of the response pointer to be initialized
  2386. * @opcode: operation to perform
  2387. * @idn: flag idn to access
  2388. * @index: LU number to access
  2389. * @selector: query/flag/descriptor further identification
  2390. */
  2391. static inline void ufshcd_init_query(struct ufs_hba *hba,
  2392. struct ufs_query_req **request, struct ufs_query_res **response,
  2393. enum query_opcode opcode, u8 idn, u8 index, u8 selector)
  2394. {
  2395. *request = &hba->dev_cmd.query.request;
  2396. *response = &hba->dev_cmd.query.response;
  2397. memset(*request, 0, sizeof(struct ufs_query_req));
  2398. memset(*response, 0, sizeof(struct ufs_query_res));
  2399. (*request)->upiu_req.opcode = opcode;
  2400. (*request)->upiu_req.idn = idn;
  2401. (*request)->upiu_req.index = index;
  2402. (*request)->upiu_req.selector = selector;
  2403. }
  2404. static int ufshcd_query_flag_retry(struct ufs_hba *hba,
  2405. enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
  2406. {
  2407. int ret;
  2408. int retries;
  2409. for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
  2410. ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
  2411. if (ret)
  2412. dev_dbg(hba->dev,
  2413. "%s: failed with error %d, retries %d\n",
  2414. __func__, ret, retries);
  2415. else
  2416. break;
  2417. }
  2418. if (ret)
  2419. dev_err(hba->dev,
  2420. "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
  2421. __func__, opcode, idn, ret, retries);
  2422. return ret;
  2423. }
  2424. /**
  2425. * ufshcd_query_flag() - API function for sending flag query requests
  2426. * @hba: per-adapter instance
  2427. * @opcode: flag query to perform
  2428. * @idn: flag idn to access
  2429. * @flag_res: the flag value after the query request completes
  2430. *
  2431. * Returns 0 for success, non-zero in case of failure
  2432. */
  2433. int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  2434. enum flag_idn idn, bool *flag_res)
  2435. {
  2436. struct ufs_query_req *request = NULL;
  2437. struct ufs_query_res *response = NULL;
  2438. int err, index = 0, selector = 0;
  2439. int timeout = QUERY_REQ_TIMEOUT;
  2440. BUG_ON(!hba);
  2441. ufshcd_hold(hba, false);
  2442. mutex_lock(&hba->dev_cmd.lock);
  2443. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  2444. selector);
  2445. switch (opcode) {
  2446. case UPIU_QUERY_OPCODE_SET_FLAG:
  2447. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  2448. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  2449. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  2450. break;
  2451. case UPIU_QUERY_OPCODE_READ_FLAG:
  2452. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  2453. if (!flag_res) {
  2454. /* No dummy reads */
  2455. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  2456. __func__);
  2457. err = -EINVAL;
  2458. goto out_unlock;
  2459. }
  2460. break;
  2461. default:
  2462. dev_err(hba->dev,
  2463. "%s: Expected query flag opcode but got = %d\n",
  2464. __func__, opcode);
  2465. err = -EINVAL;
  2466. goto out_unlock;
  2467. }
  2468. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
  2469. if (err) {
  2470. dev_err(hba->dev,
  2471. "%s: Sending flag query for idn %d failed, err = %d\n",
  2472. __func__, idn, err);
  2473. goto out_unlock;
  2474. }
  2475. if (flag_res)
  2476. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  2477. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  2478. out_unlock:
  2479. mutex_unlock(&hba->dev_cmd.lock);
  2480. ufshcd_release(hba);
  2481. return err;
  2482. }
  2483. /**
  2484. * ufshcd_query_attr - API function for sending attribute requests
  2485. * @hba: per-adapter instance
  2486. * @opcode: attribute opcode
  2487. * @idn: attribute idn to access
  2488. * @index: index field
  2489. * @selector: selector field
  2490. * @attr_val: the attribute value after the query request completes
  2491. *
  2492. * Returns 0 for success, non-zero in case of failure
  2493. */
  2494. int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
  2495. enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
  2496. {
  2497. struct ufs_query_req *request = NULL;
  2498. struct ufs_query_res *response = NULL;
  2499. int err;
  2500. BUG_ON(!hba);
  2501. ufshcd_hold(hba, false);
  2502. if (!attr_val) {
  2503. dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
  2504. __func__, opcode);
  2505. err = -EINVAL;
  2506. goto out;
  2507. }
  2508. mutex_lock(&hba->dev_cmd.lock);
  2509. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  2510. selector);
  2511. switch (opcode) {
  2512. case UPIU_QUERY_OPCODE_WRITE_ATTR:
  2513. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  2514. request->upiu_req.value = cpu_to_be32(*attr_val);
  2515. break;
  2516. case UPIU_QUERY_OPCODE_READ_ATTR:
  2517. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  2518. break;
  2519. default:
  2520. dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
  2521. __func__, opcode);
  2522. err = -EINVAL;
  2523. goto out_unlock;
  2524. }
  2525. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  2526. if (err) {
  2527. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
  2528. __func__, opcode, idn, index, err);
  2529. goto out_unlock;
  2530. }
  2531. *attr_val = be32_to_cpu(response->upiu_res.value);
  2532. out_unlock:
  2533. mutex_unlock(&hba->dev_cmd.lock);
  2534. out:
  2535. ufshcd_release(hba);
  2536. return err;
  2537. }
  2538. /**
  2539. * ufshcd_query_attr_retry() - API function for sending query
  2540. * attribute with retries
  2541. * @hba: per-adapter instance
  2542. * @opcode: attribute opcode
  2543. * @idn: attribute idn to access
  2544. * @index: index field
  2545. * @selector: selector field
  2546. * @attr_val: the attribute value after the query request
  2547. * completes
  2548. *
  2549. * Returns 0 for success, non-zero in case of failure
  2550. */
  2551. static int ufshcd_query_attr_retry(struct ufs_hba *hba,
  2552. enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
  2553. u32 *attr_val)
  2554. {
  2555. int ret = 0;
  2556. u32 retries;
  2557. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2558. ret = ufshcd_query_attr(hba, opcode, idn, index,
  2559. selector, attr_val);
  2560. if (ret)
  2561. dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
  2562. __func__, ret, retries);
  2563. else
  2564. break;
  2565. }
  2566. if (ret)
  2567. dev_err(hba->dev,
  2568. "%s: query attribute, idn %d, failed with error %d after %d retires\n",
  2569. __func__, idn, ret, QUERY_REQ_RETRIES);
  2570. return ret;
  2571. }
  2572. static int __ufshcd_query_descriptor(struct ufs_hba *hba,
  2573. enum query_opcode opcode, enum desc_idn idn, u8 index,
  2574. u8 selector, u8 *desc_buf, int *buf_len)
  2575. {
  2576. struct ufs_query_req *request = NULL;
  2577. struct ufs_query_res *response = NULL;
  2578. int err;
  2579. BUG_ON(!hba);
  2580. ufshcd_hold(hba, false);
  2581. if (!desc_buf) {
  2582. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  2583. __func__, opcode);
  2584. err = -EINVAL;
  2585. goto out;
  2586. }
  2587. if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  2588. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  2589. __func__, *buf_len);
  2590. err = -EINVAL;
  2591. goto out;
  2592. }
  2593. mutex_lock(&hba->dev_cmd.lock);
  2594. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  2595. selector);
  2596. hba->dev_cmd.query.descriptor = desc_buf;
  2597. request->upiu_req.length = cpu_to_be16(*buf_len);
  2598. switch (opcode) {
  2599. case UPIU_QUERY_OPCODE_WRITE_DESC:
  2600. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  2601. break;
  2602. case UPIU_QUERY_OPCODE_READ_DESC:
  2603. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  2604. break;
  2605. default:
  2606. dev_err(hba->dev,
  2607. "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  2608. __func__, opcode);
  2609. err = -EINVAL;
  2610. goto out_unlock;
  2611. }
  2612. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  2613. if (err) {
  2614. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
  2615. __func__, opcode, idn, index, err);
  2616. goto out_unlock;
  2617. }
  2618. *buf_len = be16_to_cpu(response->upiu_res.length);
  2619. out_unlock:
  2620. hba->dev_cmd.query.descriptor = NULL;
  2621. mutex_unlock(&hba->dev_cmd.lock);
  2622. out:
  2623. ufshcd_release(hba);
  2624. return err;
  2625. }
  2626. /**
  2627. * ufshcd_query_descriptor_retry - API function for sending descriptor requests
  2628. * @hba: per-adapter instance
  2629. * @opcode: attribute opcode
  2630. * @idn: attribute idn to access
  2631. * @index: index field
  2632. * @selector: selector field
  2633. * @desc_buf: the buffer that contains the descriptor
  2634. * @buf_len: length parameter passed to the device
  2635. *
  2636. * Returns 0 for success, non-zero in case of failure.
  2637. * The buf_len parameter will contain, on return, the length parameter
  2638. * received on the response.
  2639. */
  2640. int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
  2641. enum query_opcode opcode,
  2642. enum desc_idn idn, u8 index,
  2643. u8 selector,
  2644. u8 *desc_buf, int *buf_len)
  2645. {
  2646. int err;
  2647. int retries;
  2648. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2649. err = __ufshcd_query_descriptor(hba, opcode, idn, index,
  2650. selector, desc_buf, buf_len);
  2651. if (!err || err == -EINVAL)
  2652. break;
  2653. }
  2654. return err;
  2655. }
  2656. /**
  2657. * ufshcd_read_desc_length - read the specified descriptor length from header
  2658. * @hba: Pointer to adapter instance
  2659. * @desc_id: descriptor idn value
  2660. * @desc_index: descriptor index
  2661. * @desc_length: pointer to variable to read the length of descriptor
  2662. *
  2663. * Return 0 in case of success, non-zero otherwise
  2664. */
  2665. static int ufshcd_read_desc_length(struct ufs_hba *hba,
  2666. enum desc_idn desc_id,
  2667. int desc_index,
  2668. int *desc_length)
  2669. {
  2670. int ret;
  2671. u8 header[QUERY_DESC_HDR_SIZE];
  2672. int header_len = QUERY_DESC_HDR_SIZE;
  2673. if (desc_id >= QUERY_DESC_IDN_MAX)
  2674. return -EINVAL;
  2675. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  2676. desc_id, desc_index, 0, header,
  2677. &header_len);
  2678. if (ret) {
  2679. dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
  2680. __func__, desc_id);
  2681. return ret;
  2682. } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
  2683. dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
  2684. __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
  2685. desc_id);
  2686. ret = -EINVAL;
  2687. }
  2688. *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
  2689. return ret;
  2690. }
  2691. /**
  2692. * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
  2693. * @hba: Pointer to adapter instance
  2694. * @desc_id: descriptor idn value
  2695. * @desc_len: mapped desc length (out)
  2696. *
  2697. * Return 0 in case of success, non-zero otherwise
  2698. */
  2699. int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
  2700. enum desc_idn desc_id, int *desc_len)
  2701. {
  2702. switch (desc_id) {
  2703. case QUERY_DESC_IDN_DEVICE:
  2704. *desc_len = hba->desc_size.dev_desc;
  2705. break;
  2706. case QUERY_DESC_IDN_POWER:
  2707. *desc_len = hba->desc_size.pwr_desc;
  2708. break;
  2709. case QUERY_DESC_IDN_GEOMETRY:
  2710. *desc_len = hba->desc_size.geom_desc;
  2711. break;
  2712. case QUERY_DESC_IDN_CONFIGURATION:
  2713. *desc_len = hba->desc_size.conf_desc;
  2714. break;
  2715. case QUERY_DESC_IDN_UNIT:
  2716. *desc_len = hba->desc_size.unit_desc;
  2717. break;
  2718. case QUERY_DESC_IDN_INTERCONNECT:
  2719. *desc_len = hba->desc_size.interc_desc;
  2720. break;
  2721. case QUERY_DESC_IDN_STRING:
  2722. *desc_len = QUERY_DESC_MAX_SIZE;
  2723. break;
  2724. case QUERY_DESC_IDN_HEALTH:
  2725. *desc_len = hba->desc_size.hlth_desc;
  2726. break;
  2727. case QUERY_DESC_IDN_RFU_0:
  2728. case QUERY_DESC_IDN_RFU_1:
  2729. *desc_len = 0;
  2730. break;
  2731. default:
  2732. *desc_len = 0;
  2733. return -EINVAL;
  2734. }
  2735. return 0;
  2736. }
  2737. EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
  2738. /**
  2739. * ufshcd_read_desc_param - read the specified descriptor parameter
  2740. * @hba: Pointer to adapter instance
  2741. * @desc_id: descriptor idn value
  2742. * @desc_index: descriptor index
  2743. * @param_offset: offset of the parameter to read
  2744. * @param_read_buf: pointer to buffer where parameter would be read
  2745. * @param_size: sizeof(param_read_buf)
  2746. *
  2747. * Return 0 in case of success, non-zero otherwise
  2748. */
  2749. int ufshcd_read_desc_param(struct ufs_hba *hba,
  2750. enum desc_idn desc_id,
  2751. int desc_index,
  2752. u8 param_offset,
  2753. u8 *param_read_buf,
  2754. u8 param_size)
  2755. {
  2756. int ret;
  2757. u8 *desc_buf;
  2758. int buff_len;
  2759. bool is_kmalloc = true;
  2760. /* Safety check */
  2761. if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
  2762. return -EINVAL;
  2763. /* Get the max length of descriptor from structure filled up at probe
  2764. * time.
  2765. */
  2766. ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
  2767. /* Sanity checks */
  2768. if (ret || !buff_len) {
  2769. dev_err(hba->dev, "%s: Failed to get full descriptor length",
  2770. __func__);
  2771. return ret;
  2772. }
  2773. /* Check whether we need temp memory */
  2774. if (param_offset != 0 || param_size < buff_len) {
  2775. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  2776. if (!desc_buf)
  2777. return -ENOMEM;
  2778. } else {
  2779. desc_buf = param_read_buf;
  2780. is_kmalloc = false;
  2781. }
  2782. /* Request for full descriptor */
  2783. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  2784. desc_id, desc_index, 0,
  2785. desc_buf, &buff_len);
  2786. if (ret) {
  2787. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
  2788. __func__, desc_id, desc_index, param_offset, ret);
  2789. goto out;
  2790. }
  2791. /* Sanity check */
  2792. if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
  2793. dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
  2794. __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
  2795. ret = -EINVAL;
  2796. goto out;
  2797. }
  2798. /* Check wherher we will not copy more data, than available */
  2799. if (is_kmalloc && param_size > buff_len)
  2800. param_size = buff_len;
  2801. if (is_kmalloc)
  2802. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  2803. out:
  2804. if (is_kmalloc)
  2805. kfree(desc_buf);
  2806. return ret;
  2807. }
  2808. static inline int ufshcd_read_desc(struct ufs_hba *hba,
  2809. enum desc_idn desc_id,
  2810. int desc_index,
  2811. u8 *buf,
  2812. u32 size)
  2813. {
  2814. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  2815. }
  2816. static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
  2817. u8 *buf,
  2818. u32 size)
  2819. {
  2820. return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
  2821. }
  2822. static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
  2823. {
  2824. return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
  2825. }
  2826. /**
  2827. * ufshcd_read_string_desc - read string descriptor
  2828. * @hba: pointer to adapter instance
  2829. * @desc_index: descriptor index
  2830. * @buf: pointer to buffer where descriptor would be read
  2831. * @size: size of buf
  2832. * @ascii: if true convert from unicode to ascii characters
  2833. *
  2834. * Return 0 in case of success, non-zero otherwise
  2835. */
  2836. int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
  2837. u8 *buf, u32 size, bool ascii)
  2838. {
  2839. int err = 0;
  2840. err = ufshcd_read_desc(hba,
  2841. QUERY_DESC_IDN_STRING, desc_index, buf, size);
  2842. if (err) {
  2843. dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
  2844. __func__, QUERY_REQ_RETRIES, err);
  2845. goto out;
  2846. }
  2847. if (ascii) {
  2848. int desc_len;
  2849. int ascii_len;
  2850. int i;
  2851. char *buff_ascii;
  2852. desc_len = buf[0];
  2853. /* remove header and divide by 2 to move from UTF16 to UTF8 */
  2854. ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
  2855. if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
  2856. dev_err(hba->dev, "%s: buffer allocated size is too small\n",
  2857. __func__);
  2858. err = -ENOMEM;
  2859. goto out;
  2860. }
  2861. buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
  2862. if (!buff_ascii) {
  2863. err = -ENOMEM;
  2864. goto out;
  2865. }
  2866. /*
  2867. * the descriptor contains string in UTF16 format
  2868. * we need to convert to utf-8 so it can be displayed
  2869. */
  2870. utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
  2871. desc_len - QUERY_DESC_HDR_SIZE,
  2872. UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
  2873. /* replace non-printable or non-ASCII characters with spaces */
  2874. for (i = 0; i < ascii_len; i++)
  2875. ufshcd_remove_non_printable(&buff_ascii[i]);
  2876. memset(buf + QUERY_DESC_HDR_SIZE, 0,
  2877. size - QUERY_DESC_HDR_SIZE);
  2878. memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
  2879. buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
  2880. kfree(buff_ascii);
  2881. }
  2882. out:
  2883. return err;
  2884. }
  2885. /**
  2886. * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
  2887. * @hba: Pointer to adapter instance
  2888. * @lun: lun id
  2889. * @param_offset: offset of the parameter to read
  2890. * @param_read_buf: pointer to buffer where parameter would be read
  2891. * @param_size: sizeof(param_read_buf)
  2892. *
  2893. * Return 0 in case of success, non-zero otherwise
  2894. */
  2895. static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
  2896. int lun,
  2897. enum unit_desc_param param_offset,
  2898. u8 *param_read_buf,
  2899. u32 param_size)
  2900. {
  2901. /*
  2902. * Unit descriptors are only available for general purpose LUs (LUN id
  2903. * from 0 to 7) and RPMB Well known LU.
  2904. */
  2905. if (!ufs_is_valid_unit_desc_lun(lun))
  2906. return -EOPNOTSUPP;
  2907. return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
  2908. param_offset, param_read_buf, param_size);
  2909. }
  2910. /**
  2911. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  2912. * @hba: per adapter instance
  2913. *
  2914. * 1. Allocate DMA memory for Command Descriptor array
  2915. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  2916. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  2917. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  2918. * (UTMRDL)
  2919. * 4. Allocate memory for local reference block(lrb).
  2920. *
  2921. * Returns 0 for success, non-zero in case of failure
  2922. */
  2923. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  2924. {
  2925. size_t utmrdl_size, utrdl_size, ucdl_size;
  2926. /* Allocate memory for UTP command descriptors */
  2927. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  2928. hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
  2929. ucdl_size,
  2930. &hba->ucdl_dma_addr,
  2931. GFP_KERNEL);
  2932. /*
  2933. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  2934. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  2935. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  2936. * be aligned to 128 bytes as well
  2937. */
  2938. if (!hba->ucdl_base_addr ||
  2939. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  2940. dev_err(hba->dev,
  2941. "Command Descriptor Memory allocation failed\n");
  2942. goto out;
  2943. }
  2944. /*
  2945. * Allocate memory for UTP Transfer descriptors
  2946. * UFSHCI requires 1024 byte alignment of UTRD
  2947. */
  2948. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  2949. hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
  2950. utrdl_size,
  2951. &hba->utrdl_dma_addr,
  2952. GFP_KERNEL);
  2953. if (!hba->utrdl_base_addr ||
  2954. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  2955. dev_err(hba->dev,
  2956. "Transfer Descriptor Memory allocation failed\n");
  2957. goto out;
  2958. }
  2959. /*
  2960. * Allocate memory for UTP Task Management descriptors
  2961. * UFSHCI requires 1024 byte alignment of UTMRD
  2962. */
  2963. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  2964. hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
  2965. utmrdl_size,
  2966. &hba->utmrdl_dma_addr,
  2967. GFP_KERNEL);
  2968. if (!hba->utmrdl_base_addr ||
  2969. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  2970. dev_err(hba->dev,
  2971. "Task Management Descriptor Memory allocation failed\n");
  2972. goto out;
  2973. }
  2974. /* Allocate memory for local reference block */
  2975. hba->lrb = devm_kcalloc(hba->dev,
  2976. hba->nutrs, sizeof(struct ufshcd_lrb),
  2977. GFP_KERNEL);
  2978. if (!hba->lrb) {
  2979. dev_err(hba->dev, "LRB Memory allocation failed\n");
  2980. goto out;
  2981. }
  2982. return 0;
  2983. out:
  2984. return -ENOMEM;
  2985. }
  2986. /**
  2987. * ufshcd_host_memory_configure - configure local reference block with
  2988. * memory offsets
  2989. * @hba: per adapter instance
  2990. *
  2991. * Configure Host memory space
  2992. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  2993. * address.
  2994. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  2995. * and PRDT offset.
  2996. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  2997. * into local reference block.
  2998. */
  2999. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  3000. {
  3001. struct utp_transfer_cmd_desc *cmd_descp;
  3002. struct utp_transfer_req_desc *utrdlp;
  3003. dma_addr_t cmd_desc_dma_addr;
  3004. dma_addr_t cmd_desc_element_addr;
  3005. u16 response_offset;
  3006. u16 prdt_offset;
  3007. int cmd_desc_size;
  3008. int i;
  3009. utrdlp = hba->utrdl_base_addr;
  3010. cmd_descp = hba->ucdl_base_addr;
  3011. response_offset =
  3012. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  3013. prdt_offset =
  3014. offsetof(struct utp_transfer_cmd_desc, prd_table);
  3015. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  3016. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  3017. for (i = 0; i < hba->nutrs; i++) {
  3018. /* Configure UTRD with command descriptor base address */
  3019. cmd_desc_element_addr =
  3020. (cmd_desc_dma_addr + (cmd_desc_size * i));
  3021. utrdlp[i].command_desc_base_addr_lo =
  3022. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  3023. utrdlp[i].command_desc_base_addr_hi =
  3024. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  3025. /* Response upiu and prdt offset should be in double words */
  3026. if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
  3027. utrdlp[i].response_upiu_offset =
  3028. cpu_to_le16(response_offset);
  3029. utrdlp[i].prd_table_offset =
  3030. cpu_to_le16(prdt_offset);
  3031. utrdlp[i].response_upiu_length =
  3032. cpu_to_le16(ALIGNED_UPIU_SIZE);
  3033. } else {
  3034. utrdlp[i].response_upiu_offset =
  3035. cpu_to_le16((response_offset >> 2));
  3036. utrdlp[i].prd_table_offset =
  3037. cpu_to_le16((prdt_offset >> 2));
  3038. utrdlp[i].response_upiu_length =
  3039. cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  3040. }
  3041. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  3042. hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
  3043. (i * sizeof(struct utp_transfer_req_desc));
  3044. hba->lrb[i].ucd_req_ptr =
  3045. (struct utp_upiu_req *)(cmd_descp + i);
  3046. hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
  3047. hba->lrb[i].ucd_rsp_ptr =
  3048. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  3049. hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
  3050. response_offset;
  3051. hba->lrb[i].ucd_prdt_ptr =
  3052. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  3053. hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
  3054. prdt_offset;
  3055. }
  3056. }
  3057. /**
  3058. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  3059. * @hba: per adapter instance
  3060. *
  3061. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  3062. * in order to initialize the Unipro link startup procedure.
  3063. * Once the Unipro links are up, the device connected to the controller
  3064. * is detected.
  3065. *
  3066. * Returns 0 on success, non-zero value on failure
  3067. */
  3068. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  3069. {
  3070. struct uic_command uic_cmd = {0};
  3071. int ret;
  3072. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  3073. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3074. if (ret)
  3075. dev_dbg(hba->dev,
  3076. "dme-link-startup: error code %d\n", ret);
  3077. return ret;
  3078. }
  3079. /**
  3080. * ufshcd_dme_reset - UIC command for DME_RESET
  3081. * @hba: per adapter instance
  3082. *
  3083. * DME_RESET command is issued in order to reset UniPro stack.
  3084. * This function now deal with cold reset.
  3085. *
  3086. * Returns 0 on success, non-zero value on failure
  3087. */
  3088. static int ufshcd_dme_reset(struct ufs_hba *hba)
  3089. {
  3090. struct uic_command uic_cmd = {0};
  3091. int ret;
  3092. uic_cmd.command = UIC_CMD_DME_RESET;
  3093. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3094. if (ret)
  3095. dev_err(hba->dev,
  3096. "dme-reset: error code %d\n", ret);
  3097. return ret;
  3098. }
  3099. /**
  3100. * ufshcd_dme_enable - UIC command for DME_ENABLE
  3101. * @hba: per adapter instance
  3102. *
  3103. * DME_ENABLE command is issued in order to enable UniPro stack.
  3104. *
  3105. * Returns 0 on success, non-zero value on failure
  3106. */
  3107. static int ufshcd_dme_enable(struct ufs_hba *hba)
  3108. {
  3109. struct uic_command uic_cmd = {0};
  3110. int ret;
  3111. uic_cmd.command = UIC_CMD_DME_ENABLE;
  3112. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3113. if (ret)
  3114. dev_err(hba->dev,
  3115. "dme-enable: error code %d\n", ret);
  3116. return ret;
  3117. }
  3118. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
  3119. {
  3120. #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
  3121. unsigned long min_sleep_time_us;
  3122. if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
  3123. return;
  3124. /*
  3125. * last_dme_cmd_tstamp will be 0 only for 1st call to
  3126. * this function
  3127. */
  3128. if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
  3129. min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
  3130. } else {
  3131. unsigned long delta =
  3132. (unsigned long) ktime_to_us(
  3133. ktime_sub(ktime_get(),
  3134. hba->last_dme_cmd_tstamp));
  3135. if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
  3136. min_sleep_time_us =
  3137. MIN_DELAY_BEFORE_DME_CMDS_US - delta;
  3138. else
  3139. return; /* no more delay required */
  3140. }
  3141. /* allow sleep for extra 50us if needed */
  3142. usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
  3143. }
  3144. /**
  3145. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  3146. * @hba: per adapter instance
  3147. * @attr_sel: uic command argument1
  3148. * @attr_set: attribute set type as uic command argument2
  3149. * @mib_val: setting value as uic command argument3
  3150. * @peer: indicate whether peer or local
  3151. *
  3152. * Returns 0 on success, non-zero value on failure
  3153. */
  3154. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  3155. u8 attr_set, u32 mib_val, u8 peer)
  3156. {
  3157. struct uic_command uic_cmd = {0};
  3158. static const char *const action[] = {
  3159. "dme-set",
  3160. "dme-peer-set"
  3161. };
  3162. const char *set = action[!!peer];
  3163. int ret;
  3164. int retries = UFS_UIC_COMMAND_RETRIES;
  3165. uic_cmd.command = peer ?
  3166. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  3167. uic_cmd.argument1 = attr_sel;
  3168. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  3169. uic_cmd.argument3 = mib_val;
  3170. do {
  3171. /* for peer attributes we retry upon failure */
  3172. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3173. if (ret)
  3174. dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  3175. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  3176. } while (ret && peer && --retries);
  3177. if (ret)
  3178. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
  3179. set, UIC_GET_ATTR_ID(attr_sel), mib_val,
  3180. UFS_UIC_COMMAND_RETRIES - retries);
  3181. return ret;
  3182. }
  3183. EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
  3184. /**
  3185. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  3186. * @hba: per adapter instance
  3187. * @attr_sel: uic command argument1
  3188. * @mib_val: the value of the attribute as returned by the UIC command
  3189. * @peer: indicate whether peer or local
  3190. *
  3191. * Returns 0 on success, non-zero value on failure
  3192. */
  3193. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  3194. u32 *mib_val, u8 peer)
  3195. {
  3196. struct uic_command uic_cmd = {0};
  3197. static const char *const action[] = {
  3198. "dme-get",
  3199. "dme-peer-get"
  3200. };
  3201. const char *get = action[!!peer];
  3202. int ret;
  3203. int retries = UFS_UIC_COMMAND_RETRIES;
  3204. struct ufs_pa_layer_attr orig_pwr_info;
  3205. struct ufs_pa_layer_attr temp_pwr_info;
  3206. bool pwr_mode_change = false;
  3207. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
  3208. orig_pwr_info = hba->pwr_info;
  3209. temp_pwr_info = orig_pwr_info;
  3210. if (orig_pwr_info.pwr_tx == FAST_MODE ||
  3211. orig_pwr_info.pwr_rx == FAST_MODE) {
  3212. temp_pwr_info.pwr_tx = FASTAUTO_MODE;
  3213. temp_pwr_info.pwr_rx = FASTAUTO_MODE;
  3214. pwr_mode_change = true;
  3215. } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
  3216. orig_pwr_info.pwr_rx == SLOW_MODE) {
  3217. temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
  3218. temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
  3219. pwr_mode_change = true;
  3220. }
  3221. if (pwr_mode_change) {
  3222. ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
  3223. if (ret)
  3224. goto out;
  3225. }
  3226. }
  3227. uic_cmd.command = peer ?
  3228. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  3229. uic_cmd.argument1 = attr_sel;
  3230. do {
  3231. /* for peer attributes we retry upon failure */
  3232. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3233. if (ret)
  3234. dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
  3235. get, UIC_GET_ATTR_ID(attr_sel), ret);
  3236. } while (ret && peer && --retries);
  3237. if (ret)
  3238. dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
  3239. get, UIC_GET_ATTR_ID(attr_sel),
  3240. UFS_UIC_COMMAND_RETRIES - retries);
  3241. if (mib_val && !ret)
  3242. *mib_val = uic_cmd.argument3;
  3243. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
  3244. && pwr_mode_change)
  3245. ufshcd_change_power_mode(hba, &orig_pwr_info);
  3246. out:
  3247. return ret;
  3248. }
  3249. EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
  3250. /**
  3251. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  3252. * state) and waits for it to take effect.
  3253. *
  3254. * @hba: per adapter instance
  3255. * @cmd: UIC command to execute
  3256. *
  3257. * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
  3258. * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
  3259. * and device UniPro link and hence it's final completion would be indicated by
  3260. * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
  3261. * addition to normal UIC command completion Status (UCCS). This function only
  3262. * returns after the relevant status bits indicate the completion.
  3263. *
  3264. * Returns 0 on success, non-zero value on failure
  3265. */
  3266. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  3267. {
  3268. struct completion uic_async_done;
  3269. unsigned long flags;
  3270. u8 status;
  3271. int ret;
  3272. bool reenable_intr = false;
  3273. mutex_lock(&hba->uic_cmd_mutex);
  3274. init_completion(&uic_async_done);
  3275. ufshcd_add_delay_before_dme_cmd(hba);
  3276. spin_lock_irqsave(hba->host->host_lock, flags);
  3277. hba->uic_async_done = &uic_async_done;
  3278. if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
  3279. ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
  3280. /*
  3281. * Make sure UIC command completion interrupt is disabled before
  3282. * issuing UIC command.
  3283. */
  3284. wmb();
  3285. reenable_intr = true;
  3286. }
  3287. ret = __ufshcd_send_uic_cmd(hba, cmd, false);
  3288. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3289. if (ret) {
  3290. dev_err(hba->dev,
  3291. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  3292. cmd->command, cmd->argument3, ret);
  3293. goto out;
  3294. }
  3295. if (!wait_for_completion_timeout(hba->uic_async_done,
  3296. msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
  3297. dev_err(hba->dev,
  3298. "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
  3299. cmd->command, cmd->argument3);
  3300. ret = -ETIMEDOUT;
  3301. goto out;
  3302. }
  3303. status = ufshcd_get_upmcrs(hba);
  3304. if (status != PWR_LOCAL) {
  3305. dev_err(hba->dev,
  3306. "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
  3307. cmd->command, status);
  3308. ret = (status != PWR_OK) ? status : -1;
  3309. }
  3310. out:
  3311. if (ret) {
  3312. ufshcd_print_host_state(hba);
  3313. ufshcd_print_pwr_info(hba);
  3314. ufshcd_print_host_regs(hba);
  3315. }
  3316. spin_lock_irqsave(hba->host->host_lock, flags);
  3317. hba->active_uic_cmd = NULL;
  3318. hba->uic_async_done = NULL;
  3319. if (reenable_intr)
  3320. ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
  3321. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3322. mutex_unlock(&hba->uic_cmd_mutex);
  3323. return ret;
  3324. }
  3325. /**
  3326. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
  3327. * using DME_SET primitives.
  3328. * @hba: per adapter instance
  3329. * @mode: powr mode value
  3330. *
  3331. * Returns 0 on success, non-zero value on failure
  3332. */
  3333. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  3334. {
  3335. struct uic_command uic_cmd = {0};
  3336. int ret;
  3337. if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
  3338. ret = ufshcd_dme_set(hba,
  3339. UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
  3340. if (ret) {
  3341. dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
  3342. __func__, ret);
  3343. goto out;
  3344. }
  3345. }
  3346. uic_cmd.command = UIC_CMD_DME_SET;
  3347. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  3348. uic_cmd.argument3 = mode;
  3349. ufshcd_hold(hba, false);
  3350. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  3351. ufshcd_release(hba);
  3352. out:
  3353. return ret;
  3354. }
  3355. static int ufshcd_link_recovery(struct ufs_hba *hba)
  3356. {
  3357. int ret;
  3358. unsigned long flags;
  3359. spin_lock_irqsave(hba->host->host_lock, flags);
  3360. hba->ufshcd_state = UFSHCD_STATE_RESET;
  3361. ufshcd_set_eh_in_progress(hba);
  3362. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3363. ret = ufshcd_host_reset_and_restore(hba);
  3364. spin_lock_irqsave(hba->host->host_lock, flags);
  3365. if (ret)
  3366. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3367. ufshcd_clear_eh_in_progress(hba);
  3368. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3369. if (ret)
  3370. dev_err(hba->dev, "%s: link recovery failed, err %d",
  3371. __func__, ret);
  3372. return ret;
  3373. }
  3374. static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  3375. {
  3376. int ret;
  3377. struct uic_command uic_cmd = {0};
  3378. ktime_t start = ktime_get();
  3379. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
  3380. uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
  3381. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  3382. trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
  3383. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  3384. if (ret) {
  3385. int err;
  3386. dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
  3387. __func__, ret);
  3388. /*
  3389. * If link recovery fails then return error code returned from
  3390. * ufshcd_link_recovery().
  3391. * If link recovery succeeds then return -EAGAIN to attempt
  3392. * hibern8 enter retry again.
  3393. */
  3394. err = ufshcd_link_recovery(hba);
  3395. if (err) {
  3396. dev_err(hba->dev, "%s: link recovery failed", __func__);
  3397. ret = err;
  3398. } else {
  3399. ret = -EAGAIN;
  3400. }
  3401. } else
  3402. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
  3403. POST_CHANGE);
  3404. return ret;
  3405. }
  3406. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  3407. {
  3408. int ret = 0, retries;
  3409. for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
  3410. ret = __ufshcd_uic_hibern8_enter(hba);
  3411. if (!ret)
  3412. goto out;
  3413. }
  3414. out:
  3415. return ret;
  3416. }
  3417. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
  3418. {
  3419. struct uic_command uic_cmd = {0};
  3420. int ret;
  3421. ktime_t start = ktime_get();
  3422. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
  3423. uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
  3424. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  3425. trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
  3426. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  3427. if (ret) {
  3428. dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
  3429. __func__, ret);
  3430. ret = ufshcd_link_recovery(hba);
  3431. } else {
  3432. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
  3433. POST_CHANGE);
  3434. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
  3435. hba->ufs_stats.hibern8_exit_cnt++;
  3436. }
  3437. return ret;
  3438. }
  3439. static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
  3440. {
  3441. unsigned long flags;
  3442. if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) || !hba->ahit)
  3443. return;
  3444. spin_lock_irqsave(hba->host->host_lock, flags);
  3445. ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
  3446. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3447. }
  3448. /**
  3449. * ufshcd_init_pwr_info - setting the POR (power on reset)
  3450. * values in hba power info
  3451. * @hba: per-adapter instance
  3452. */
  3453. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  3454. {
  3455. hba->pwr_info.gear_rx = UFS_PWM_G1;
  3456. hba->pwr_info.gear_tx = UFS_PWM_G1;
  3457. hba->pwr_info.lane_rx = 1;
  3458. hba->pwr_info.lane_tx = 1;
  3459. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  3460. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  3461. hba->pwr_info.hs_rate = 0;
  3462. }
  3463. /**
  3464. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  3465. * @hba: per-adapter instance
  3466. */
  3467. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  3468. {
  3469. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  3470. if (hba->max_pwr_info.is_valid)
  3471. return 0;
  3472. pwr_info->pwr_tx = FAST_MODE;
  3473. pwr_info->pwr_rx = FAST_MODE;
  3474. pwr_info->hs_rate = PA_HS_MODE_B;
  3475. /* Get the connected lane count */
  3476. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  3477. &pwr_info->lane_rx);
  3478. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  3479. &pwr_info->lane_tx);
  3480. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  3481. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  3482. __func__,
  3483. pwr_info->lane_rx,
  3484. pwr_info->lane_tx);
  3485. return -EINVAL;
  3486. }
  3487. /*
  3488. * First, get the maximum gears of HS speed.
  3489. * If a zero value, it means there is no HSGEAR capability.
  3490. * Then, get the maximum gears of PWM speed.
  3491. */
  3492. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  3493. if (!pwr_info->gear_rx) {
  3494. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  3495. &pwr_info->gear_rx);
  3496. if (!pwr_info->gear_rx) {
  3497. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  3498. __func__, pwr_info->gear_rx);
  3499. return -EINVAL;
  3500. }
  3501. pwr_info->pwr_rx = SLOW_MODE;
  3502. }
  3503. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  3504. &pwr_info->gear_tx);
  3505. if (!pwr_info->gear_tx) {
  3506. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  3507. &pwr_info->gear_tx);
  3508. if (!pwr_info->gear_tx) {
  3509. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  3510. __func__, pwr_info->gear_tx);
  3511. return -EINVAL;
  3512. }
  3513. pwr_info->pwr_tx = SLOW_MODE;
  3514. }
  3515. hba->max_pwr_info.is_valid = true;
  3516. return 0;
  3517. }
  3518. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  3519. struct ufs_pa_layer_attr *pwr_mode)
  3520. {
  3521. int ret;
  3522. /* if already configured to the requested pwr_mode */
  3523. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  3524. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  3525. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  3526. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  3527. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  3528. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  3529. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  3530. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  3531. return 0;
  3532. }
  3533. /*
  3534. * Configure attributes for power mode change with below.
  3535. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  3536. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  3537. * - PA_HSSERIES
  3538. */
  3539. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  3540. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  3541. pwr_mode->lane_rx);
  3542. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  3543. pwr_mode->pwr_rx == FAST_MODE)
  3544. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  3545. else
  3546. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  3547. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  3548. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  3549. pwr_mode->lane_tx);
  3550. if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
  3551. pwr_mode->pwr_tx == FAST_MODE)
  3552. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  3553. else
  3554. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  3555. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  3556. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  3557. pwr_mode->pwr_rx == FAST_MODE ||
  3558. pwr_mode->pwr_tx == FAST_MODE)
  3559. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  3560. pwr_mode->hs_rate);
  3561. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
  3562. | pwr_mode->pwr_tx);
  3563. if (ret) {
  3564. dev_err(hba->dev,
  3565. "%s: power mode change failed %d\n", __func__, ret);
  3566. } else {
  3567. ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
  3568. pwr_mode);
  3569. memcpy(&hba->pwr_info, pwr_mode,
  3570. sizeof(struct ufs_pa_layer_attr));
  3571. }
  3572. return ret;
  3573. }
  3574. /**
  3575. * ufshcd_config_pwr_mode - configure a new power mode
  3576. * @hba: per-adapter instance
  3577. * @desired_pwr_mode: desired power configuration
  3578. */
  3579. int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  3580. struct ufs_pa_layer_attr *desired_pwr_mode)
  3581. {
  3582. struct ufs_pa_layer_attr final_params = { 0 };
  3583. int ret;
  3584. ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
  3585. desired_pwr_mode, &final_params);
  3586. if (ret)
  3587. memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
  3588. ret = ufshcd_change_power_mode(hba, &final_params);
  3589. if (!ret)
  3590. ufshcd_print_pwr_info(hba);
  3591. return ret;
  3592. }
  3593. EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
  3594. /**
  3595. * ufshcd_complete_dev_init() - checks device readiness
  3596. * @hba: per-adapter instance
  3597. *
  3598. * Set fDeviceInit flag and poll until device toggles it.
  3599. */
  3600. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  3601. {
  3602. int i;
  3603. int err;
  3604. bool flag_res = 1;
  3605. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  3606. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  3607. if (err) {
  3608. dev_err(hba->dev,
  3609. "%s setting fDeviceInit flag failed with error %d\n",
  3610. __func__, err);
  3611. goto out;
  3612. }
  3613. /* poll for max. 1000 iterations for fDeviceInit flag to clear */
  3614. for (i = 0; i < 1000 && !err && flag_res; i++)
  3615. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  3616. QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
  3617. if (err)
  3618. dev_err(hba->dev,
  3619. "%s reading fDeviceInit flag failed with error %d\n",
  3620. __func__, err);
  3621. else if (flag_res)
  3622. dev_err(hba->dev,
  3623. "%s fDeviceInit was not cleared by the device\n",
  3624. __func__);
  3625. out:
  3626. return err;
  3627. }
  3628. /**
  3629. * ufshcd_make_hba_operational - Make UFS controller operational
  3630. * @hba: per adapter instance
  3631. *
  3632. * To bring UFS host controller to operational state,
  3633. * 1. Enable required interrupts
  3634. * 2. Configure interrupt aggregation
  3635. * 3. Program UTRL and UTMRL base address
  3636. * 4. Configure run-stop-registers
  3637. *
  3638. * Returns 0 on success, non-zero value on failure
  3639. */
  3640. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  3641. {
  3642. int err = 0;
  3643. u32 reg;
  3644. /* Enable required interrupts */
  3645. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  3646. /* Configure interrupt aggregation */
  3647. if (ufshcd_is_intr_aggr_allowed(hba))
  3648. ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
  3649. else
  3650. ufshcd_disable_intr_aggr(hba);
  3651. /* Configure UTRL and UTMRL base address registers */
  3652. ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
  3653. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  3654. ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
  3655. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  3656. ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
  3657. REG_UTP_TASK_REQ_LIST_BASE_L);
  3658. ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
  3659. REG_UTP_TASK_REQ_LIST_BASE_H);
  3660. /*
  3661. * Make sure base address and interrupt setup are updated before
  3662. * enabling the run/stop registers below.
  3663. */
  3664. wmb();
  3665. /*
  3666. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  3667. */
  3668. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  3669. if (!(ufshcd_get_lists_status(reg))) {
  3670. ufshcd_enable_run_stop_reg(hba);
  3671. } else {
  3672. dev_err(hba->dev,
  3673. "Host controller not ready to process requests");
  3674. err = -EIO;
  3675. goto out;
  3676. }
  3677. out:
  3678. return err;
  3679. }
  3680. /**
  3681. * ufshcd_hba_stop - Send controller to reset state
  3682. * @hba: per adapter instance
  3683. * @can_sleep: perform sleep or just spin
  3684. */
  3685. static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
  3686. {
  3687. int err;
  3688. ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
  3689. err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
  3690. CONTROLLER_ENABLE, CONTROLLER_DISABLE,
  3691. 10, 1, can_sleep);
  3692. if (err)
  3693. dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
  3694. }
  3695. /**
  3696. * ufshcd_hba_execute_hce - initialize the controller
  3697. * @hba: per adapter instance
  3698. *
  3699. * The controller resets itself and controller firmware initialization
  3700. * sequence kicks off. When controller is ready it will set
  3701. * the Host Controller Enable bit to 1.
  3702. *
  3703. * Returns 0 on success, non-zero value on failure
  3704. */
  3705. static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
  3706. {
  3707. int retry;
  3708. /*
  3709. * msleep of 1 and 5 used in this function might result in msleep(20),
  3710. * but it was necessary to send the UFS FPGA to reset mode during
  3711. * development and testing of this driver. msleep can be changed to
  3712. * mdelay and retry count can be reduced based on the controller.
  3713. */
  3714. if (!ufshcd_is_hba_active(hba))
  3715. /* change controller state to "reset state" */
  3716. ufshcd_hba_stop(hba, true);
  3717. /* UniPro link is disabled at this point */
  3718. ufshcd_set_link_off(hba);
  3719. ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
  3720. /* start controller initialization sequence */
  3721. ufshcd_hba_start(hba);
  3722. /*
  3723. * To initialize a UFS host controller HCE bit must be set to 1.
  3724. * During initialization the HCE bit value changes from 1->0->1.
  3725. * When the host controller completes initialization sequence
  3726. * it sets the value of HCE bit to 1. The same HCE bit is read back
  3727. * to check if the controller has completed initialization sequence.
  3728. * So without this delay the value HCE = 1, set in the previous
  3729. * instruction might be read back.
  3730. * This delay can be changed based on the controller.
  3731. */
  3732. msleep(1);
  3733. /* wait for the host controller to complete initialization */
  3734. retry = 10;
  3735. while (ufshcd_is_hba_active(hba)) {
  3736. if (retry) {
  3737. retry--;
  3738. } else {
  3739. dev_err(hba->dev,
  3740. "Controller enable failed\n");
  3741. return -EIO;
  3742. }
  3743. msleep(5);
  3744. }
  3745. /* enable UIC related interrupts */
  3746. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  3747. ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
  3748. return 0;
  3749. }
  3750. static int ufshcd_hba_enable(struct ufs_hba *hba)
  3751. {
  3752. int ret;
  3753. if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
  3754. ufshcd_set_link_off(hba);
  3755. ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
  3756. /* enable UIC related interrupts */
  3757. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  3758. ret = ufshcd_dme_reset(hba);
  3759. if (!ret) {
  3760. ret = ufshcd_dme_enable(hba);
  3761. if (!ret)
  3762. ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
  3763. if (ret)
  3764. dev_err(hba->dev,
  3765. "Host controller enable failed with non-hce\n");
  3766. }
  3767. } else {
  3768. ret = ufshcd_hba_execute_hce(hba);
  3769. }
  3770. return ret;
  3771. }
  3772. static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
  3773. {
  3774. int tx_lanes, i, err = 0;
  3775. if (!peer)
  3776. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  3777. &tx_lanes);
  3778. else
  3779. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  3780. &tx_lanes);
  3781. for (i = 0; i < tx_lanes; i++) {
  3782. if (!peer)
  3783. err = ufshcd_dme_set(hba,
  3784. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  3785. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  3786. 0);
  3787. else
  3788. err = ufshcd_dme_peer_set(hba,
  3789. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  3790. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  3791. 0);
  3792. if (err) {
  3793. dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
  3794. __func__, peer, i, err);
  3795. break;
  3796. }
  3797. }
  3798. return err;
  3799. }
  3800. static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
  3801. {
  3802. return ufshcd_disable_tx_lcc(hba, true);
  3803. }
  3804. /**
  3805. * ufshcd_link_startup - Initialize unipro link startup
  3806. * @hba: per adapter instance
  3807. *
  3808. * Returns 0 for success, non-zero in case of failure
  3809. */
  3810. static int ufshcd_link_startup(struct ufs_hba *hba)
  3811. {
  3812. int ret;
  3813. int retries = DME_LINKSTARTUP_RETRIES;
  3814. bool link_startup_again = false;
  3815. /*
  3816. * If UFS device isn't active then we will have to issue link startup
  3817. * 2 times to make sure the device state move to active.
  3818. */
  3819. if (!ufshcd_is_ufs_dev_active(hba))
  3820. link_startup_again = true;
  3821. link_startup:
  3822. do {
  3823. ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
  3824. ret = ufshcd_dme_link_startup(hba);
  3825. /* check if device is detected by inter-connect layer */
  3826. if (!ret && !ufshcd_is_device_present(hba)) {
  3827. dev_err(hba->dev, "%s: Device not present\n", __func__);
  3828. ret = -ENXIO;
  3829. goto out;
  3830. }
  3831. /*
  3832. * DME link lost indication is only received when link is up,
  3833. * but we can't be sure if the link is up until link startup
  3834. * succeeds. So reset the local Uni-Pro and try again.
  3835. */
  3836. if (ret && ufshcd_hba_enable(hba))
  3837. goto out;
  3838. } while (ret && retries--);
  3839. if (ret)
  3840. /* failed to get the link up... retire */
  3841. goto out;
  3842. if (link_startup_again) {
  3843. link_startup_again = false;
  3844. retries = DME_LINKSTARTUP_RETRIES;
  3845. goto link_startup;
  3846. }
  3847. /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
  3848. ufshcd_init_pwr_info(hba);
  3849. ufshcd_print_pwr_info(hba);
  3850. if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
  3851. ret = ufshcd_disable_device_tx_lcc(hba);
  3852. if (ret)
  3853. goto out;
  3854. }
  3855. /* Include any host controller configuration via UIC commands */
  3856. ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
  3857. if (ret)
  3858. goto out;
  3859. ret = ufshcd_make_hba_operational(hba);
  3860. out:
  3861. if (ret) {
  3862. dev_err(hba->dev, "link startup failed %d\n", ret);
  3863. ufshcd_print_host_state(hba);
  3864. ufshcd_print_pwr_info(hba);
  3865. ufshcd_print_host_regs(hba);
  3866. }
  3867. return ret;
  3868. }
  3869. /**
  3870. * ufshcd_verify_dev_init() - Verify device initialization
  3871. * @hba: per-adapter instance
  3872. *
  3873. * Send NOP OUT UPIU and wait for NOP IN response to check whether the
  3874. * device Transport Protocol (UTP) layer is ready after a reset.
  3875. * If the UTP layer at the device side is not initialized, it may
  3876. * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
  3877. * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
  3878. */
  3879. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  3880. {
  3881. int err = 0;
  3882. int retries;
  3883. ufshcd_hold(hba, false);
  3884. mutex_lock(&hba->dev_cmd.lock);
  3885. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  3886. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  3887. NOP_OUT_TIMEOUT);
  3888. if (!err || err == -ETIMEDOUT)
  3889. break;
  3890. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  3891. }
  3892. mutex_unlock(&hba->dev_cmd.lock);
  3893. ufshcd_release(hba);
  3894. if (err)
  3895. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  3896. return err;
  3897. }
  3898. /**
  3899. * ufshcd_set_queue_depth - set lun queue depth
  3900. * @sdev: pointer to SCSI device
  3901. *
  3902. * Read bLUQueueDepth value and activate scsi tagged command
  3903. * queueing. For WLUN, queue depth is set to 1. For best-effort
  3904. * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
  3905. * value that host can queue.
  3906. */
  3907. static void ufshcd_set_queue_depth(struct scsi_device *sdev)
  3908. {
  3909. int ret = 0;
  3910. u8 lun_qdepth;
  3911. struct ufs_hba *hba;
  3912. hba = shost_priv(sdev->host);
  3913. lun_qdepth = hba->nutrs;
  3914. ret = ufshcd_read_unit_desc_param(hba,
  3915. ufshcd_scsi_to_upiu_lun(sdev->lun),
  3916. UNIT_DESC_PARAM_LU_Q_DEPTH,
  3917. &lun_qdepth,
  3918. sizeof(lun_qdepth));
  3919. /* Some WLUN doesn't support unit descriptor */
  3920. if (ret == -EOPNOTSUPP)
  3921. lun_qdepth = 1;
  3922. else if (!lun_qdepth)
  3923. /* eventually, we can figure out the real queue depth */
  3924. lun_qdepth = hba->nutrs;
  3925. else
  3926. lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
  3927. dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
  3928. __func__, lun_qdepth);
  3929. scsi_change_queue_depth(sdev, lun_qdepth);
  3930. }
  3931. /*
  3932. * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
  3933. * @hba: per-adapter instance
  3934. * @lun: UFS device lun id
  3935. * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
  3936. *
  3937. * Returns 0 in case of success and b_lu_write_protect status would be returned
  3938. * @b_lu_write_protect parameter.
  3939. * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
  3940. * Returns -EINVAL in case of invalid parameters passed to this function.
  3941. */
  3942. static int ufshcd_get_lu_wp(struct ufs_hba *hba,
  3943. u8 lun,
  3944. u8 *b_lu_write_protect)
  3945. {
  3946. int ret;
  3947. if (!b_lu_write_protect)
  3948. ret = -EINVAL;
  3949. /*
  3950. * According to UFS device spec, RPMB LU can't be write
  3951. * protected so skip reading bLUWriteProtect parameter for
  3952. * it. For other W-LUs, UNIT DESCRIPTOR is not available.
  3953. */
  3954. else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
  3955. ret = -ENOTSUPP;
  3956. else
  3957. ret = ufshcd_read_unit_desc_param(hba,
  3958. lun,
  3959. UNIT_DESC_PARAM_LU_WR_PROTECT,
  3960. b_lu_write_protect,
  3961. sizeof(*b_lu_write_protect));
  3962. return ret;
  3963. }
  3964. /**
  3965. * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
  3966. * status
  3967. * @hba: per-adapter instance
  3968. * @sdev: pointer to SCSI device
  3969. *
  3970. */
  3971. static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
  3972. struct scsi_device *sdev)
  3973. {
  3974. if (hba->dev_info.f_power_on_wp_en &&
  3975. !hba->dev_info.is_lu_power_on_wp) {
  3976. u8 b_lu_write_protect;
  3977. if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
  3978. &b_lu_write_protect) &&
  3979. (b_lu_write_protect == UFS_LU_POWER_ON_WP))
  3980. hba->dev_info.is_lu_power_on_wp = true;
  3981. }
  3982. }
  3983. /**
  3984. * ufshcd_slave_alloc - handle initial SCSI device configurations
  3985. * @sdev: pointer to SCSI device
  3986. *
  3987. * Returns success
  3988. */
  3989. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  3990. {
  3991. struct ufs_hba *hba;
  3992. hba = shost_priv(sdev->host);
  3993. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  3994. sdev->use_10_for_ms = 1;
  3995. /* allow SCSI layer to restart the device in case of errors */
  3996. sdev->allow_restart = 1;
  3997. /* REPORT SUPPORTED OPERATION CODES is not supported */
  3998. sdev->no_report_opcodes = 1;
  3999. /* WRITE_SAME command is not supported */
  4000. sdev->no_write_same = 1;
  4001. ufshcd_set_queue_depth(sdev);
  4002. ufshcd_get_lu_power_on_wp_status(hba, sdev);
  4003. return 0;
  4004. }
  4005. /**
  4006. * ufshcd_change_queue_depth - change queue depth
  4007. * @sdev: pointer to SCSI device
  4008. * @depth: required depth to set
  4009. *
  4010. * Change queue depth and make sure the max. limits are not crossed.
  4011. */
  4012. static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
  4013. {
  4014. struct ufs_hba *hba = shost_priv(sdev->host);
  4015. if (depth > hba->nutrs)
  4016. depth = hba->nutrs;
  4017. return scsi_change_queue_depth(sdev, depth);
  4018. }
  4019. /**
  4020. * ufshcd_slave_configure - adjust SCSI device configurations
  4021. * @sdev: pointer to SCSI device
  4022. */
  4023. static int ufshcd_slave_configure(struct scsi_device *sdev)
  4024. {
  4025. struct request_queue *q = sdev->request_queue;
  4026. blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
  4027. blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
  4028. return 0;
  4029. }
  4030. /**
  4031. * ufshcd_slave_destroy - remove SCSI device configurations
  4032. * @sdev: pointer to SCSI device
  4033. */
  4034. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  4035. {
  4036. struct ufs_hba *hba;
  4037. hba = shost_priv(sdev->host);
  4038. /* Drop the reference as it won't be needed anymore */
  4039. if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
  4040. unsigned long flags;
  4041. spin_lock_irqsave(hba->host->host_lock, flags);
  4042. hba->sdev_ufs_device = NULL;
  4043. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4044. }
  4045. }
  4046. /**
  4047. * ufshcd_task_req_compl - handle task management request completion
  4048. * @hba: per adapter instance
  4049. * @index: index of the completed request
  4050. * @resp: task management service response
  4051. *
  4052. * Returns non-zero value on error, zero on success
  4053. */
  4054. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
  4055. {
  4056. struct utp_task_req_desc *task_req_descp;
  4057. struct utp_upiu_task_rsp *task_rsp_upiup;
  4058. unsigned long flags;
  4059. int ocs_value;
  4060. int task_result;
  4061. spin_lock_irqsave(hba->host->host_lock, flags);
  4062. /* Clear completed tasks from outstanding_tasks */
  4063. __clear_bit(index, &hba->outstanding_tasks);
  4064. task_req_descp = hba->utmrdl_base_addr;
  4065. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  4066. if (ocs_value == OCS_SUCCESS) {
  4067. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  4068. task_req_descp[index].task_rsp_upiu;
  4069. task_result = be32_to_cpu(task_rsp_upiup->output_param1);
  4070. task_result = task_result & MASK_TM_SERVICE_RESP;
  4071. if (resp)
  4072. *resp = (u8)task_result;
  4073. } else {
  4074. dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
  4075. __func__, ocs_value);
  4076. }
  4077. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4078. return ocs_value;
  4079. }
  4080. /**
  4081. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  4082. * @lrbp: pointer to local reference block of completed command
  4083. * @scsi_status: SCSI command status
  4084. *
  4085. * Returns value base on SCSI command status
  4086. */
  4087. static inline int
  4088. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  4089. {
  4090. int result = 0;
  4091. switch (scsi_status) {
  4092. case SAM_STAT_CHECK_CONDITION:
  4093. ufshcd_copy_sense_data(lrbp);
  4094. case SAM_STAT_GOOD:
  4095. result |= DID_OK << 16 |
  4096. COMMAND_COMPLETE << 8 |
  4097. scsi_status;
  4098. break;
  4099. case SAM_STAT_TASK_SET_FULL:
  4100. case SAM_STAT_BUSY:
  4101. case SAM_STAT_TASK_ABORTED:
  4102. ufshcd_copy_sense_data(lrbp);
  4103. result |= scsi_status;
  4104. break;
  4105. default:
  4106. result |= DID_ERROR << 16;
  4107. break;
  4108. } /* end of switch */
  4109. return result;
  4110. }
  4111. /**
  4112. * ufshcd_transfer_rsp_status - Get overall status of the response
  4113. * @hba: per adapter instance
  4114. * @lrbp: pointer to local reference block of completed command
  4115. *
  4116. * Returns result of the command to notify SCSI midlayer
  4117. */
  4118. static inline int
  4119. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  4120. {
  4121. int result = 0;
  4122. int scsi_status;
  4123. int ocs;
  4124. /* overall command status of utrd */
  4125. ocs = ufshcd_get_tr_ocs(lrbp);
  4126. switch (ocs) {
  4127. case OCS_SUCCESS:
  4128. result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  4129. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
  4130. switch (result) {
  4131. case UPIU_TRANSACTION_RESPONSE:
  4132. /*
  4133. * get the response UPIU result to extract
  4134. * the SCSI command status
  4135. */
  4136. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  4137. /*
  4138. * get the result based on SCSI status response
  4139. * to notify the SCSI midlayer of the command status
  4140. */
  4141. scsi_status = result & MASK_SCSI_STATUS;
  4142. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  4143. /*
  4144. * Currently we are only supporting BKOPs exception
  4145. * events hence we can ignore BKOPs exception event
  4146. * during power management callbacks. BKOPs exception
  4147. * event is not expected to be raised in runtime suspend
  4148. * callback as it allows the urgent bkops.
  4149. * During system suspend, we are anyway forcefully
  4150. * disabling the bkops and if urgent bkops is needed
  4151. * it will be enabled on system resume. Long term
  4152. * solution could be to abort the system suspend if
  4153. * UFS device needs urgent BKOPs.
  4154. */
  4155. if (!hba->pm_op_in_progress &&
  4156. ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
  4157. schedule_work(&hba->eeh_work);
  4158. break;
  4159. case UPIU_TRANSACTION_REJECT_UPIU:
  4160. /* TODO: handle Reject UPIU Response */
  4161. result = DID_ERROR << 16;
  4162. dev_err(hba->dev,
  4163. "Reject UPIU not fully implemented\n");
  4164. break;
  4165. default:
  4166. result = DID_ERROR << 16;
  4167. dev_err(hba->dev,
  4168. "Unexpected request response code = %x\n",
  4169. result);
  4170. break;
  4171. }
  4172. break;
  4173. case OCS_ABORTED:
  4174. result |= DID_ABORT << 16;
  4175. break;
  4176. case OCS_INVALID_COMMAND_STATUS:
  4177. result |= DID_REQUEUE << 16;
  4178. break;
  4179. case OCS_INVALID_CMD_TABLE_ATTR:
  4180. case OCS_INVALID_PRDT_ATTR:
  4181. case OCS_MISMATCH_DATA_BUF_SIZE:
  4182. case OCS_MISMATCH_RESP_UPIU_SIZE:
  4183. case OCS_PEER_COMM_FAILURE:
  4184. case OCS_FATAL_ERROR:
  4185. default:
  4186. result |= DID_ERROR << 16;
  4187. dev_err(hba->dev,
  4188. "OCS error from controller = %x for tag %d\n",
  4189. ocs, lrbp->task_tag);
  4190. ufshcd_print_host_regs(hba);
  4191. ufshcd_print_host_state(hba);
  4192. break;
  4193. } /* end of switch */
  4194. if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
  4195. ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
  4196. return result;
  4197. }
  4198. /**
  4199. * ufshcd_uic_cmd_compl - handle completion of uic command
  4200. * @hba: per adapter instance
  4201. * @intr_status: interrupt status generated by the controller
  4202. */
  4203. static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
  4204. {
  4205. if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
  4206. hba->active_uic_cmd->argument2 |=
  4207. ufshcd_get_uic_cmd_result(hba);
  4208. hba->active_uic_cmd->argument3 =
  4209. ufshcd_get_dme_attr_val(hba);
  4210. complete(&hba->active_uic_cmd->done);
  4211. }
  4212. if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
  4213. complete(hba->uic_async_done);
  4214. }
  4215. /**
  4216. * __ufshcd_transfer_req_compl - handle SCSI and query command completion
  4217. * @hba: per adapter instance
  4218. * @completed_reqs: requests to complete
  4219. */
  4220. static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
  4221. unsigned long completed_reqs)
  4222. {
  4223. struct ufshcd_lrb *lrbp;
  4224. struct scsi_cmnd *cmd;
  4225. int result;
  4226. int index;
  4227. for_each_set_bit(index, &completed_reqs, hba->nutrs) {
  4228. lrbp = &hba->lrb[index];
  4229. cmd = lrbp->cmd;
  4230. if (cmd) {
  4231. ufshcd_add_command_trace(hba, index, "complete");
  4232. result = ufshcd_transfer_rsp_status(hba, lrbp);
  4233. scsi_dma_unmap(cmd);
  4234. cmd->result = result;
  4235. /* Mark completed command as NULL in LRB */
  4236. lrbp->cmd = NULL;
  4237. clear_bit_unlock(index, &hba->lrb_in_use);
  4238. /* Do not touch lrbp after scsi done */
  4239. cmd->scsi_done(cmd);
  4240. __ufshcd_release(hba);
  4241. } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
  4242. lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
  4243. if (hba->dev_cmd.complete) {
  4244. ufshcd_add_command_trace(hba, index,
  4245. "dev_complete");
  4246. complete(hba->dev_cmd.complete);
  4247. }
  4248. }
  4249. if (ufshcd_is_clkscaling_supported(hba))
  4250. hba->clk_scaling.active_reqs--;
  4251. lrbp->compl_time_stamp = ktime_get();
  4252. }
  4253. /* clear corresponding bits of completed commands */
  4254. hba->outstanding_reqs ^= completed_reqs;
  4255. ufshcd_clk_scaling_update_busy(hba);
  4256. /* we might have free'd some tags above */
  4257. wake_up(&hba->dev_cmd.tag_wq);
  4258. }
  4259. /**
  4260. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  4261. * @hba: per adapter instance
  4262. */
  4263. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  4264. {
  4265. unsigned long completed_reqs;
  4266. u32 tr_doorbell;
  4267. /* Resetting interrupt aggregation counters first and reading the
  4268. * DOOR_BELL afterward allows us to handle all the completed requests.
  4269. * In order to prevent other interrupts starvation the DB is read once
  4270. * after reset. The down side of this solution is the possibility of
  4271. * false interrupt if device completes another request after resetting
  4272. * aggregation and before reading the DB.
  4273. */
  4274. if (ufshcd_is_intr_aggr_allowed(hba) &&
  4275. !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
  4276. ufshcd_reset_intr_aggr(hba);
  4277. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  4278. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  4279. __ufshcd_transfer_req_compl(hba, completed_reqs);
  4280. }
  4281. /**
  4282. * ufshcd_disable_ee - disable exception event
  4283. * @hba: per-adapter instance
  4284. * @mask: exception event to disable
  4285. *
  4286. * Disables exception event in the device so that the EVENT_ALERT
  4287. * bit is not set.
  4288. *
  4289. * Returns zero on success, non-zero error value on failure.
  4290. */
  4291. static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
  4292. {
  4293. int err = 0;
  4294. u32 val;
  4295. if (!(hba->ee_ctrl_mask & mask))
  4296. goto out;
  4297. val = hba->ee_ctrl_mask & ~mask;
  4298. val &= MASK_EE_STATUS;
  4299. err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  4300. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  4301. if (!err)
  4302. hba->ee_ctrl_mask &= ~mask;
  4303. out:
  4304. return err;
  4305. }
  4306. /**
  4307. * ufshcd_enable_ee - enable exception event
  4308. * @hba: per-adapter instance
  4309. * @mask: exception event to enable
  4310. *
  4311. * Enable corresponding exception event in the device to allow
  4312. * device to alert host in critical scenarios.
  4313. *
  4314. * Returns zero on success, non-zero error value on failure.
  4315. */
  4316. static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
  4317. {
  4318. int err = 0;
  4319. u32 val;
  4320. if (hba->ee_ctrl_mask & mask)
  4321. goto out;
  4322. val = hba->ee_ctrl_mask | mask;
  4323. val &= MASK_EE_STATUS;
  4324. err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  4325. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  4326. if (!err)
  4327. hba->ee_ctrl_mask |= mask;
  4328. out:
  4329. return err;
  4330. }
  4331. /**
  4332. * ufshcd_enable_auto_bkops - Allow device managed BKOPS
  4333. * @hba: per-adapter instance
  4334. *
  4335. * Allow device to manage background operations on its own. Enabling
  4336. * this might lead to inconsistent latencies during normal data transfers
  4337. * as the device is allowed to manage its own way of handling background
  4338. * operations.
  4339. *
  4340. * Returns zero on success, non-zero on failure.
  4341. */
  4342. static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
  4343. {
  4344. int err = 0;
  4345. if (hba->auto_bkops_enabled)
  4346. goto out;
  4347. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  4348. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  4349. if (err) {
  4350. dev_err(hba->dev, "%s: failed to enable bkops %d\n",
  4351. __func__, err);
  4352. goto out;
  4353. }
  4354. hba->auto_bkops_enabled = true;
  4355. trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
  4356. /* No need of URGENT_BKOPS exception from the device */
  4357. err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  4358. if (err)
  4359. dev_err(hba->dev, "%s: failed to disable exception event %d\n",
  4360. __func__, err);
  4361. out:
  4362. return err;
  4363. }
  4364. /**
  4365. * ufshcd_disable_auto_bkops - block device in doing background operations
  4366. * @hba: per-adapter instance
  4367. *
  4368. * Disabling background operations improves command response latency but
  4369. * has drawback of device moving into critical state where the device is
  4370. * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
  4371. * host is idle so that BKOPS are managed effectively without any negative
  4372. * impacts.
  4373. *
  4374. * Returns zero on success, non-zero on failure.
  4375. */
  4376. static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
  4377. {
  4378. int err = 0;
  4379. if (!hba->auto_bkops_enabled)
  4380. goto out;
  4381. /*
  4382. * If host assisted BKOPs is to be enabled, make sure
  4383. * urgent bkops exception is allowed.
  4384. */
  4385. err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
  4386. if (err) {
  4387. dev_err(hba->dev, "%s: failed to enable exception event %d\n",
  4388. __func__, err);
  4389. goto out;
  4390. }
  4391. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
  4392. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  4393. if (err) {
  4394. dev_err(hba->dev, "%s: failed to disable bkops %d\n",
  4395. __func__, err);
  4396. ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  4397. goto out;
  4398. }
  4399. hba->auto_bkops_enabled = false;
  4400. trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
  4401. hba->is_urgent_bkops_lvl_checked = false;
  4402. out:
  4403. return err;
  4404. }
  4405. /**
  4406. * ufshcd_force_reset_auto_bkops - force reset auto bkops state
  4407. * @hba: per adapter instance
  4408. *
  4409. * After a device reset the device may toggle the BKOPS_EN flag
  4410. * to default value. The s/w tracking variables should be updated
  4411. * as well. This function would change the auto-bkops state based on
  4412. * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
  4413. */
  4414. static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
  4415. {
  4416. if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
  4417. hba->auto_bkops_enabled = false;
  4418. hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
  4419. ufshcd_enable_auto_bkops(hba);
  4420. } else {
  4421. hba->auto_bkops_enabled = true;
  4422. hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
  4423. ufshcd_disable_auto_bkops(hba);
  4424. }
  4425. hba->is_urgent_bkops_lvl_checked = false;
  4426. }
  4427. static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
  4428. {
  4429. return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  4430. QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
  4431. }
  4432. /**
  4433. * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
  4434. * @hba: per-adapter instance
  4435. * @status: bkops_status value
  4436. *
  4437. * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
  4438. * flag in the device to permit background operations if the device
  4439. * bkops_status is greater than or equal to "status" argument passed to
  4440. * this function, disable otherwise.
  4441. *
  4442. * Returns 0 for success, non-zero in case of failure.
  4443. *
  4444. * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
  4445. * to know whether auto bkops is enabled or disabled after this function
  4446. * returns control to it.
  4447. */
  4448. static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
  4449. enum bkops_status status)
  4450. {
  4451. int err;
  4452. u32 curr_status = 0;
  4453. err = ufshcd_get_bkops_status(hba, &curr_status);
  4454. if (err) {
  4455. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  4456. __func__, err);
  4457. goto out;
  4458. } else if (curr_status > BKOPS_STATUS_MAX) {
  4459. dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
  4460. __func__, curr_status);
  4461. err = -EINVAL;
  4462. goto out;
  4463. }
  4464. if (curr_status >= status)
  4465. err = ufshcd_enable_auto_bkops(hba);
  4466. else
  4467. err = ufshcd_disable_auto_bkops(hba);
  4468. out:
  4469. return err;
  4470. }
  4471. /**
  4472. * ufshcd_urgent_bkops - handle urgent bkops exception event
  4473. * @hba: per-adapter instance
  4474. *
  4475. * Enable fBackgroundOpsEn flag in the device to permit background
  4476. * operations.
  4477. *
  4478. * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
  4479. * and negative error value for any other failure.
  4480. */
  4481. static int ufshcd_urgent_bkops(struct ufs_hba *hba)
  4482. {
  4483. return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
  4484. }
  4485. static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
  4486. {
  4487. return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  4488. QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
  4489. }
  4490. static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
  4491. {
  4492. int err;
  4493. u32 curr_status = 0;
  4494. if (hba->is_urgent_bkops_lvl_checked)
  4495. goto enable_auto_bkops;
  4496. err = ufshcd_get_bkops_status(hba, &curr_status);
  4497. if (err) {
  4498. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  4499. __func__, err);
  4500. goto out;
  4501. }
  4502. /*
  4503. * We are seeing that some devices are raising the urgent bkops
  4504. * exception events even when BKOPS status doesn't indicate performace
  4505. * impacted or critical. Handle these device by determining their urgent
  4506. * bkops status at runtime.
  4507. */
  4508. if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
  4509. dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
  4510. __func__, curr_status);
  4511. /* update the current status as the urgent bkops level */
  4512. hba->urgent_bkops_lvl = curr_status;
  4513. hba->is_urgent_bkops_lvl_checked = true;
  4514. }
  4515. enable_auto_bkops:
  4516. err = ufshcd_enable_auto_bkops(hba);
  4517. out:
  4518. if (err < 0)
  4519. dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
  4520. __func__, err);
  4521. }
  4522. /**
  4523. * ufshcd_exception_event_handler - handle exceptions raised by device
  4524. * @work: pointer to work data
  4525. *
  4526. * Read bExceptionEventStatus attribute from the device and handle the
  4527. * exception event accordingly.
  4528. */
  4529. static void ufshcd_exception_event_handler(struct work_struct *work)
  4530. {
  4531. struct ufs_hba *hba;
  4532. int err;
  4533. u32 status = 0;
  4534. hba = container_of(work, struct ufs_hba, eeh_work);
  4535. pm_runtime_get_sync(hba->dev);
  4536. scsi_block_requests(hba->host);
  4537. err = ufshcd_get_ee_status(hba, &status);
  4538. if (err) {
  4539. dev_err(hba->dev, "%s: failed to get exception status %d\n",
  4540. __func__, err);
  4541. goto out;
  4542. }
  4543. status &= hba->ee_ctrl_mask;
  4544. if (status & MASK_EE_URGENT_BKOPS)
  4545. ufshcd_bkops_exception_event_handler(hba);
  4546. out:
  4547. scsi_unblock_requests(hba->host);
  4548. pm_runtime_put_sync(hba->dev);
  4549. return;
  4550. }
  4551. /* Complete requests that have door-bell cleared */
  4552. static void ufshcd_complete_requests(struct ufs_hba *hba)
  4553. {
  4554. ufshcd_transfer_req_compl(hba);
  4555. ufshcd_tmc_handler(hba);
  4556. }
  4557. /**
  4558. * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
  4559. * to recover from the DL NAC errors or not.
  4560. * @hba: per-adapter instance
  4561. *
  4562. * Returns true if error handling is required, false otherwise
  4563. */
  4564. static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
  4565. {
  4566. unsigned long flags;
  4567. bool err_handling = true;
  4568. spin_lock_irqsave(hba->host->host_lock, flags);
  4569. /*
  4570. * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
  4571. * device fatal error and/or DL NAC & REPLAY timeout errors.
  4572. */
  4573. if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
  4574. goto out;
  4575. if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
  4576. ((hba->saved_err & UIC_ERROR) &&
  4577. (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
  4578. goto out;
  4579. if ((hba->saved_err & UIC_ERROR) &&
  4580. (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
  4581. int err;
  4582. /*
  4583. * wait for 50ms to see if we can get any other errors or not.
  4584. */
  4585. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4586. msleep(50);
  4587. spin_lock_irqsave(hba->host->host_lock, flags);
  4588. /*
  4589. * now check if we have got any other severe errors other than
  4590. * DL NAC error?
  4591. */
  4592. if ((hba->saved_err & INT_FATAL_ERRORS) ||
  4593. ((hba->saved_err & UIC_ERROR) &&
  4594. (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
  4595. goto out;
  4596. /*
  4597. * As DL NAC is the only error received so far, send out NOP
  4598. * command to confirm if link is still active or not.
  4599. * - If we don't get any response then do error recovery.
  4600. * - If we get response then clear the DL NAC error bit.
  4601. */
  4602. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4603. err = ufshcd_verify_dev_init(hba);
  4604. spin_lock_irqsave(hba->host->host_lock, flags);
  4605. if (err)
  4606. goto out;
  4607. /* Link seems to be alive hence ignore the DL NAC errors */
  4608. if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
  4609. hba->saved_err &= ~UIC_ERROR;
  4610. /* clear NAC error */
  4611. hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
  4612. if (!hba->saved_uic_err) {
  4613. err_handling = false;
  4614. goto out;
  4615. }
  4616. }
  4617. out:
  4618. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4619. return err_handling;
  4620. }
  4621. /**
  4622. * ufshcd_err_handler - handle UFS errors that require s/w attention
  4623. * @work: pointer to work structure
  4624. */
  4625. static void ufshcd_err_handler(struct work_struct *work)
  4626. {
  4627. struct ufs_hba *hba;
  4628. unsigned long flags;
  4629. u32 err_xfer = 0;
  4630. u32 err_tm = 0;
  4631. int err = 0;
  4632. int tag;
  4633. bool needs_reset = false;
  4634. hba = container_of(work, struct ufs_hba, eh_work);
  4635. pm_runtime_get_sync(hba->dev);
  4636. ufshcd_hold(hba, false);
  4637. spin_lock_irqsave(hba->host->host_lock, flags);
  4638. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  4639. goto out;
  4640. hba->ufshcd_state = UFSHCD_STATE_RESET;
  4641. ufshcd_set_eh_in_progress(hba);
  4642. /* Complete requests that have door-bell cleared by h/w */
  4643. ufshcd_complete_requests(hba);
  4644. if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
  4645. bool ret;
  4646. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4647. /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
  4648. ret = ufshcd_quirk_dl_nac_errors(hba);
  4649. spin_lock_irqsave(hba->host->host_lock, flags);
  4650. if (!ret)
  4651. goto skip_err_handling;
  4652. }
  4653. if ((hba->saved_err & INT_FATAL_ERRORS) ||
  4654. ((hba->saved_err & UIC_ERROR) &&
  4655. (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
  4656. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
  4657. UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
  4658. needs_reset = true;
  4659. /*
  4660. * if host reset is required then skip clearing the pending
  4661. * transfers forcefully because they will get cleared during
  4662. * host reset and restore
  4663. */
  4664. if (needs_reset)
  4665. goto skip_pending_xfer_clear;
  4666. /* release lock as clear command might sleep */
  4667. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4668. /* Clear pending transfer requests */
  4669. for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
  4670. if (ufshcd_clear_cmd(hba, tag)) {
  4671. err_xfer = true;
  4672. goto lock_skip_pending_xfer_clear;
  4673. }
  4674. }
  4675. /* Clear pending task management requests */
  4676. for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
  4677. if (ufshcd_clear_tm_cmd(hba, tag)) {
  4678. err_tm = true;
  4679. goto lock_skip_pending_xfer_clear;
  4680. }
  4681. }
  4682. lock_skip_pending_xfer_clear:
  4683. spin_lock_irqsave(hba->host->host_lock, flags);
  4684. /* Complete the requests that are cleared by s/w */
  4685. ufshcd_complete_requests(hba);
  4686. if (err_xfer || err_tm)
  4687. needs_reset = true;
  4688. skip_pending_xfer_clear:
  4689. /* Fatal errors need reset */
  4690. if (needs_reset) {
  4691. unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
  4692. /*
  4693. * ufshcd_reset_and_restore() does the link reinitialization
  4694. * which will need atleast one empty doorbell slot to send the
  4695. * device management commands (NOP and query commands).
  4696. * If there is no slot empty at this moment then free up last
  4697. * slot forcefully.
  4698. */
  4699. if (hba->outstanding_reqs == max_doorbells)
  4700. __ufshcd_transfer_req_compl(hba,
  4701. (1UL << (hba->nutrs - 1)));
  4702. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4703. err = ufshcd_reset_and_restore(hba);
  4704. spin_lock_irqsave(hba->host->host_lock, flags);
  4705. if (err) {
  4706. dev_err(hba->dev, "%s: reset and restore failed\n",
  4707. __func__);
  4708. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  4709. }
  4710. /*
  4711. * Inform scsi mid-layer that we did reset and allow to handle
  4712. * Unit Attention properly.
  4713. */
  4714. scsi_report_bus_reset(hba->host, 0);
  4715. hba->saved_err = 0;
  4716. hba->saved_uic_err = 0;
  4717. }
  4718. skip_err_handling:
  4719. if (!needs_reset) {
  4720. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  4721. if (hba->saved_err || hba->saved_uic_err)
  4722. dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
  4723. __func__, hba->saved_err, hba->saved_uic_err);
  4724. }
  4725. ufshcd_clear_eh_in_progress(hba);
  4726. out:
  4727. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4728. ufshcd_scsi_unblock_requests(hba);
  4729. ufshcd_release(hba);
  4730. pm_runtime_put_sync(hba->dev);
  4731. }
  4732. static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
  4733. u32 reg)
  4734. {
  4735. reg_hist->reg[reg_hist->pos] = reg;
  4736. reg_hist->tstamp[reg_hist->pos] = ktime_get();
  4737. reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
  4738. }
  4739. /**
  4740. * ufshcd_update_uic_error - check and set fatal UIC error flags.
  4741. * @hba: per-adapter instance
  4742. */
  4743. static void ufshcd_update_uic_error(struct ufs_hba *hba)
  4744. {
  4745. u32 reg;
  4746. /* PHY layer lane error */
  4747. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
  4748. /* Ignore LINERESET indication, as this is not an error */
  4749. if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
  4750. (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
  4751. /*
  4752. * To know whether this error is fatal or not, DB timeout
  4753. * must be checked but this error is handled separately.
  4754. */
  4755. dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
  4756. ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
  4757. }
  4758. /* PA_INIT_ERROR is fatal and needs UIC reset */
  4759. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
  4760. if (reg)
  4761. ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
  4762. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  4763. hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
  4764. else if (hba->dev_quirks &
  4765. UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
  4766. if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
  4767. hba->uic_error |=
  4768. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
  4769. else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
  4770. hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
  4771. }
  4772. /* UIC NL/TL/DME errors needs software retry */
  4773. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
  4774. if (reg) {
  4775. ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
  4776. hba->uic_error |= UFSHCD_UIC_NL_ERROR;
  4777. }
  4778. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
  4779. if (reg) {
  4780. ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
  4781. hba->uic_error |= UFSHCD_UIC_TL_ERROR;
  4782. }
  4783. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
  4784. if (reg) {
  4785. ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
  4786. hba->uic_error |= UFSHCD_UIC_DME_ERROR;
  4787. }
  4788. dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
  4789. __func__, hba->uic_error);
  4790. }
  4791. /**
  4792. * ufshcd_check_errors - Check for errors that need s/w attention
  4793. * @hba: per-adapter instance
  4794. */
  4795. static void ufshcd_check_errors(struct ufs_hba *hba)
  4796. {
  4797. bool queue_eh_work = false;
  4798. if (hba->errors & INT_FATAL_ERRORS)
  4799. queue_eh_work = true;
  4800. if (hba->errors & UIC_ERROR) {
  4801. hba->uic_error = 0;
  4802. ufshcd_update_uic_error(hba);
  4803. if (hba->uic_error)
  4804. queue_eh_work = true;
  4805. }
  4806. if (queue_eh_work) {
  4807. /*
  4808. * update the transfer error masks to sticky bits, let's do this
  4809. * irrespective of current ufshcd_state.
  4810. */
  4811. hba->saved_err |= hba->errors;
  4812. hba->saved_uic_err |= hba->uic_error;
  4813. /* handle fatal errors only when link is functional */
  4814. if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
  4815. /* block commands from scsi mid-layer */
  4816. ufshcd_scsi_block_requests(hba);
  4817. hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
  4818. /* dump controller state before resetting */
  4819. if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
  4820. bool pr_prdt = !!(hba->saved_err &
  4821. SYSTEM_BUS_FATAL_ERROR);
  4822. dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
  4823. __func__, hba->saved_err,
  4824. hba->saved_uic_err);
  4825. ufshcd_print_host_regs(hba);
  4826. ufshcd_print_pwr_info(hba);
  4827. ufshcd_print_tmrs(hba, hba->outstanding_tasks);
  4828. ufshcd_print_trs(hba, hba->outstanding_reqs,
  4829. pr_prdt);
  4830. }
  4831. schedule_work(&hba->eh_work);
  4832. }
  4833. }
  4834. /*
  4835. * if (!queue_eh_work) -
  4836. * Other errors are either non-fatal where host recovers
  4837. * itself without s/w intervention or errors that will be
  4838. * handled by the SCSI core layer.
  4839. */
  4840. }
  4841. /**
  4842. * ufshcd_tmc_handler - handle task management function completion
  4843. * @hba: per adapter instance
  4844. */
  4845. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  4846. {
  4847. u32 tm_doorbell;
  4848. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  4849. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  4850. wake_up(&hba->tm_wq);
  4851. }
  4852. /**
  4853. * ufshcd_sl_intr - Interrupt service routine
  4854. * @hba: per adapter instance
  4855. * @intr_status: contains interrupts generated by the controller
  4856. */
  4857. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  4858. {
  4859. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  4860. if (hba->errors)
  4861. ufshcd_check_errors(hba);
  4862. if (intr_status & UFSHCD_UIC_MASK)
  4863. ufshcd_uic_cmd_compl(hba, intr_status);
  4864. if (intr_status & UTP_TASK_REQ_COMPL)
  4865. ufshcd_tmc_handler(hba);
  4866. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  4867. ufshcd_transfer_req_compl(hba);
  4868. }
  4869. /**
  4870. * ufshcd_intr - Main interrupt service routine
  4871. * @irq: irq number
  4872. * @__hba: pointer to adapter instance
  4873. *
  4874. * Returns IRQ_HANDLED - If interrupt is valid
  4875. * IRQ_NONE - If invalid interrupt
  4876. */
  4877. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  4878. {
  4879. u32 intr_status, enabled_intr_status = 0;
  4880. irqreturn_t retval = IRQ_NONE;
  4881. struct ufs_hba *hba = __hba;
  4882. int retries = hba->nutrs;
  4883. spin_lock(hba->host->host_lock);
  4884. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  4885. /*
  4886. * There could be max of hba->nutrs reqs in flight and in worst case
  4887. * if the reqs get finished 1 by 1 after the interrupt status is
  4888. * read, make sure we handle them by checking the interrupt status
  4889. * again in a loop until we process all of the reqs before returning.
  4890. */
  4891. while (intr_status && retries--) {
  4892. enabled_intr_status =
  4893. intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  4894. if (intr_status)
  4895. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  4896. if (enabled_intr_status) {
  4897. ufshcd_sl_intr(hba, enabled_intr_status);
  4898. retval = IRQ_HANDLED;
  4899. }
  4900. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  4901. }
  4902. spin_unlock(hba->host->host_lock);
  4903. return retval;
  4904. }
  4905. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
  4906. {
  4907. int err = 0;
  4908. u32 mask = 1 << tag;
  4909. unsigned long flags;
  4910. if (!test_bit(tag, &hba->outstanding_tasks))
  4911. goto out;
  4912. spin_lock_irqsave(hba->host->host_lock, flags);
  4913. ufshcd_utmrl_clear(hba, tag);
  4914. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4915. /* poll for max. 1 sec to clear door bell register by h/w */
  4916. err = ufshcd_wait_for_register(hba,
  4917. REG_UTP_TASK_REQ_DOOR_BELL,
  4918. mask, 0, 1000, 1000, true);
  4919. out:
  4920. return err;
  4921. }
  4922. /**
  4923. * ufshcd_issue_tm_cmd - issues task management commands to controller
  4924. * @hba: per adapter instance
  4925. * @lun_id: LUN ID to which TM command is sent
  4926. * @task_id: task ID to which the TM command is applicable
  4927. * @tm_function: task management function opcode
  4928. * @tm_response: task management service response return value
  4929. *
  4930. * Returns non-zero value on error, zero on success.
  4931. */
  4932. static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
  4933. u8 tm_function, u8 *tm_response)
  4934. {
  4935. struct utp_task_req_desc *task_req_descp;
  4936. struct utp_upiu_task_req *task_req_upiup;
  4937. struct Scsi_Host *host;
  4938. unsigned long flags;
  4939. int free_slot;
  4940. int err;
  4941. int task_tag;
  4942. host = hba->host;
  4943. /*
  4944. * Get free slot, sleep if slots are unavailable.
  4945. * Even though we use wait_event() which sleeps indefinitely,
  4946. * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
  4947. */
  4948. wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
  4949. ufshcd_hold(hba, false);
  4950. spin_lock_irqsave(host->host_lock, flags);
  4951. task_req_descp = hba->utmrdl_base_addr;
  4952. task_req_descp += free_slot;
  4953. /* Configure task request descriptor */
  4954. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  4955. task_req_descp->header.dword_2 =
  4956. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  4957. /* Configure task request UPIU */
  4958. task_req_upiup =
  4959. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  4960. task_tag = hba->nutrs + free_slot;
  4961. task_req_upiup->header.dword_0 =
  4962. UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  4963. lun_id, task_tag);
  4964. task_req_upiup->header.dword_1 =
  4965. UPIU_HEADER_DWORD(0, tm_function, 0, 0);
  4966. /*
  4967. * The host shall provide the same value for LUN field in the basic
  4968. * header and for Input Parameter.
  4969. */
  4970. task_req_upiup->input_param1 = cpu_to_be32(lun_id);
  4971. task_req_upiup->input_param2 = cpu_to_be32(task_id);
  4972. ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
  4973. /* send command to the controller */
  4974. __set_bit(free_slot, &hba->outstanding_tasks);
  4975. /* Make sure descriptors are ready before ringing the task doorbell */
  4976. wmb();
  4977. ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
  4978. /* Make sure that doorbell is committed immediately */
  4979. wmb();
  4980. spin_unlock_irqrestore(host->host_lock, flags);
  4981. ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
  4982. /* wait until the task management command is completed */
  4983. err = wait_event_timeout(hba->tm_wq,
  4984. test_bit(free_slot, &hba->tm_condition),
  4985. msecs_to_jiffies(TM_CMD_TIMEOUT));
  4986. if (!err) {
  4987. ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
  4988. dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
  4989. __func__, tm_function);
  4990. if (ufshcd_clear_tm_cmd(hba, free_slot))
  4991. dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
  4992. __func__, free_slot);
  4993. err = -ETIMEDOUT;
  4994. } else {
  4995. err = ufshcd_task_req_compl(hba, free_slot, tm_response);
  4996. ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
  4997. }
  4998. clear_bit(free_slot, &hba->tm_condition);
  4999. ufshcd_put_tm_slot(hba, free_slot);
  5000. wake_up(&hba->tm_tag_wq);
  5001. ufshcd_release(hba);
  5002. return err;
  5003. }
  5004. /**
  5005. * ufshcd_eh_device_reset_handler - device reset handler registered to
  5006. * scsi layer.
  5007. * @cmd: SCSI command pointer
  5008. *
  5009. * Returns SUCCESS/FAILED
  5010. */
  5011. static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
  5012. {
  5013. struct Scsi_Host *host;
  5014. struct ufs_hba *hba;
  5015. u32 pos;
  5016. int err;
  5017. u8 resp = 0xF, lun;
  5018. unsigned long flags;
  5019. host = cmd->device->host;
  5020. hba = shost_priv(host);
  5021. lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
  5022. err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
  5023. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  5024. if (!err)
  5025. err = resp;
  5026. goto out;
  5027. }
  5028. /* clear the commands that were pending for corresponding LUN */
  5029. for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
  5030. if (hba->lrb[pos].lun == lun) {
  5031. err = ufshcd_clear_cmd(hba, pos);
  5032. if (err)
  5033. break;
  5034. }
  5035. }
  5036. spin_lock_irqsave(host->host_lock, flags);
  5037. ufshcd_transfer_req_compl(hba);
  5038. spin_unlock_irqrestore(host->host_lock, flags);
  5039. out:
  5040. hba->req_abort_count = 0;
  5041. if (!err) {
  5042. err = SUCCESS;
  5043. } else {
  5044. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  5045. err = FAILED;
  5046. }
  5047. return err;
  5048. }
  5049. static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
  5050. {
  5051. struct ufshcd_lrb *lrbp;
  5052. int tag;
  5053. for_each_set_bit(tag, &bitmap, hba->nutrs) {
  5054. lrbp = &hba->lrb[tag];
  5055. lrbp->req_abort_skip = true;
  5056. }
  5057. }
  5058. /**
  5059. * ufshcd_abort - abort a specific command
  5060. * @cmd: SCSI command pointer
  5061. *
  5062. * Abort the pending command in device by sending UFS_ABORT_TASK task management
  5063. * command, and in host controller by clearing the door-bell register. There can
  5064. * be race between controller sending the command to the device while abort is
  5065. * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
  5066. * really issued and then try to abort it.
  5067. *
  5068. * Returns SUCCESS/FAILED
  5069. */
  5070. static int ufshcd_abort(struct scsi_cmnd *cmd)
  5071. {
  5072. struct Scsi_Host *host;
  5073. struct ufs_hba *hba;
  5074. unsigned long flags;
  5075. unsigned int tag;
  5076. int err = 0;
  5077. int poll_cnt;
  5078. u8 resp = 0xF;
  5079. struct ufshcd_lrb *lrbp;
  5080. u32 reg;
  5081. host = cmd->device->host;
  5082. hba = shost_priv(host);
  5083. tag = cmd->request->tag;
  5084. lrbp = &hba->lrb[tag];
  5085. if (!ufshcd_valid_tag(hba, tag)) {
  5086. dev_err(hba->dev,
  5087. "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
  5088. __func__, tag, cmd, cmd->request);
  5089. BUG();
  5090. }
  5091. /*
  5092. * Task abort to the device W-LUN is illegal. When this command
  5093. * will fail, due to spec violation, scsi err handling next step
  5094. * will be to send LU reset which, again, is a spec violation.
  5095. * To avoid these unnecessary/illegal step we skip to the last error
  5096. * handling stage: reset and restore.
  5097. */
  5098. if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
  5099. return ufshcd_eh_host_reset_handler(cmd);
  5100. ufshcd_hold(hba, false);
  5101. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  5102. /* If command is already aborted/completed, return SUCCESS */
  5103. if (!(test_bit(tag, &hba->outstanding_reqs))) {
  5104. dev_err(hba->dev,
  5105. "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
  5106. __func__, tag, hba->outstanding_reqs, reg);
  5107. goto out;
  5108. }
  5109. if (!(reg & (1 << tag))) {
  5110. dev_err(hba->dev,
  5111. "%s: cmd was completed, but without a notifying intr, tag = %d",
  5112. __func__, tag);
  5113. }
  5114. /* Print Transfer Request of aborted task */
  5115. dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
  5116. /*
  5117. * Print detailed info about aborted request.
  5118. * As more than one request might get aborted at the same time,
  5119. * print full information only for the first aborted request in order
  5120. * to reduce repeated printouts. For other aborted requests only print
  5121. * basic details.
  5122. */
  5123. scsi_print_command(hba->lrb[tag].cmd);
  5124. if (!hba->req_abort_count) {
  5125. ufshcd_print_host_regs(hba);
  5126. ufshcd_print_host_state(hba);
  5127. ufshcd_print_pwr_info(hba);
  5128. ufshcd_print_trs(hba, 1 << tag, true);
  5129. } else {
  5130. ufshcd_print_trs(hba, 1 << tag, false);
  5131. }
  5132. hba->req_abort_count++;
  5133. /* Skip task abort in case previous aborts failed and report failure */
  5134. if (lrbp->req_abort_skip) {
  5135. err = -EIO;
  5136. goto out;
  5137. }
  5138. for (poll_cnt = 100; poll_cnt; poll_cnt--) {
  5139. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  5140. UFS_QUERY_TASK, &resp);
  5141. if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
  5142. /* cmd pending in the device */
  5143. dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
  5144. __func__, tag);
  5145. break;
  5146. } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  5147. /*
  5148. * cmd not pending in the device, check if it is
  5149. * in transition.
  5150. */
  5151. dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
  5152. __func__, tag);
  5153. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  5154. if (reg & (1 << tag)) {
  5155. /* sleep for max. 200us to stabilize */
  5156. usleep_range(100, 200);
  5157. continue;
  5158. }
  5159. /* command completed already */
  5160. dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
  5161. __func__, tag);
  5162. goto cleanup;
  5163. } else {
  5164. dev_err(hba->dev,
  5165. "%s: no response from device. tag = %d, err %d\n",
  5166. __func__, tag, err);
  5167. if (!err)
  5168. err = resp; /* service response error */
  5169. goto out;
  5170. }
  5171. }
  5172. if (!poll_cnt) {
  5173. err = -EBUSY;
  5174. goto out;
  5175. }
  5176. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  5177. UFS_ABORT_TASK, &resp);
  5178. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  5179. if (!err) {
  5180. err = resp; /* service response error */
  5181. dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
  5182. __func__, tag, err);
  5183. }
  5184. goto out;
  5185. }
  5186. err = ufshcd_clear_cmd(hba, tag);
  5187. if (err) {
  5188. dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
  5189. __func__, tag, err);
  5190. goto out;
  5191. }
  5192. cleanup:
  5193. scsi_dma_unmap(cmd);
  5194. spin_lock_irqsave(host->host_lock, flags);
  5195. ufshcd_outstanding_req_clear(hba, tag);
  5196. hba->lrb[tag].cmd = NULL;
  5197. spin_unlock_irqrestore(host->host_lock, flags);
  5198. clear_bit_unlock(tag, &hba->lrb_in_use);
  5199. wake_up(&hba->dev_cmd.tag_wq);
  5200. out:
  5201. if (!err) {
  5202. err = SUCCESS;
  5203. } else {
  5204. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  5205. ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
  5206. err = FAILED;
  5207. }
  5208. /*
  5209. * This ufshcd_release() corresponds to the original scsi cmd that got
  5210. * aborted here (as we won't get any IRQ for it).
  5211. */
  5212. ufshcd_release(hba);
  5213. return err;
  5214. }
  5215. /**
  5216. * ufshcd_host_reset_and_restore - reset and restore host controller
  5217. * @hba: per-adapter instance
  5218. *
  5219. * Note that host controller reset may issue DME_RESET to
  5220. * local and remote (device) Uni-Pro stack and the attributes
  5221. * are reset to default state.
  5222. *
  5223. * Returns zero on success, non-zero on failure
  5224. */
  5225. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
  5226. {
  5227. int err;
  5228. unsigned long flags;
  5229. /*
  5230. * Stop the host controller and complete the requests
  5231. * cleared by h/w
  5232. */
  5233. spin_lock_irqsave(hba->host->host_lock, flags);
  5234. ufshcd_hba_stop(hba, false);
  5235. hba->silence_err_logs = true;
  5236. ufshcd_complete_requests(hba);
  5237. hba->silence_err_logs = false;
  5238. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5239. /* scale up clocks to max frequency before full reinitialization */
  5240. ufshcd_scale_clks(hba, true);
  5241. err = ufshcd_hba_enable(hba);
  5242. if (err)
  5243. goto out;
  5244. /* Establish the link again and restore the device */
  5245. err = ufshcd_probe_hba(hba);
  5246. if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
  5247. err = -EIO;
  5248. out:
  5249. if (err)
  5250. dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
  5251. return err;
  5252. }
  5253. /**
  5254. * ufshcd_reset_and_restore - reset and re-initialize host/device
  5255. * @hba: per-adapter instance
  5256. *
  5257. * Reset and recover device, host and re-establish link. This
  5258. * is helpful to recover the communication in fatal error conditions.
  5259. *
  5260. * Returns zero on success, non-zero on failure
  5261. */
  5262. static int ufshcd_reset_and_restore(struct ufs_hba *hba)
  5263. {
  5264. int err = 0;
  5265. int retries = MAX_HOST_RESET_RETRIES;
  5266. do {
  5267. err = ufshcd_host_reset_and_restore(hba);
  5268. } while (err && --retries);
  5269. return err;
  5270. }
  5271. /**
  5272. * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
  5273. * @cmd: SCSI command pointer
  5274. *
  5275. * Returns SUCCESS/FAILED
  5276. */
  5277. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
  5278. {
  5279. int err;
  5280. unsigned long flags;
  5281. struct ufs_hba *hba;
  5282. hba = shost_priv(cmd->device->host);
  5283. ufshcd_hold(hba, false);
  5284. /*
  5285. * Check if there is any race with fatal error handling.
  5286. * If so, wait for it to complete. Even though fatal error
  5287. * handling does reset and restore in some cases, don't assume
  5288. * anything out of it. We are just avoiding race here.
  5289. */
  5290. do {
  5291. spin_lock_irqsave(hba->host->host_lock, flags);
  5292. if (!(work_pending(&hba->eh_work) ||
  5293. hba->ufshcd_state == UFSHCD_STATE_RESET ||
  5294. hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
  5295. break;
  5296. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5297. dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
  5298. flush_work(&hba->eh_work);
  5299. } while (1);
  5300. hba->ufshcd_state = UFSHCD_STATE_RESET;
  5301. ufshcd_set_eh_in_progress(hba);
  5302. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5303. err = ufshcd_reset_and_restore(hba);
  5304. spin_lock_irqsave(hba->host->host_lock, flags);
  5305. if (!err) {
  5306. err = SUCCESS;
  5307. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  5308. } else {
  5309. err = FAILED;
  5310. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  5311. }
  5312. ufshcd_clear_eh_in_progress(hba);
  5313. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5314. ufshcd_release(hba);
  5315. return err;
  5316. }
  5317. /**
  5318. * ufshcd_get_max_icc_level - calculate the ICC level
  5319. * @sup_curr_uA: max. current supported by the regulator
  5320. * @start_scan: row at the desc table to start scan from
  5321. * @buff: power descriptor buffer
  5322. *
  5323. * Returns calculated max ICC level for specific regulator
  5324. */
  5325. static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
  5326. {
  5327. int i;
  5328. int curr_uA;
  5329. u16 data;
  5330. u16 unit;
  5331. for (i = start_scan; i >= 0; i--) {
  5332. data = be16_to_cpup((__be16 *)&buff[2 * i]);
  5333. unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
  5334. ATTR_ICC_LVL_UNIT_OFFSET;
  5335. curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
  5336. switch (unit) {
  5337. case UFSHCD_NANO_AMP:
  5338. curr_uA = curr_uA / 1000;
  5339. break;
  5340. case UFSHCD_MILI_AMP:
  5341. curr_uA = curr_uA * 1000;
  5342. break;
  5343. case UFSHCD_AMP:
  5344. curr_uA = curr_uA * 1000 * 1000;
  5345. break;
  5346. case UFSHCD_MICRO_AMP:
  5347. default:
  5348. break;
  5349. }
  5350. if (sup_curr_uA >= curr_uA)
  5351. break;
  5352. }
  5353. if (i < 0) {
  5354. i = 0;
  5355. pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
  5356. }
  5357. return (u32)i;
  5358. }
  5359. /**
  5360. * ufshcd_calc_icc_level - calculate the max ICC level
  5361. * In case regulators are not initialized we'll return 0
  5362. * @hba: per-adapter instance
  5363. * @desc_buf: power descriptor buffer to extract ICC levels from.
  5364. * @len: length of desc_buff
  5365. *
  5366. * Returns calculated ICC level
  5367. */
  5368. static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
  5369. u8 *desc_buf, int len)
  5370. {
  5371. u32 icc_level = 0;
  5372. if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
  5373. !hba->vreg_info.vccq2) {
  5374. dev_err(hba->dev,
  5375. "%s: Regulator capability was not set, actvIccLevel=%d",
  5376. __func__, icc_level);
  5377. goto out;
  5378. }
  5379. if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
  5380. icc_level = ufshcd_get_max_icc_level(
  5381. hba->vreg_info.vcc->max_uA,
  5382. POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
  5383. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
  5384. if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
  5385. icc_level = ufshcd_get_max_icc_level(
  5386. hba->vreg_info.vccq->max_uA,
  5387. icc_level,
  5388. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
  5389. if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
  5390. icc_level = ufshcd_get_max_icc_level(
  5391. hba->vreg_info.vccq2->max_uA,
  5392. icc_level,
  5393. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
  5394. out:
  5395. return icc_level;
  5396. }
  5397. static void ufshcd_init_icc_levels(struct ufs_hba *hba)
  5398. {
  5399. int ret;
  5400. int buff_len = hba->desc_size.pwr_desc;
  5401. u8 *desc_buf;
  5402. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  5403. if (!desc_buf)
  5404. return;
  5405. ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
  5406. if (ret) {
  5407. dev_err(hba->dev,
  5408. "%s: Failed reading power descriptor.len = %d ret = %d",
  5409. __func__, buff_len, ret);
  5410. goto out;
  5411. }
  5412. hba->init_prefetch_data.icc_level =
  5413. ufshcd_find_max_sup_active_icc_level(hba,
  5414. desc_buf, buff_len);
  5415. dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
  5416. __func__, hba->init_prefetch_data.icc_level);
  5417. ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  5418. QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
  5419. &hba->init_prefetch_data.icc_level);
  5420. if (ret)
  5421. dev_err(hba->dev,
  5422. "%s: Failed configuring bActiveICCLevel = %d ret = %d",
  5423. __func__, hba->init_prefetch_data.icc_level , ret);
  5424. out:
  5425. kfree(desc_buf);
  5426. }
  5427. /**
  5428. * ufshcd_scsi_add_wlus - Adds required W-LUs
  5429. * @hba: per-adapter instance
  5430. *
  5431. * UFS device specification requires the UFS devices to support 4 well known
  5432. * logical units:
  5433. * "REPORT_LUNS" (address: 01h)
  5434. * "UFS Device" (address: 50h)
  5435. * "RPMB" (address: 44h)
  5436. * "BOOT" (address: 30h)
  5437. * UFS device's power management needs to be controlled by "POWER CONDITION"
  5438. * field of SSU (START STOP UNIT) command. But this "power condition" field
  5439. * will take effect only when its sent to "UFS device" well known logical unit
  5440. * hence we require the scsi_device instance to represent this logical unit in
  5441. * order for the UFS host driver to send the SSU command for power management.
  5442. *
  5443. * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
  5444. * Block) LU so user space process can control this LU. User space may also
  5445. * want to have access to BOOT LU.
  5446. *
  5447. * This function adds scsi device instances for each of all well known LUs
  5448. * (except "REPORT LUNS" LU).
  5449. *
  5450. * Returns zero on success (all required W-LUs are added successfully),
  5451. * non-zero error value on failure (if failed to add any of the required W-LU).
  5452. */
  5453. static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
  5454. {
  5455. int ret = 0;
  5456. struct scsi_device *sdev_rpmb;
  5457. struct scsi_device *sdev_boot;
  5458. hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
  5459. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
  5460. if (IS_ERR(hba->sdev_ufs_device)) {
  5461. ret = PTR_ERR(hba->sdev_ufs_device);
  5462. hba->sdev_ufs_device = NULL;
  5463. goto out;
  5464. }
  5465. scsi_device_put(hba->sdev_ufs_device);
  5466. sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
  5467. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
  5468. if (IS_ERR(sdev_rpmb)) {
  5469. ret = PTR_ERR(sdev_rpmb);
  5470. goto remove_sdev_ufs_device;
  5471. }
  5472. scsi_device_put(sdev_rpmb);
  5473. sdev_boot = __scsi_add_device(hba->host, 0, 0,
  5474. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
  5475. if (IS_ERR(sdev_boot))
  5476. dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
  5477. else
  5478. scsi_device_put(sdev_boot);
  5479. goto out;
  5480. remove_sdev_ufs_device:
  5481. scsi_remove_device(hba->sdev_ufs_device);
  5482. out:
  5483. return ret;
  5484. }
  5485. static int ufs_get_device_desc(struct ufs_hba *hba,
  5486. struct ufs_dev_desc *dev_desc)
  5487. {
  5488. int err;
  5489. size_t buff_len;
  5490. u8 model_index;
  5491. u8 *desc_buf;
  5492. buff_len = max_t(size_t, hba->desc_size.dev_desc,
  5493. QUERY_DESC_MAX_SIZE + 1);
  5494. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  5495. if (!desc_buf) {
  5496. err = -ENOMEM;
  5497. goto out;
  5498. }
  5499. err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
  5500. if (err) {
  5501. dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
  5502. __func__, err);
  5503. goto out;
  5504. }
  5505. /*
  5506. * getting vendor (manufacturerID) and Bank Index in big endian
  5507. * format
  5508. */
  5509. dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
  5510. desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
  5511. model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
  5512. /* Zero-pad entire buffer for string termination. */
  5513. memset(desc_buf, 0, buff_len);
  5514. err = ufshcd_read_string_desc(hba, model_index, desc_buf,
  5515. QUERY_DESC_MAX_SIZE, true/*ASCII*/);
  5516. if (err) {
  5517. dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
  5518. __func__, err);
  5519. goto out;
  5520. }
  5521. desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
  5522. strlcpy(dev_desc->model, (desc_buf + QUERY_DESC_HDR_SIZE),
  5523. min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
  5524. MAX_MODEL_LEN));
  5525. /* Null terminate the model string */
  5526. dev_desc->model[MAX_MODEL_LEN] = '\0';
  5527. out:
  5528. kfree(desc_buf);
  5529. return err;
  5530. }
  5531. static void ufs_fixup_device_setup(struct ufs_hba *hba,
  5532. struct ufs_dev_desc *dev_desc)
  5533. {
  5534. struct ufs_dev_fix *f;
  5535. for (f = ufs_fixups; f->quirk; f++) {
  5536. if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
  5537. f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
  5538. (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
  5539. !strcmp(f->card.model, UFS_ANY_MODEL)))
  5540. hba->dev_quirks |= f->quirk;
  5541. }
  5542. }
  5543. /**
  5544. * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
  5545. * @hba: per-adapter instance
  5546. *
  5547. * PA_TActivate parameter can be tuned manually if UniPro version is less than
  5548. * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
  5549. * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
  5550. * the hibern8 exit latency.
  5551. *
  5552. * Returns zero on success, non-zero error value on failure.
  5553. */
  5554. static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
  5555. {
  5556. int ret = 0;
  5557. u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
  5558. ret = ufshcd_dme_peer_get(hba,
  5559. UIC_ARG_MIB_SEL(
  5560. RX_MIN_ACTIVATETIME_CAPABILITY,
  5561. UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
  5562. &peer_rx_min_activatetime);
  5563. if (ret)
  5564. goto out;
  5565. /* make sure proper unit conversion is applied */
  5566. tuned_pa_tactivate =
  5567. ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
  5568. / PA_TACTIVATE_TIME_UNIT_US);
  5569. ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
  5570. tuned_pa_tactivate);
  5571. out:
  5572. return ret;
  5573. }
  5574. /**
  5575. * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
  5576. * @hba: per-adapter instance
  5577. *
  5578. * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
  5579. * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
  5580. * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
  5581. * This optimal value can help reduce the hibern8 exit latency.
  5582. *
  5583. * Returns zero on success, non-zero error value on failure.
  5584. */
  5585. static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
  5586. {
  5587. int ret = 0;
  5588. u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
  5589. u32 max_hibern8_time, tuned_pa_hibern8time;
  5590. ret = ufshcd_dme_get(hba,
  5591. UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
  5592. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
  5593. &local_tx_hibern8_time_cap);
  5594. if (ret)
  5595. goto out;
  5596. ret = ufshcd_dme_peer_get(hba,
  5597. UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
  5598. UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
  5599. &peer_rx_hibern8_time_cap);
  5600. if (ret)
  5601. goto out;
  5602. max_hibern8_time = max(local_tx_hibern8_time_cap,
  5603. peer_rx_hibern8_time_cap);
  5604. /* make sure proper unit conversion is applied */
  5605. tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
  5606. / PA_HIBERN8_TIME_UNIT_US);
  5607. ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
  5608. tuned_pa_hibern8time);
  5609. out:
  5610. return ret;
  5611. }
  5612. /**
  5613. * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
  5614. * less than device PA_TACTIVATE time.
  5615. * @hba: per-adapter instance
  5616. *
  5617. * Some UFS devices require host PA_TACTIVATE to be lower than device
  5618. * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
  5619. * for such devices.
  5620. *
  5621. * Returns zero on success, non-zero error value on failure.
  5622. */
  5623. static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
  5624. {
  5625. int ret = 0;
  5626. u32 granularity, peer_granularity;
  5627. u32 pa_tactivate, peer_pa_tactivate;
  5628. u32 pa_tactivate_us, peer_pa_tactivate_us;
  5629. u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
  5630. ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
  5631. &granularity);
  5632. if (ret)
  5633. goto out;
  5634. ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
  5635. &peer_granularity);
  5636. if (ret)
  5637. goto out;
  5638. if ((granularity < PA_GRANULARITY_MIN_VAL) ||
  5639. (granularity > PA_GRANULARITY_MAX_VAL)) {
  5640. dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
  5641. __func__, granularity);
  5642. return -EINVAL;
  5643. }
  5644. if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
  5645. (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
  5646. dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
  5647. __func__, peer_granularity);
  5648. return -EINVAL;
  5649. }
  5650. ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
  5651. if (ret)
  5652. goto out;
  5653. ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
  5654. &peer_pa_tactivate);
  5655. if (ret)
  5656. goto out;
  5657. pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
  5658. peer_pa_tactivate_us = peer_pa_tactivate *
  5659. gran_to_us_table[peer_granularity - 1];
  5660. if (pa_tactivate_us > peer_pa_tactivate_us) {
  5661. u32 new_peer_pa_tactivate;
  5662. new_peer_pa_tactivate = pa_tactivate_us /
  5663. gran_to_us_table[peer_granularity - 1];
  5664. new_peer_pa_tactivate++;
  5665. ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
  5666. new_peer_pa_tactivate);
  5667. }
  5668. out:
  5669. return ret;
  5670. }
  5671. static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
  5672. {
  5673. if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
  5674. ufshcd_tune_pa_tactivate(hba);
  5675. ufshcd_tune_pa_hibern8time(hba);
  5676. }
  5677. if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
  5678. /* set 1ms timeout for PA_TACTIVATE */
  5679. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
  5680. if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
  5681. ufshcd_quirk_tune_host_pa_tactivate(hba);
  5682. ufshcd_vops_apply_dev_quirks(hba);
  5683. }
  5684. static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
  5685. {
  5686. int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
  5687. hba->ufs_stats.hibern8_exit_cnt = 0;
  5688. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
  5689. memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
  5690. memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
  5691. memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
  5692. memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
  5693. memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
  5694. hba->req_abort_count = 0;
  5695. }
  5696. static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
  5697. {
  5698. int err;
  5699. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
  5700. &hba->desc_size.dev_desc);
  5701. if (err)
  5702. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  5703. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
  5704. &hba->desc_size.pwr_desc);
  5705. if (err)
  5706. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  5707. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
  5708. &hba->desc_size.interc_desc);
  5709. if (err)
  5710. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  5711. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
  5712. &hba->desc_size.conf_desc);
  5713. if (err)
  5714. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  5715. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
  5716. &hba->desc_size.unit_desc);
  5717. if (err)
  5718. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  5719. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
  5720. &hba->desc_size.geom_desc);
  5721. if (err)
  5722. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  5723. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
  5724. &hba->desc_size.hlth_desc);
  5725. if (err)
  5726. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  5727. }
  5728. static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
  5729. {
  5730. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  5731. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  5732. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  5733. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  5734. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  5735. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  5736. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  5737. }
  5738. /**
  5739. * ufshcd_probe_hba - probe hba to detect device and initialize
  5740. * @hba: per-adapter instance
  5741. *
  5742. * Execute link-startup and verify device initialization
  5743. */
  5744. static int ufshcd_probe_hba(struct ufs_hba *hba)
  5745. {
  5746. struct ufs_dev_desc card = {0};
  5747. int ret;
  5748. ktime_t start = ktime_get();
  5749. ret = ufshcd_link_startup(hba);
  5750. if (ret)
  5751. goto out;
  5752. /* set the default level for urgent bkops */
  5753. hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
  5754. hba->is_urgent_bkops_lvl_checked = false;
  5755. /* Debug counters initialization */
  5756. ufshcd_clear_dbg_ufs_stats(hba);
  5757. /* UniPro link is active now */
  5758. ufshcd_set_link_active(hba);
  5759. /* Enable Auto-Hibernate if configured */
  5760. ufshcd_auto_hibern8_enable(hba);
  5761. ret = ufshcd_verify_dev_init(hba);
  5762. if (ret)
  5763. goto out;
  5764. ret = ufshcd_complete_dev_init(hba);
  5765. if (ret)
  5766. goto out;
  5767. /* Init check for device descriptor sizes */
  5768. ufshcd_init_desc_sizes(hba);
  5769. ret = ufs_get_device_desc(hba, &card);
  5770. if (ret) {
  5771. dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
  5772. __func__, ret);
  5773. goto out;
  5774. }
  5775. ufs_fixup_device_setup(hba, &card);
  5776. ufshcd_tune_unipro_params(hba);
  5777. ret = ufshcd_set_vccq_rail_unused(hba,
  5778. (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
  5779. if (ret)
  5780. goto out;
  5781. /* UFS device is also active now */
  5782. ufshcd_set_ufs_dev_active(hba);
  5783. ufshcd_force_reset_auto_bkops(hba);
  5784. hba->wlun_dev_clr_ua = true;
  5785. if (ufshcd_get_max_pwr_mode(hba)) {
  5786. dev_err(hba->dev,
  5787. "%s: Failed getting max supported power mode\n",
  5788. __func__);
  5789. } else {
  5790. ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
  5791. if (ret) {
  5792. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  5793. __func__, ret);
  5794. goto out;
  5795. }
  5796. }
  5797. /* set the state as operational after switching to desired gear */
  5798. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  5799. /*
  5800. * If we are in error handling context or in power management callbacks
  5801. * context, no need to scan the host
  5802. */
  5803. if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  5804. bool flag;
  5805. /* clear any previous UFS device information */
  5806. memset(&hba->dev_info, 0, sizeof(hba->dev_info));
  5807. if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  5808. QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
  5809. hba->dev_info.f_power_on_wp_en = flag;
  5810. if (!hba->is_init_prefetch)
  5811. ufshcd_init_icc_levels(hba);
  5812. /* Add required well known logical units to scsi mid layer */
  5813. ret = ufshcd_scsi_add_wlus(hba);
  5814. if (ret)
  5815. goto out;
  5816. /* Initialize devfreq after UFS device is detected */
  5817. if (ufshcd_is_clkscaling_supported(hba)) {
  5818. memcpy(&hba->clk_scaling.saved_pwr_info.info,
  5819. &hba->pwr_info,
  5820. sizeof(struct ufs_pa_layer_attr));
  5821. hba->clk_scaling.saved_pwr_info.is_valid = true;
  5822. if (!hba->devfreq) {
  5823. ret = ufshcd_devfreq_init(hba);
  5824. if (ret)
  5825. goto out;
  5826. }
  5827. hba->clk_scaling.is_allowed = true;
  5828. }
  5829. scsi_scan_host(hba->host);
  5830. pm_runtime_put_sync(hba->dev);
  5831. }
  5832. if (!hba->is_init_prefetch)
  5833. hba->is_init_prefetch = true;
  5834. out:
  5835. /*
  5836. * If we failed to initialize the device or the device is not
  5837. * present, turn off the power/clocks etc.
  5838. */
  5839. if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  5840. pm_runtime_put_sync(hba->dev);
  5841. ufshcd_exit_clk_scaling(hba);
  5842. ufshcd_hba_exit(hba);
  5843. }
  5844. trace_ufshcd_init(dev_name(hba->dev), ret,
  5845. ktime_to_us(ktime_sub(ktime_get(), start)),
  5846. hba->curr_dev_pwr_mode, hba->uic_link_state);
  5847. return ret;
  5848. }
  5849. /**
  5850. * ufshcd_async_scan - asynchronous execution for probing hba
  5851. * @data: data pointer to pass to this function
  5852. * @cookie: cookie data
  5853. */
  5854. static void ufshcd_async_scan(void *data, async_cookie_t cookie)
  5855. {
  5856. struct ufs_hba *hba = (struct ufs_hba *)data;
  5857. ufshcd_probe_hba(hba);
  5858. }
  5859. static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
  5860. {
  5861. unsigned long flags;
  5862. struct Scsi_Host *host;
  5863. struct ufs_hba *hba;
  5864. int index;
  5865. bool found = false;
  5866. if (!scmd || !scmd->device || !scmd->device->host)
  5867. return BLK_EH_DONE;
  5868. host = scmd->device->host;
  5869. hba = shost_priv(host);
  5870. if (!hba)
  5871. return BLK_EH_DONE;
  5872. spin_lock_irqsave(host->host_lock, flags);
  5873. for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
  5874. if (hba->lrb[index].cmd == scmd) {
  5875. found = true;
  5876. break;
  5877. }
  5878. }
  5879. spin_unlock_irqrestore(host->host_lock, flags);
  5880. /*
  5881. * Bypass SCSI error handling and reset the block layer timer if this
  5882. * SCSI command was not actually dispatched to UFS driver, otherwise
  5883. * let SCSI layer handle the error as usual.
  5884. */
  5885. return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
  5886. }
  5887. static const struct attribute_group *ufshcd_driver_groups[] = {
  5888. &ufs_sysfs_unit_descriptor_group,
  5889. &ufs_sysfs_lun_attributes_group,
  5890. NULL,
  5891. };
  5892. static struct scsi_host_template ufshcd_driver_template = {
  5893. .module = THIS_MODULE,
  5894. .name = UFSHCD,
  5895. .proc_name = UFSHCD,
  5896. .queuecommand = ufshcd_queuecommand,
  5897. .slave_alloc = ufshcd_slave_alloc,
  5898. .slave_configure = ufshcd_slave_configure,
  5899. .slave_destroy = ufshcd_slave_destroy,
  5900. .change_queue_depth = ufshcd_change_queue_depth,
  5901. .eh_abort_handler = ufshcd_abort,
  5902. .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
  5903. .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
  5904. .eh_timed_out = ufshcd_eh_timed_out,
  5905. .this_id = -1,
  5906. .sg_tablesize = SG_ALL,
  5907. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  5908. .can_queue = UFSHCD_CAN_QUEUE,
  5909. .max_host_blocked = 1,
  5910. .track_queue_depth = 1,
  5911. .sdev_groups = ufshcd_driver_groups,
  5912. };
  5913. static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
  5914. int ua)
  5915. {
  5916. int ret;
  5917. if (!vreg)
  5918. return 0;
  5919. /*
  5920. * "set_load" operation shall be required on those regulators
  5921. * which specifically configured current limitation. Otherwise
  5922. * zero max_uA may cause unexpected behavior when regulator is
  5923. * enabled or set as high power mode.
  5924. */
  5925. if (!vreg->max_uA)
  5926. return 0;
  5927. ret = regulator_set_load(vreg->reg, ua);
  5928. if (ret < 0) {
  5929. dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
  5930. __func__, vreg->name, ua, ret);
  5931. }
  5932. return ret;
  5933. }
  5934. static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
  5935. struct ufs_vreg *vreg)
  5936. {
  5937. if (!vreg)
  5938. return 0;
  5939. else if (vreg->unused)
  5940. return 0;
  5941. else
  5942. return ufshcd_config_vreg_load(hba->dev, vreg,
  5943. UFS_VREG_LPM_LOAD_UA);
  5944. }
  5945. static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
  5946. struct ufs_vreg *vreg)
  5947. {
  5948. if (!vreg)
  5949. return 0;
  5950. else if (vreg->unused)
  5951. return 0;
  5952. else
  5953. return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
  5954. }
  5955. static int ufshcd_config_vreg(struct device *dev,
  5956. struct ufs_vreg *vreg, bool on)
  5957. {
  5958. int ret = 0;
  5959. struct regulator *reg;
  5960. const char *name;
  5961. int min_uV, uA_load;
  5962. BUG_ON(!vreg);
  5963. reg = vreg->reg;
  5964. name = vreg->name;
  5965. if (regulator_count_voltages(reg) > 0) {
  5966. if (vreg->min_uV && vreg->max_uV) {
  5967. min_uV = on ? vreg->min_uV : 0;
  5968. ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
  5969. if (ret) {
  5970. dev_err(dev,
  5971. "%s: %s set voltage failed, err=%d\n",
  5972. __func__, name, ret);
  5973. goto out;
  5974. }
  5975. }
  5976. uA_load = on ? vreg->max_uA : 0;
  5977. ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
  5978. if (ret)
  5979. goto out;
  5980. }
  5981. out:
  5982. return ret;
  5983. }
  5984. static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
  5985. {
  5986. int ret = 0;
  5987. if (!vreg)
  5988. goto out;
  5989. else if (vreg->enabled || vreg->unused)
  5990. goto out;
  5991. ret = ufshcd_config_vreg(dev, vreg, true);
  5992. if (!ret)
  5993. ret = regulator_enable(vreg->reg);
  5994. if (!ret)
  5995. vreg->enabled = true;
  5996. else
  5997. dev_err(dev, "%s: %s enable failed, err=%d\n",
  5998. __func__, vreg->name, ret);
  5999. out:
  6000. return ret;
  6001. }
  6002. static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
  6003. {
  6004. int ret = 0;
  6005. if (!vreg)
  6006. goto out;
  6007. else if (!vreg->enabled || vreg->unused)
  6008. goto out;
  6009. ret = regulator_disable(vreg->reg);
  6010. if (!ret) {
  6011. /* ignore errors on applying disable config */
  6012. ufshcd_config_vreg(dev, vreg, false);
  6013. vreg->enabled = false;
  6014. } else {
  6015. dev_err(dev, "%s: %s disable failed, err=%d\n",
  6016. __func__, vreg->name, ret);
  6017. }
  6018. out:
  6019. return ret;
  6020. }
  6021. static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
  6022. {
  6023. int ret = 0;
  6024. struct device *dev = hba->dev;
  6025. struct ufs_vreg_info *info = &hba->vreg_info;
  6026. if (!info)
  6027. goto out;
  6028. ret = ufshcd_toggle_vreg(dev, info->vcc, on);
  6029. if (ret)
  6030. goto out;
  6031. ret = ufshcd_toggle_vreg(dev, info->vccq, on);
  6032. if (ret)
  6033. goto out;
  6034. ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
  6035. if (ret)
  6036. goto out;
  6037. out:
  6038. if (ret) {
  6039. ufshcd_toggle_vreg(dev, info->vccq2, false);
  6040. ufshcd_toggle_vreg(dev, info->vccq, false);
  6041. ufshcd_toggle_vreg(dev, info->vcc, false);
  6042. }
  6043. return ret;
  6044. }
  6045. static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
  6046. {
  6047. struct ufs_vreg_info *info = &hba->vreg_info;
  6048. if (info)
  6049. return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
  6050. return 0;
  6051. }
  6052. static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
  6053. {
  6054. int ret = 0;
  6055. if (!vreg)
  6056. goto out;
  6057. vreg->reg = devm_regulator_get(dev, vreg->name);
  6058. if (IS_ERR(vreg->reg)) {
  6059. ret = PTR_ERR(vreg->reg);
  6060. dev_err(dev, "%s: %s get failed, err=%d\n",
  6061. __func__, vreg->name, ret);
  6062. }
  6063. out:
  6064. return ret;
  6065. }
  6066. static int ufshcd_init_vreg(struct ufs_hba *hba)
  6067. {
  6068. int ret = 0;
  6069. struct device *dev = hba->dev;
  6070. struct ufs_vreg_info *info = &hba->vreg_info;
  6071. if (!info)
  6072. goto out;
  6073. ret = ufshcd_get_vreg(dev, info->vcc);
  6074. if (ret)
  6075. goto out;
  6076. ret = ufshcd_get_vreg(dev, info->vccq);
  6077. if (ret)
  6078. goto out;
  6079. ret = ufshcd_get_vreg(dev, info->vccq2);
  6080. out:
  6081. return ret;
  6082. }
  6083. static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
  6084. {
  6085. struct ufs_vreg_info *info = &hba->vreg_info;
  6086. if (info)
  6087. return ufshcd_get_vreg(hba->dev, info->vdd_hba);
  6088. return 0;
  6089. }
  6090. static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
  6091. {
  6092. int ret = 0;
  6093. struct ufs_vreg_info *info = &hba->vreg_info;
  6094. if (!info)
  6095. goto out;
  6096. else if (!info->vccq)
  6097. goto out;
  6098. if (unused) {
  6099. /* shut off the rail here */
  6100. ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
  6101. /*
  6102. * Mark this rail as no longer used, so it doesn't get enabled
  6103. * later by mistake
  6104. */
  6105. if (!ret)
  6106. info->vccq->unused = true;
  6107. } else {
  6108. /*
  6109. * rail should have been already enabled hence just make sure
  6110. * that unused flag is cleared.
  6111. */
  6112. info->vccq->unused = false;
  6113. }
  6114. out:
  6115. return ret;
  6116. }
  6117. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  6118. bool skip_ref_clk)
  6119. {
  6120. int ret = 0;
  6121. struct ufs_clk_info *clki;
  6122. struct list_head *head = &hba->clk_list_head;
  6123. unsigned long flags;
  6124. ktime_t start = ktime_get();
  6125. bool clk_state_changed = false;
  6126. if (list_empty(head))
  6127. goto out;
  6128. /*
  6129. * vendor specific setup_clocks ops may depend on clocks managed by
  6130. * this standard driver hence call the vendor specific setup_clocks
  6131. * before disabling the clocks managed here.
  6132. */
  6133. if (!on) {
  6134. ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
  6135. if (ret)
  6136. return ret;
  6137. }
  6138. list_for_each_entry(clki, head, list) {
  6139. if (!IS_ERR_OR_NULL(clki->clk)) {
  6140. if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
  6141. continue;
  6142. clk_state_changed = on ^ clki->enabled;
  6143. if (on && !clki->enabled) {
  6144. ret = clk_prepare_enable(clki->clk);
  6145. if (ret) {
  6146. dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
  6147. __func__, clki->name, ret);
  6148. goto out;
  6149. }
  6150. } else if (!on && clki->enabled) {
  6151. clk_disable_unprepare(clki->clk);
  6152. }
  6153. clki->enabled = on;
  6154. dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
  6155. clki->name, on ? "en" : "dis");
  6156. }
  6157. }
  6158. /*
  6159. * vendor specific setup_clocks ops may depend on clocks managed by
  6160. * this standard driver hence call the vendor specific setup_clocks
  6161. * after enabling the clocks managed here.
  6162. */
  6163. if (on) {
  6164. ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
  6165. if (ret)
  6166. return ret;
  6167. }
  6168. out:
  6169. if (ret) {
  6170. list_for_each_entry(clki, head, list) {
  6171. if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
  6172. clk_disable_unprepare(clki->clk);
  6173. }
  6174. } else if (!ret && on) {
  6175. spin_lock_irqsave(hba->host->host_lock, flags);
  6176. hba->clk_gating.state = CLKS_ON;
  6177. trace_ufshcd_clk_gating(dev_name(hba->dev),
  6178. hba->clk_gating.state);
  6179. spin_unlock_irqrestore(hba->host->host_lock, flags);
  6180. }
  6181. if (clk_state_changed)
  6182. trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
  6183. (on ? "on" : "off"),
  6184. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  6185. return ret;
  6186. }
  6187. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
  6188. {
  6189. return __ufshcd_setup_clocks(hba, on, false);
  6190. }
  6191. static int ufshcd_init_clocks(struct ufs_hba *hba)
  6192. {
  6193. int ret = 0;
  6194. struct ufs_clk_info *clki;
  6195. struct device *dev = hba->dev;
  6196. struct list_head *head = &hba->clk_list_head;
  6197. if (list_empty(head))
  6198. goto out;
  6199. list_for_each_entry(clki, head, list) {
  6200. if (!clki->name)
  6201. continue;
  6202. clki->clk = devm_clk_get(dev, clki->name);
  6203. if (IS_ERR(clki->clk)) {
  6204. ret = PTR_ERR(clki->clk);
  6205. dev_err(dev, "%s: %s clk get failed, %d\n",
  6206. __func__, clki->name, ret);
  6207. goto out;
  6208. }
  6209. if (clki->max_freq) {
  6210. ret = clk_set_rate(clki->clk, clki->max_freq);
  6211. if (ret) {
  6212. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  6213. __func__, clki->name,
  6214. clki->max_freq, ret);
  6215. goto out;
  6216. }
  6217. clki->curr_freq = clki->max_freq;
  6218. }
  6219. dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
  6220. clki->name, clk_get_rate(clki->clk));
  6221. }
  6222. out:
  6223. return ret;
  6224. }
  6225. static int ufshcd_variant_hba_init(struct ufs_hba *hba)
  6226. {
  6227. int err = 0;
  6228. if (!hba->vops)
  6229. goto out;
  6230. err = ufshcd_vops_init(hba);
  6231. if (err)
  6232. goto out;
  6233. err = ufshcd_vops_setup_regulators(hba, true);
  6234. if (err)
  6235. goto out_exit;
  6236. goto out;
  6237. out_exit:
  6238. ufshcd_vops_exit(hba);
  6239. out:
  6240. if (err)
  6241. dev_err(hba->dev, "%s: variant %s init failed err %d\n",
  6242. __func__, ufshcd_get_var_name(hba), err);
  6243. return err;
  6244. }
  6245. static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
  6246. {
  6247. if (!hba->vops)
  6248. return;
  6249. ufshcd_vops_setup_regulators(hba, false);
  6250. ufshcd_vops_exit(hba);
  6251. }
  6252. static int ufshcd_hba_init(struct ufs_hba *hba)
  6253. {
  6254. int err;
  6255. /*
  6256. * Handle host controller power separately from the UFS device power
  6257. * rails as it will help controlling the UFS host controller power
  6258. * collapse easily which is different than UFS device power collapse.
  6259. * Also, enable the host controller power before we go ahead with rest
  6260. * of the initialization here.
  6261. */
  6262. err = ufshcd_init_hba_vreg(hba);
  6263. if (err)
  6264. goto out;
  6265. err = ufshcd_setup_hba_vreg(hba, true);
  6266. if (err)
  6267. goto out;
  6268. err = ufshcd_init_clocks(hba);
  6269. if (err)
  6270. goto out_disable_hba_vreg;
  6271. err = ufshcd_setup_clocks(hba, true);
  6272. if (err)
  6273. goto out_disable_hba_vreg;
  6274. err = ufshcd_init_vreg(hba);
  6275. if (err)
  6276. goto out_disable_clks;
  6277. err = ufshcd_setup_vreg(hba, true);
  6278. if (err)
  6279. goto out_disable_clks;
  6280. err = ufshcd_variant_hba_init(hba);
  6281. if (err)
  6282. goto out_disable_vreg;
  6283. hba->is_powered = true;
  6284. goto out;
  6285. out_disable_vreg:
  6286. ufshcd_setup_vreg(hba, false);
  6287. out_disable_clks:
  6288. ufshcd_setup_clocks(hba, false);
  6289. out_disable_hba_vreg:
  6290. ufshcd_setup_hba_vreg(hba, false);
  6291. out:
  6292. return err;
  6293. }
  6294. static void ufshcd_hba_exit(struct ufs_hba *hba)
  6295. {
  6296. if (hba->is_powered) {
  6297. ufshcd_variant_hba_exit(hba);
  6298. ufshcd_setup_vreg(hba, false);
  6299. ufshcd_suspend_clkscaling(hba);
  6300. if (ufshcd_is_clkscaling_supported(hba))
  6301. if (hba->devfreq)
  6302. ufshcd_suspend_clkscaling(hba);
  6303. ufshcd_setup_clocks(hba, false);
  6304. ufshcd_setup_hba_vreg(hba, false);
  6305. hba->is_powered = false;
  6306. }
  6307. }
  6308. static int
  6309. ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
  6310. {
  6311. unsigned char cmd[6] = {REQUEST_SENSE,
  6312. 0,
  6313. 0,
  6314. 0,
  6315. UFSHCD_REQ_SENSE_SIZE,
  6316. 0};
  6317. char *buffer;
  6318. int ret;
  6319. buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
  6320. if (!buffer) {
  6321. ret = -ENOMEM;
  6322. goto out;
  6323. }
  6324. ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
  6325. UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
  6326. msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
  6327. if (ret)
  6328. pr_err("%s: failed with err %d\n", __func__, ret);
  6329. kfree(buffer);
  6330. out:
  6331. return ret;
  6332. }
  6333. /**
  6334. * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
  6335. * power mode
  6336. * @hba: per adapter instance
  6337. * @pwr_mode: device power mode to set
  6338. *
  6339. * Returns 0 if requested power mode is set successfully
  6340. * Returns non-zero if failed to set the requested power mode
  6341. */
  6342. static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
  6343. enum ufs_dev_pwr_mode pwr_mode)
  6344. {
  6345. unsigned char cmd[6] = { START_STOP };
  6346. struct scsi_sense_hdr sshdr;
  6347. struct scsi_device *sdp;
  6348. unsigned long flags;
  6349. int ret;
  6350. spin_lock_irqsave(hba->host->host_lock, flags);
  6351. sdp = hba->sdev_ufs_device;
  6352. if (sdp) {
  6353. ret = scsi_device_get(sdp);
  6354. if (!ret && !scsi_device_online(sdp)) {
  6355. ret = -ENODEV;
  6356. scsi_device_put(sdp);
  6357. }
  6358. } else {
  6359. ret = -ENODEV;
  6360. }
  6361. spin_unlock_irqrestore(hba->host->host_lock, flags);
  6362. if (ret)
  6363. return ret;
  6364. /*
  6365. * If scsi commands fail, the scsi mid-layer schedules scsi error-
  6366. * handling, which would wait for host to be resumed. Since we know
  6367. * we are functional while we are here, skip host resume in error
  6368. * handling context.
  6369. */
  6370. hba->host->eh_noresume = 1;
  6371. if (hba->wlun_dev_clr_ua) {
  6372. ret = ufshcd_send_request_sense(hba, sdp);
  6373. if (ret)
  6374. goto out;
  6375. /* Unit attention condition is cleared now */
  6376. hba->wlun_dev_clr_ua = false;
  6377. }
  6378. cmd[4] = pwr_mode << 4;
  6379. /*
  6380. * Current function would be generally called from the power management
  6381. * callbacks hence set the RQF_PM flag so that it doesn't resume the
  6382. * already suspended childs.
  6383. */
  6384. ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
  6385. START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
  6386. if (ret) {
  6387. sdev_printk(KERN_WARNING, sdp,
  6388. "START_STOP failed for power mode: %d, result %x\n",
  6389. pwr_mode, ret);
  6390. if (driver_byte(ret) == DRIVER_SENSE)
  6391. scsi_print_sense_hdr(sdp, NULL, &sshdr);
  6392. }
  6393. if (!ret)
  6394. hba->curr_dev_pwr_mode = pwr_mode;
  6395. out:
  6396. scsi_device_put(sdp);
  6397. hba->host->eh_noresume = 0;
  6398. return ret;
  6399. }
  6400. static int ufshcd_link_state_transition(struct ufs_hba *hba,
  6401. enum uic_link_state req_link_state,
  6402. int check_for_bkops)
  6403. {
  6404. int ret = 0;
  6405. if (req_link_state == hba->uic_link_state)
  6406. return 0;
  6407. if (req_link_state == UIC_LINK_HIBERN8_STATE) {
  6408. ret = ufshcd_uic_hibern8_enter(hba);
  6409. if (!ret)
  6410. ufshcd_set_link_hibern8(hba);
  6411. else
  6412. goto out;
  6413. }
  6414. /*
  6415. * If autobkops is enabled, link can't be turned off because
  6416. * turning off the link would also turn off the device.
  6417. */
  6418. else if ((req_link_state == UIC_LINK_OFF_STATE) &&
  6419. (!check_for_bkops || (check_for_bkops &&
  6420. !hba->auto_bkops_enabled))) {
  6421. /*
  6422. * Let's make sure that link is in low power mode, we are doing
  6423. * this currently by putting the link in Hibern8. Otherway to
  6424. * put the link in low power mode is to send the DME end point
  6425. * to device and then send the DME reset command to local
  6426. * unipro. But putting the link in hibern8 is much faster.
  6427. */
  6428. ret = ufshcd_uic_hibern8_enter(hba);
  6429. if (ret)
  6430. goto out;
  6431. /*
  6432. * Change controller state to "reset state" which
  6433. * should also put the link in off/reset state
  6434. */
  6435. ufshcd_hba_stop(hba, true);
  6436. /*
  6437. * TODO: Check if we need any delay to make sure that
  6438. * controller is reset
  6439. */
  6440. ufshcd_set_link_off(hba);
  6441. }
  6442. out:
  6443. return ret;
  6444. }
  6445. static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
  6446. {
  6447. /*
  6448. * It seems some UFS devices may keep drawing more than sleep current
  6449. * (atleast for 500us) from UFS rails (especially from VCCQ rail).
  6450. * To avoid this situation, add 2ms delay before putting these UFS
  6451. * rails in LPM mode.
  6452. */
  6453. if (!ufshcd_is_link_active(hba) &&
  6454. hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
  6455. usleep_range(2000, 2100);
  6456. /*
  6457. * If UFS device is either in UFS_Sleep turn off VCC rail to save some
  6458. * power.
  6459. *
  6460. * If UFS device and link is in OFF state, all power supplies (VCC,
  6461. * VCCQ, VCCQ2) can be turned off if power on write protect is not
  6462. * required. If UFS link is inactive (Hibern8 or OFF state) and device
  6463. * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
  6464. *
  6465. * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
  6466. * in low power state which would save some power.
  6467. */
  6468. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  6469. !hba->dev_info.is_lu_power_on_wp) {
  6470. ufshcd_setup_vreg(hba, false);
  6471. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  6472. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  6473. if (!ufshcd_is_link_active(hba)) {
  6474. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  6475. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
  6476. }
  6477. }
  6478. }
  6479. static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
  6480. {
  6481. int ret = 0;
  6482. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  6483. !hba->dev_info.is_lu_power_on_wp) {
  6484. ret = ufshcd_setup_vreg(hba, true);
  6485. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  6486. if (!ret && !ufshcd_is_link_active(hba)) {
  6487. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
  6488. if (ret)
  6489. goto vcc_disable;
  6490. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
  6491. if (ret)
  6492. goto vccq_lpm;
  6493. }
  6494. ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
  6495. }
  6496. goto out;
  6497. vccq_lpm:
  6498. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  6499. vcc_disable:
  6500. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  6501. out:
  6502. return ret;
  6503. }
  6504. static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
  6505. {
  6506. if (ufshcd_is_link_off(hba))
  6507. ufshcd_setup_hba_vreg(hba, false);
  6508. }
  6509. static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
  6510. {
  6511. if (ufshcd_is_link_off(hba))
  6512. ufshcd_setup_hba_vreg(hba, true);
  6513. }
  6514. /**
  6515. * ufshcd_suspend - helper function for suspend operations
  6516. * @hba: per adapter instance
  6517. * @pm_op: desired low power operation type
  6518. *
  6519. * This function will try to put the UFS device and link into low power
  6520. * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
  6521. * (System PM level).
  6522. *
  6523. * If this function is called during shutdown, it will make sure that
  6524. * both UFS device and UFS link is powered off.
  6525. *
  6526. * NOTE: UFS device & link must be active before we enter in this function.
  6527. *
  6528. * Returns 0 for success and non-zero for failure
  6529. */
  6530. static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  6531. {
  6532. int ret = 0;
  6533. enum ufs_pm_level pm_lvl;
  6534. enum ufs_dev_pwr_mode req_dev_pwr_mode;
  6535. enum uic_link_state req_link_state;
  6536. hba->pm_op_in_progress = 1;
  6537. if (!ufshcd_is_shutdown_pm(pm_op)) {
  6538. pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
  6539. hba->rpm_lvl : hba->spm_lvl;
  6540. req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
  6541. req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
  6542. } else {
  6543. req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
  6544. req_link_state = UIC_LINK_OFF_STATE;
  6545. }
  6546. /*
  6547. * If we can't transition into any of the low power modes
  6548. * just gate the clocks.
  6549. */
  6550. ufshcd_hold(hba, false);
  6551. hba->clk_gating.is_suspended = true;
  6552. if (hba->clk_scaling.is_allowed) {
  6553. cancel_work_sync(&hba->clk_scaling.suspend_work);
  6554. cancel_work_sync(&hba->clk_scaling.resume_work);
  6555. ufshcd_suspend_clkscaling(hba);
  6556. }
  6557. if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
  6558. req_link_state == UIC_LINK_ACTIVE_STATE) {
  6559. goto disable_clks;
  6560. }
  6561. if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
  6562. (req_link_state == hba->uic_link_state))
  6563. goto enable_gating;
  6564. /* UFS device & link must be active before we enter in this function */
  6565. if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
  6566. ret = -EINVAL;
  6567. goto enable_gating;
  6568. }
  6569. if (ufshcd_is_runtime_pm(pm_op)) {
  6570. if (ufshcd_can_autobkops_during_suspend(hba)) {
  6571. /*
  6572. * The device is idle with no requests in the queue,
  6573. * allow background operations if bkops status shows
  6574. * that performance might be impacted.
  6575. */
  6576. ret = ufshcd_urgent_bkops(hba);
  6577. if (ret)
  6578. goto enable_gating;
  6579. } else {
  6580. /* make sure that auto bkops is disabled */
  6581. ufshcd_disable_auto_bkops(hba);
  6582. }
  6583. }
  6584. if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
  6585. ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
  6586. !ufshcd_is_runtime_pm(pm_op))) {
  6587. /* ensure that bkops is disabled */
  6588. ufshcd_disable_auto_bkops(hba);
  6589. ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
  6590. if (ret)
  6591. goto enable_gating;
  6592. }
  6593. ret = ufshcd_link_state_transition(hba, req_link_state, 1);
  6594. if (ret)
  6595. goto set_dev_active;
  6596. ufshcd_vreg_set_lpm(hba);
  6597. disable_clks:
  6598. /*
  6599. * Call vendor specific suspend callback. As these callbacks may access
  6600. * vendor specific host controller register space call them before the
  6601. * host clocks are ON.
  6602. */
  6603. ret = ufshcd_vops_suspend(hba, pm_op);
  6604. if (ret)
  6605. goto set_link_active;
  6606. if (!ufshcd_is_link_active(hba))
  6607. ufshcd_setup_clocks(hba, false);
  6608. else
  6609. /* If link is active, device ref_clk can't be switched off */
  6610. __ufshcd_setup_clocks(hba, false, true);
  6611. hba->clk_gating.state = CLKS_OFF;
  6612. trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
  6613. /*
  6614. * Disable the host irq as host controller as there won't be any
  6615. * host controller transaction expected till resume.
  6616. */
  6617. ufshcd_disable_irq(hba);
  6618. /* Put the host controller in low power mode if possible */
  6619. ufshcd_hba_vreg_set_lpm(hba);
  6620. goto out;
  6621. set_link_active:
  6622. if (hba->clk_scaling.is_allowed)
  6623. ufshcd_resume_clkscaling(hba);
  6624. ufshcd_vreg_set_hpm(hba);
  6625. if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
  6626. ufshcd_set_link_active(hba);
  6627. else if (ufshcd_is_link_off(hba))
  6628. ufshcd_host_reset_and_restore(hba);
  6629. set_dev_active:
  6630. if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
  6631. ufshcd_disable_auto_bkops(hba);
  6632. enable_gating:
  6633. if (hba->clk_scaling.is_allowed)
  6634. ufshcd_resume_clkscaling(hba);
  6635. hba->clk_gating.is_suspended = false;
  6636. ufshcd_release(hba);
  6637. out:
  6638. hba->pm_op_in_progress = 0;
  6639. return ret;
  6640. }
  6641. /**
  6642. * ufshcd_resume - helper function for resume operations
  6643. * @hba: per adapter instance
  6644. * @pm_op: runtime PM or system PM
  6645. *
  6646. * This function basically brings the UFS device, UniPro link and controller
  6647. * to active state.
  6648. *
  6649. * Returns 0 for success and non-zero for failure
  6650. */
  6651. static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  6652. {
  6653. int ret;
  6654. enum uic_link_state old_link_state;
  6655. hba->pm_op_in_progress = 1;
  6656. old_link_state = hba->uic_link_state;
  6657. ufshcd_hba_vreg_set_hpm(hba);
  6658. /* Make sure clocks are enabled before accessing controller */
  6659. ret = ufshcd_setup_clocks(hba, true);
  6660. if (ret)
  6661. goto out;
  6662. /* enable the host irq as host controller would be active soon */
  6663. ret = ufshcd_enable_irq(hba);
  6664. if (ret)
  6665. goto disable_irq_and_vops_clks;
  6666. ret = ufshcd_vreg_set_hpm(hba);
  6667. if (ret)
  6668. goto disable_irq_and_vops_clks;
  6669. /*
  6670. * Call vendor specific resume callback. As these callbacks may access
  6671. * vendor specific host controller register space call them when the
  6672. * host clocks are ON.
  6673. */
  6674. ret = ufshcd_vops_resume(hba, pm_op);
  6675. if (ret)
  6676. goto disable_vreg;
  6677. if (ufshcd_is_link_hibern8(hba)) {
  6678. ret = ufshcd_uic_hibern8_exit(hba);
  6679. if (!ret)
  6680. ufshcd_set_link_active(hba);
  6681. else
  6682. goto vendor_suspend;
  6683. } else if (ufshcd_is_link_off(hba)) {
  6684. ret = ufshcd_host_reset_and_restore(hba);
  6685. /*
  6686. * ufshcd_host_reset_and_restore() should have already
  6687. * set the link state as active
  6688. */
  6689. if (ret || !ufshcd_is_link_active(hba))
  6690. goto vendor_suspend;
  6691. }
  6692. if (!ufshcd_is_ufs_dev_active(hba)) {
  6693. ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
  6694. if (ret)
  6695. goto set_old_link_state;
  6696. }
  6697. if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
  6698. ufshcd_enable_auto_bkops(hba);
  6699. else
  6700. /*
  6701. * If BKOPs operations are urgently needed at this moment then
  6702. * keep auto-bkops enabled or else disable it.
  6703. */
  6704. ufshcd_urgent_bkops(hba);
  6705. hba->clk_gating.is_suspended = false;
  6706. if (hba->clk_scaling.is_allowed)
  6707. ufshcd_resume_clkscaling(hba);
  6708. /* Schedule clock gating in case of no access to UFS device yet */
  6709. ufshcd_release(hba);
  6710. /* Enable Auto-Hibernate if configured */
  6711. ufshcd_auto_hibern8_enable(hba);
  6712. goto out;
  6713. set_old_link_state:
  6714. ufshcd_link_state_transition(hba, old_link_state, 0);
  6715. vendor_suspend:
  6716. ufshcd_vops_suspend(hba, pm_op);
  6717. disable_vreg:
  6718. ufshcd_vreg_set_lpm(hba);
  6719. disable_irq_and_vops_clks:
  6720. ufshcd_disable_irq(hba);
  6721. if (hba->clk_scaling.is_allowed)
  6722. ufshcd_suspend_clkscaling(hba);
  6723. ufshcd_setup_clocks(hba, false);
  6724. out:
  6725. hba->pm_op_in_progress = 0;
  6726. return ret;
  6727. }
  6728. /**
  6729. * ufshcd_system_suspend - system suspend routine
  6730. * @hba: per adapter instance
  6731. *
  6732. * Check the description of ufshcd_suspend() function for more details.
  6733. *
  6734. * Returns 0 for success and non-zero for failure
  6735. */
  6736. int ufshcd_system_suspend(struct ufs_hba *hba)
  6737. {
  6738. int ret = 0;
  6739. ktime_t start = ktime_get();
  6740. if (!hba || !hba->is_powered)
  6741. return 0;
  6742. if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
  6743. hba->curr_dev_pwr_mode) &&
  6744. (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
  6745. hba->uic_link_state))
  6746. goto out;
  6747. if (pm_runtime_suspended(hba->dev)) {
  6748. /*
  6749. * UFS device and/or UFS link low power states during runtime
  6750. * suspend seems to be different than what is expected during
  6751. * system suspend. Hence runtime resume the devic & link and
  6752. * let the system suspend low power states to take effect.
  6753. * TODO: If resume takes longer time, we might have optimize
  6754. * it in future by not resuming everything if possible.
  6755. */
  6756. ret = ufshcd_runtime_resume(hba);
  6757. if (ret)
  6758. goto out;
  6759. }
  6760. ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
  6761. out:
  6762. trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
  6763. ktime_to_us(ktime_sub(ktime_get(), start)),
  6764. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6765. if (!ret)
  6766. hba->is_sys_suspended = true;
  6767. return ret;
  6768. }
  6769. EXPORT_SYMBOL(ufshcd_system_suspend);
  6770. /**
  6771. * ufshcd_system_resume - system resume routine
  6772. * @hba: per adapter instance
  6773. *
  6774. * Returns 0 for success and non-zero for failure
  6775. */
  6776. int ufshcd_system_resume(struct ufs_hba *hba)
  6777. {
  6778. int ret = 0;
  6779. ktime_t start = ktime_get();
  6780. if (!hba)
  6781. return -EINVAL;
  6782. if (!hba->is_powered || pm_runtime_suspended(hba->dev))
  6783. /*
  6784. * Let the runtime resume take care of resuming
  6785. * if runtime suspended.
  6786. */
  6787. goto out;
  6788. else
  6789. ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
  6790. out:
  6791. trace_ufshcd_system_resume(dev_name(hba->dev), ret,
  6792. ktime_to_us(ktime_sub(ktime_get(), start)),
  6793. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6794. if (!ret)
  6795. hba->is_sys_suspended = false;
  6796. return ret;
  6797. }
  6798. EXPORT_SYMBOL(ufshcd_system_resume);
  6799. /**
  6800. * ufshcd_runtime_suspend - runtime suspend routine
  6801. * @hba: per adapter instance
  6802. *
  6803. * Check the description of ufshcd_suspend() function for more details.
  6804. *
  6805. * Returns 0 for success and non-zero for failure
  6806. */
  6807. int ufshcd_runtime_suspend(struct ufs_hba *hba)
  6808. {
  6809. int ret = 0;
  6810. ktime_t start = ktime_get();
  6811. if (!hba)
  6812. return -EINVAL;
  6813. if (!hba->is_powered)
  6814. goto out;
  6815. else
  6816. ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
  6817. out:
  6818. trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
  6819. ktime_to_us(ktime_sub(ktime_get(), start)),
  6820. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6821. return ret;
  6822. }
  6823. EXPORT_SYMBOL(ufshcd_runtime_suspend);
  6824. /**
  6825. * ufshcd_runtime_resume - runtime resume routine
  6826. * @hba: per adapter instance
  6827. *
  6828. * This function basically brings the UFS device, UniPro link and controller
  6829. * to active state. Following operations are done in this function:
  6830. *
  6831. * 1. Turn on all the controller related clocks
  6832. * 2. Bring the UniPro link out of Hibernate state
  6833. * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
  6834. * to active state.
  6835. * 4. If auto-bkops is enabled on the device, disable it.
  6836. *
  6837. * So following would be the possible power state after this function return
  6838. * successfully:
  6839. * S1: UFS device in Active state with VCC rail ON
  6840. * UniPro link in Active state
  6841. * All the UFS/UniPro controller clocks are ON
  6842. *
  6843. * Returns 0 for success and non-zero for failure
  6844. */
  6845. int ufshcd_runtime_resume(struct ufs_hba *hba)
  6846. {
  6847. int ret = 0;
  6848. ktime_t start = ktime_get();
  6849. if (!hba)
  6850. return -EINVAL;
  6851. if (!hba->is_powered)
  6852. goto out;
  6853. else
  6854. ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
  6855. out:
  6856. trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
  6857. ktime_to_us(ktime_sub(ktime_get(), start)),
  6858. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6859. return ret;
  6860. }
  6861. EXPORT_SYMBOL(ufshcd_runtime_resume);
  6862. int ufshcd_runtime_idle(struct ufs_hba *hba)
  6863. {
  6864. return 0;
  6865. }
  6866. EXPORT_SYMBOL(ufshcd_runtime_idle);
  6867. /**
  6868. * ufshcd_shutdown - shutdown routine
  6869. * @hba: per adapter instance
  6870. *
  6871. * This function would power off both UFS device and UFS link.
  6872. *
  6873. * Returns 0 always to allow force shutdown even in case of errors.
  6874. */
  6875. int ufshcd_shutdown(struct ufs_hba *hba)
  6876. {
  6877. int ret = 0;
  6878. if (!hba->is_powered)
  6879. goto out;
  6880. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
  6881. goto out;
  6882. pm_runtime_get_sync(hba->dev);
  6883. ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
  6884. out:
  6885. if (ret)
  6886. dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
  6887. /* allow force shutdown even in case of errors */
  6888. return 0;
  6889. }
  6890. EXPORT_SYMBOL(ufshcd_shutdown);
  6891. /**
  6892. * ufshcd_remove - de-allocate SCSI host and host memory space
  6893. * data structure memory
  6894. * @hba: per adapter instance
  6895. */
  6896. void ufshcd_remove(struct ufs_hba *hba)
  6897. {
  6898. ufs_sysfs_remove_nodes(hba->dev);
  6899. scsi_remove_host(hba->host);
  6900. /* disable interrupts */
  6901. ufshcd_disable_intr(hba, hba->intr_mask);
  6902. ufshcd_hba_stop(hba, true);
  6903. ufshcd_exit_clk_scaling(hba);
  6904. ufshcd_exit_clk_gating(hba);
  6905. if (ufshcd_is_clkscaling_supported(hba))
  6906. device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
  6907. ufshcd_hba_exit(hba);
  6908. }
  6909. EXPORT_SYMBOL_GPL(ufshcd_remove);
  6910. /**
  6911. * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
  6912. * @hba: pointer to Host Bus Adapter (HBA)
  6913. */
  6914. void ufshcd_dealloc_host(struct ufs_hba *hba)
  6915. {
  6916. scsi_host_put(hba->host);
  6917. }
  6918. EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
  6919. /**
  6920. * ufshcd_set_dma_mask - Set dma mask based on the controller
  6921. * addressing capability
  6922. * @hba: per adapter instance
  6923. *
  6924. * Returns 0 for success, non-zero for failure
  6925. */
  6926. static int ufshcd_set_dma_mask(struct ufs_hba *hba)
  6927. {
  6928. if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
  6929. if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
  6930. return 0;
  6931. }
  6932. return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
  6933. }
  6934. /**
  6935. * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
  6936. * @dev: pointer to device handle
  6937. * @hba_handle: driver private handle
  6938. * Returns 0 on success, non-zero value on failure
  6939. */
  6940. int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
  6941. {
  6942. struct Scsi_Host *host;
  6943. struct ufs_hba *hba;
  6944. int err = 0;
  6945. if (!dev) {
  6946. dev_err(dev,
  6947. "Invalid memory reference for dev is NULL\n");
  6948. err = -ENODEV;
  6949. goto out_error;
  6950. }
  6951. host = scsi_host_alloc(&ufshcd_driver_template,
  6952. sizeof(struct ufs_hba));
  6953. if (!host) {
  6954. dev_err(dev, "scsi_host_alloc failed\n");
  6955. err = -ENOMEM;
  6956. goto out_error;
  6957. }
  6958. /*
  6959. * Do not use blk-mq at this time because blk-mq does not support
  6960. * runtime pm.
  6961. */
  6962. host->use_blk_mq = false;
  6963. hba = shost_priv(host);
  6964. hba->host = host;
  6965. hba->dev = dev;
  6966. *hba_handle = hba;
  6967. INIT_LIST_HEAD(&hba->clk_list_head);
  6968. out_error:
  6969. return err;
  6970. }
  6971. EXPORT_SYMBOL(ufshcd_alloc_host);
  6972. /**
  6973. * ufshcd_init - Driver initialization routine
  6974. * @hba: per-adapter instance
  6975. * @mmio_base: base register address
  6976. * @irq: Interrupt line of device
  6977. * Returns 0 on success, non-zero value on failure
  6978. */
  6979. int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
  6980. {
  6981. int err;
  6982. struct Scsi_Host *host = hba->host;
  6983. struct device *dev = hba->dev;
  6984. if (!mmio_base) {
  6985. dev_err(hba->dev,
  6986. "Invalid memory reference for mmio_base is NULL\n");
  6987. err = -ENODEV;
  6988. goto out_error;
  6989. }
  6990. hba->mmio_base = mmio_base;
  6991. hba->irq = irq;
  6992. /* Set descriptor lengths to specification defaults */
  6993. ufshcd_def_desc_sizes(hba);
  6994. err = ufshcd_hba_init(hba);
  6995. if (err)
  6996. goto out_error;
  6997. /* Read capabilities registers */
  6998. ufshcd_hba_capabilities(hba);
  6999. /* Get UFS version supported by the controller */
  7000. hba->ufs_version = ufshcd_get_ufs_version(hba);
  7001. if ((hba->ufs_version != UFSHCI_VERSION_10) &&
  7002. (hba->ufs_version != UFSHCI_VERSION_11) &&
  7003. (hba->ufs_version != UFSHCI_VERSION_20) &&
  7004. (hba->ufs_version != UFSHCI_VERSION_21))
  7005. dev_err(hba->dev, "invalid UFS version 0x%x\n",
  7006. hba->ufs_version);
  7007. /* Get Interrupt bit mask per version */
  7008. hba->intr_mask = ufshcd_get_intr_mask(hba);
  7009. err = ufshcd_set_dma_mask(hba);
  7010. if (err) {
  7011. dev_err(hba->dev, "set dma mask failed\n");
  7012. goto out_disable;
  7013. }
  7014. /* Allocate memory for host memory space */
  7015. err = ufshcd_memory_alloc(hba);
  7016. if (err) {
  7017. dev_err(hba->dev, "Memory allocation failed\n");
  7018. goto out_disable;
  7019. }
  7020. /* Configure LRB */
  7021. ufshcd_host_memory_configure(hba);
  7022. host->can_queue = hba->nutrs;
  7023. host->cmd_per_lun = hba->nutrs;
  7024. host->max_id = UFSHCD_MAX_ID;
  7025. host->max_lun = UFS_MAX_LUNS;
  7026. host->max_channel = UFSHCD_MAX_CHANNEL;
  7027. host->unique_id = host->host_no;
  7028. host->max_cmd_len = MAX_CDB_SIZE;
  7029. hba->max_pwr_info.is_valid = false;
  7030. /* Initailize wait queue for task management */
  7031. init_waitqueue_head(&hba->tm_wq);
  7032. init_waitqueue_head(&hba->tm_tag_wq);
  7033. /* Initialize work queues */
  7034. INIT_WORK(&hba->eh_work, ufshcd_err_handler);
  7035. INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
  7036. /* Initialize UIC command mutex */
  7037. mutex_init(&hba->uic_cmd_mutex);
  7038. /* Initialize mutex for device management commands */
  7039. mutex_init(&hba->dev_cmd.lock);
  7040. init_rwsem(&hba->clk_scaling_lock);
  7041. /* Initialize device management tag acquire wait queue */
  7042. init_waitqueue_head(&hba->dev_cmd.tag_wq);
  7043. ufshcd_init_clk_gating(hba);
  7044. ufshcd_init_clk_scaling(hba);
  7045. /*
  7046. * In order to avoid any spurious interrupt immediately after
  7047. * registering UFS controller interrupt handler, clear any pending UFS
  7048. * interrupt status and disable all the UFS interrupts.
  7049. */
  7050. ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
  7051. REG_INTERRUPT_STATUS);
  7052. ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
  7053. /*
  7054. * Make sure that UFS interrupts are disabled and any pending interrupt
  7055. * status is cleared before registering UFS interrupt handler.
  7056. */
  7057. mb();
  7058. /* IRQ registration */
  7059. err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  7060. if (err) {
  7061. dev_err(hba->dev, "request irq failed\n");
  7062. goto exit_gating;
  7063. } else {
  7064. hba->is_irq_enabled = true;
  7065. }
  7066. err = scsi_add_host(host, hba->dev);
  7067. if (err) {
  7068. dev_err(hba->dev, "scsi_add_host failed\n");
  7069. goto exit_gating;
  7070. }
  7071. /* Host controller enable */
  7072. err = ufshcd_hba_enable(hba);
  7073. if (err) {
  7074. dev_err(hba->dev, "Host controller enable failed\n");
  7075. ufshcd_print_host_regs(hba);
  7076. ufshcd_print_host_state(hba);
  7077. goto out_remove_scsi_host;
  7078. }
  7079. /*
  7080. * Set the default power management level for runtime and system PM.
  7081. * Default power saving mode is to keep UFS link in Hibern8 state
  7082. * and UFS device in sleep state.
  7083. */
  7084. hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
  7085. UFS_SLEEP_PWR_MODE,
  7086. UIC_LINK_HIBERN8_STATE);
  7087. hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
  7088. UFS_SLEEP_PWR_MODE,
  7089. UIC_LINK_HIBERN8_STATE);
  7090. /* Set the default auto-hiberate idle timer value to 150 ms */
  7091. if (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) {
  7092. hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
  7093. FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
  7094. }
  7095. /* Hold auto suspend until async scan completes */
  7096. pm_runtime_get_sync(dev);
  7097. atomic_set(&hba->scsi_block_reqs_cnt, 0);
  7098. /*
  7099. * We are assuming that device wasn't put in sleep/power-down
  7100. * state exclusively during the boot stage before kernel.
  7101. * This assumption helps avoid doing link startup twice during
  7102. * ufshcd_probe_hba().
  7103. */
  7104. ufshcd_set_ufs_dev_active(hba);
  7105. async_schedule(ufshcd_async_scan, hba);
  7106. ufs_sysfs_add_nodes(hba->dev);
  7107. return 0;
  7108. out_remove_scsi_host:
  7109. scsi_remove_host(hba->host);
  7110. exit_gating:
  7111. ufshcd_exit_clk_scaling(hba);
  7112. ufshcd_exit_clk_gating(hba);
  7113. out_disable:
  7114. hba->is_irq_enabled = false;
  7115. ufshcd_hba_exit(hba);
  7116. out_error:
  7117. return err;
  7118. }
  7119. EXPORT_SYMBOL_GPL(ufshcd_init);
  7120. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
  7121. MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
  7122. MODULE_DESCRIPTION("Generic UFS host controller driver Core");
  7123. MODULE_LICENSE("GPL");
  7124. MODULE_VERSION(UFSHCD_DRIVER_VERSION);