| 1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768 |
- /* SPDX-License-Identifier: GPL-2.0 */
- /*
- * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * Inspired by pxafb.h
- */
- #ifndef __ASM_PLAT_FB_S3C2410_H
- #define __ASM_PLAT_FB_S3C2410_H __FILE__
- struct s3c2410fb_hw {
- unsigned long lcdcon1;
- unsigned long lcdcon2;
- unsigned long lcdcon3;
- unsigned long lcdcon4;
- unsigned long lcdcon5;
- };
- /* LCD description */
- struct s3c2410fb_display {
- /* LCD type */
- unsigned type;
- /* Screen size */
- unsigned short width;
- unsigned short height;
- /* Screen info */
- unsigned short xres;
- unsigned short yres;
- unsigned short bpp;
- unsigned pixclock; /* pixclock in picoseconds */
- unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
- unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
- unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
- unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
- unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
- unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
- /* lcd configuration registers */
- unsigned long lcdcon5;
- };
- struct s3c2410fb_mach_info {
- struct s3c2410fb_display *displays; /* attached displays info */
- unsigned num_displays; /* number of defined displays */
- unsigned default_display;
- /* GPIOs */
- unsigned long gpcup;
- unsigned long gpcup_mask;
- unsigned long gpccon;
- unsigned long gpccon_mask;
- unsigned long gpdup;
- unsigned long gpdup_mask;
- unsigned long gpdcon;
- unsigned long gpdcon_mask;
- /* lpc3600 control register */
- unsigned long lpcsel;
- };
- extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
- #endif /* __ASM_PLAT_FB_S3C2410_H */
|
