spl.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 - 2016 Xilinx, Inc.
  4. *
  5. * Michal Simek <michal.simek@xilinx.com>
  6. */
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <spl.h>
  10. #include <asm/io.h>
  11. #include <asm/spl.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/sys_proto.h>
  14. void board_init_f(ulong dummy)
  15. {
  16. board_early_init_f();
  17. board_early_init_r();
  18. #ifdef CONFIG_DEBUG_UART
  19. /* Uart debug for sure */
  20. debug_uart_init();
  21. puts("Debug uart enabled\n"); /* or printch() */
  22. #endif
  23. /* Delay is required for clocks to be propagated */
  24. udelay(1000000);
  25. /* Clear the BSS */
  26. memset(__bss_start, 0, __bss_end - __bss_start);
  27. /* No need to call timer init - it is empty for ZynqMP */
  28. board_init_r(NULL, 0);
  29. }
  30. static void ps_mode_reset(ulong mode)
  31. {
  32. writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  33. &crlapb_base->boot_pin_ctrl);
  34. udelay(5);
  35. writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
  36. mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  37. &crlapb_base->boot_pin_ctrl);
  38. }
  39. /*
  40. * Set default PS_MODE1 which is used for USB ULPI phy reset
  41. * Also other resets can be connected to this certain pin
  42. */
  43. #ifndef MODE_RESET
  44. # define MODE_RESET PS_MODE1
  45. #endif
  46. #ifdef CONFIG_SPL_BOARD_INIT
  47. void spl_board_init(void)
  48. {
  49. preloader_console_init();
  50. ps_mode_reset(MODE_RESET);
  51. board_init();
  52. }
  53. #endif
  54. u32 spl_boot_device(void)
  55. {
  56. u32 reg = 0;
  57. u8 bootmode;
  58. #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
  59. /* Change default boot mode at run-time */
  60. writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
  61. &crlapb_base->boot_mode);
  62. #endif
  63. reg = readl(&crlapb_base->boot_mode);
  64. if (reg >> BOOT_MODE_ALT_SHIFT)
  65. reg >>= BOOT_MODE_ALT_SHIFT;
  66. bootmode = reg & BOOT_MODES_MASK;
  67. switch (bootmode) {
  68. case JTAG_MODE:
  69. return BOOT_DEVICE_RAM;
  70. #ifdef CONFIG_SPL_MMC_SUPPORT
  71. case SD_MODE1:
  72. case SD1_LSHFT_MODE: /* not working on silicon v1 */
  73. /* if both controllers enabled, then these two are the second controller */
  74. #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
  75. return BOOT_DEVICE_MMC2;
  76. /* else, fall through, the one SDHCI controller that is enabled is number 1 */
  77. #endif
  78. case SD_MODE:
  79. case EMMC_MODE:
  80. return BOOT_DEVICE_MMC1;
  81. #endif
  82. #ifdef CONFIG_SPL_DFU_SUPPORT
  83. case USB_MODE:
  84. return BOOT_DEVICE_DFU;
  85. #endif
  86. #ifdef CONFIG_SPL_SATA_SUPPORT
  87. case SW_SATA_MODE:
  88. return BOOT_DEVICE_SATA;
  89. #endif
  90. #ifdef CONFIG_SPL_SPI_SUPPORT
  91. case QSPI_MODE_24BIT:
  92. case QSPI_MODE_32BIT:
  93. return BOOT_DEVICE_SPI;
  94. #endif
  95. default:
  96. printf("Invalid Boot Mode:0x%x\n", bootmode);
  97. break;
  98. }
  99. return 0;
  100. }
  101. #ifdef CONFIG_SPL_OS_BOOT
  102. int spl_start_uboot(void)
  103. {
  104. handoff_setup();
  105. return 0;
  106. }
  107. #endif
  108. #ifdef CONFIG_SPL_LOAD_FIT
  109. int board_fit_config_name_match(const char *name)
  110. {
  111. /* Just empty function now - can't decide what to choose */
  112. debug("%s: %s\n", __func__, name);
  113. return 0;
  114. }
  115. #endif