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linux-arkmicro
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u-boot
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arch
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arm
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include
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asm
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arch-armada100
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armada100.h

armada100.h 1.7 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * (C) Copyright 2010
    4. 

  4.  * Marvell Semiconductor <www.marvell.com>
    5. 

  5.  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
    6. 

  6.  * Contributor: Mahavir Jain <mjain@marvell.com>
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef _ASM_ARCH_ARMADA100_H
    10. 

  10. #define _ASM_ARCH_ARMADA100_H
    11. 

  11. 

  12. #if defined (CONFIG_ARMADA100)
    13. 

  13. 

  14. /* Common APB clock register bit definitions */
    15. 

  15. #define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
    16. 

  16. #define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
    17. 

  17. #define APBC_RST        (1<<2)  /* Reset Generation */
    18. 

  18. /* Functional Clock Selection Mask */
    19. 

  19. #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
    20. 

  20. 

  21. /* Fast Ethernet Controller Clock register definition */
    22. 

  22. #define FE_CLK_RST		0x1
    23. 

  23. #define FE_CLK_ENA		0x8
    24. 

  24. 

  25. /* SSP2 Clock Control */
    26. 

  26. #define SSP2_APBCLK		0x01
    27. 

  27. #define SSP2_FNCLK		0x02
    28. 

  28. 

  29. /* USB Clock/reset control bits */
    30. 

  30. #define USB_SPH_AXICLK_EN	0x10
    31. 

  31. #define USB_SPH_AXI_RST		0x02
    32. 

  32. 

  33. /* MPMU Clocks */
    34. 

  34. #define APB2_26M_EN		(1 << 20)
    35. 

  35. #define AP_26M			(1 << 4)
    36. 

  36. 

  37. /* Register Base Addresses */
    38. 

  38. #define ARMD1_DRAM_BASE		0xB0000000
    39. 

  39. #define ARMD1_FEC_BASE		0xC0800000
    40. 

  40. #define ARMD1_TIMER_BASE	0xD4014000
    41. 

  41. #define ARMD1_APBC1_BASE	0xD4015000
    42. 

  42. #define ARMD1_APBC2_BASE	0xD4015800
    43. 

  43. #define ARMD1_UART1_BASE	0xD4017000
    44. 

  44. #define ARMD1_UART2_BASE	0xD4018000
    45. 

  45. #define ARMD1_GPIO_BASE		0xD4019000
    46. 

  46. #define ARMD1_SSP1_BASE		0xD401B000
    47. 

  47. #define ARMD1_SSP2_BASE		0xD401C000
    48. 

  48. #define ARMD1_MFPR_BASE		0xD401E000
    49. 

  49. #define ARMD1_SSP3_BASE		0xD401F000
    50. 

  50. #define ARMD1_SSP4_BASE		0xD4020000
    51. 

  51. #define ARMD1_SSP5_BASE		0xD4021000
    52. 

  52. #define ARMD1_UART3_BASE	0xD4026000
    53. 

  53. #define ARMD1_MPMU_BASE		0xD4050000
    54. 

  54. #define ARMD1_USB_HOST_BASE	0xD4209000
    55. 

  55. #define ARMD1_APMU_BASE		0xD4282800
    56. 

  56. #define ARMD1_CPU_BASE		0xD4282C00
    57. 

  57. 

  58. #endif /* CONFIG_ARMADA100 */
    59. 

  59. #endif /* _ASM_ARCH_ARMADA100_H */
    60.