Accueil Explorer Aide
S'inscrire Connexion
RD_Software
/
linux-arkmicro
2
0
Fork 1
Fichiers Tickets 0 Pull Requests 0 Wiki
Aborescence: dac876f1e5
Branches Tags
linux-arkmicro
/
u-boot
/
arch
/
arm
/
include
/
asm
/
arch-stih410
/
sdhci.h

sdhci.h 2.2 KB
Historique Raw

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768 
  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
    4. 

  4.  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef __STI_SDHCI_H__
    8. 

  8. #define __STI_SDHCI_H__
    9. 

  9. 

  10. #define FLASHSS_MMC_CORE_CONFIG_1			0x400
    11. 

  11. #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ	BIT(24)
    12. 

  12. #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN	BIT(12)
    13. 

  13. 

  14. #define STI_FLASHSS_MMC_CORE_CONFIG_1			\
    15. 

  15. 	(FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ	| \
    16. 

  16. 	 FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
    17. 

  17. 

  18. #define FLASHSS_MMC_CORE_CONFIG_2			0x404
    19. 

  19. #define FLASHSS_MMC_CORECFG_HIGH_SPEED			BIT(28)
    20. 

  20. #define FLASHSS_MMC_CORECFG_8BIT_EMMC			BIT(20)
    21. 

  21. #define MAX_BLK_LENGTH_1024				BIT(16)
    22. 

  22. #define BASE_CLK_FREQ_200				0xc8
    23. 

  23. 

  24. #define STI_FLASHSS_MMC_CORE_CONFIG2	\
    25. 

  25. 	(FLASHSS_MMC_CORECFG_HIGH_SPEED	| \
    26. 

  26. 	 FLASHSS_MMC_CORECFG_8BIT_EMMC	| \
    27. 

  27. 	 MAX_BLK_LENGTH_1024		| \
    28. 

  28. 	 BASE_CLK_FREQ_200 << 0)
    29. 

  29. 

  30. #define STI_FLASHSS_SDCARD_CORE_CONFIG2			\
    31. 

  31. 	(FLASHSS_MMC_CORECFG_HIGH_SPEED			| \
    32. 

  32. 	 MAX_BLK_LENGTH_1024				| \
    33. 

  33. 	 BASE_CLK_FREQ_200)
    34. 

  34. 

  35. #define FLASHSS_MMC_CORE_CONFIG_3			0x408
    36. 

  36. #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC		BIT(28)
    37. 

  37. #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT		BIT(20)
    38. 

  38. #define FLASHSS_MMC_CORECFG_3P3_VOLT			BIT(8)
    39. 

  39. #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT		BIT(4)
    40. 

  40. #define FLASHSS_MMC_CORECFG_SDMA			BIT(0)
    41. 

  41. 

  42. #define STI_FLASHSS_MMC_CORE_CONFIG3			\
    43. 

  43. 	 (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC		| \
    44. 

  44. 	 FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT	| \
    45. 

  45. 	 FLASHSS_MMC_CORECFG_3P3_VOLT			| \
    46. 

  46. 	 FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT		| \
    47. 

  47. 	 FLASHSS_MMC_CORECFG_SDMA)
    48. 

  48. 

  49. #define STI_FLASHSS_SDCARD_CORE_CONFIG3			\
    50. 

  50. 	 (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT	| \
    51. 

  51. 	 FLASHSS_MMC_CORECFG_3P3_VOLT			| \
    52. 

  52. 	 FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT		| \
    53. 

  53. 	 FLASHSS_MMC_CORECFG_SDMA)
    54. 

  54. 

  55. #define FLASHSS_MMC_CORE_CONFIG_4			0x40c
    56. 

  56. #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT		BIT(20)
    57. 

  57. #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT		BIT(16)
    58. 

  58. #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT		BIT(12)
    59. 

  59. 

  60. #define STI_FLASHSS_MMC_CORE_CONFIG4			\
    61. 

  61. 	(FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT		| \
    62. 

  62. 	 FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT		| \
    63. 

  63. 	 FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
    64. 

  64. 

  65. #define ST_MMC_CCONFIG_REG_5		0x210
    66. 

  66. #define SYSCONF_MMC1_ENABLE_BIT		3
    67. 

  67. 

  68. #endif	/* _STI_SDHCI_H_ */
    69.