clk-ld11.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <linux/bitops.h>
  8. #include <linux/io.h>
  9. #include "../init.h"
  10. #include "../sc64-regs.h"
  11. #include "../sg-regs.h"
  12. #define SDCTRL_EMMC_HW_RESET 0x59810280
  13. void uniphier_ld11_clk_init(void)
  14. {
  15. /* if booted from a device other than USB, without stand-by MPU */
  16. if ((readl(SG_PINMON0) & BIT(27)) &&
  17. uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
  18. writel(1, SG_ETPHYPSHUT);
  19. writel(1, SG_ETPHYCNT);
  20. udelay(1); /* wait for regulator level 1.1V -> 2.5V */
  21. writel(3, SG_ETPHYCNT);
  22. writel(3, SG_ETPHYPSHUT);
  23. writel(7, SG_ETPHYCNT);
  24. }
  25. /* TODO: use "mmc-pwrseq-emmc" */
  26. writel(1, SDCTRL_EMMC_HW_RESET);
  27. #ifdef CONFIG_USB_EHCI_HCD
  28. {
  29. /* FIXME: the current clk driver can not handle parents */
  30. u32 tmp;
  31. int ch;
  32. tmp = readl(SC_CLKCTRL4);
  33. tmp |= BIT(10) | BIT(8); /* MIO, STDMAC */
  34. writel(tmp, SC_CLKCTRL4);
  35. for (ch = 0; ch < 3; ch++) {
  36. void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
  37. writel(0x82280600, phyctrl + 8 * ch);
  38. writel(0x00000106, phyctrl + 8 * ch + 4);
  39. }
  40. }
  41. #endif
  42. }