ark_wdt.c 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370
  1. /*
  2. * Arkmicro watchdog driver
  3. *
  4. * Licensed under GPLv2 or later.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/clk.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reboot.h>
  16. #include <linux/watchdog.h>
  17. #include <linux/gpio/consumer.h>
  18. #define ARK_WTCON 0x00
  19. #define ARK_WTPSR 0x04
  20. #define ARK_WTCNT 0x08
  21. #define ARK_WTCLRINT 0x10
  22. #define ARK_WTRCR 0x14
  23. #define ARK_WTCNT_MAXCNT 0xffff
  24. #define ARK_WTCON_MAXDIV 0x80
  25. #define ARK_WTCON_ENABLE (1 << 0)
  26. #define ARK_WTCON_RSTEN (1 << 1)
  27. #define ARK_WTCON_INTEN (1 << 2)
  28. #define ARK_WTCON_DIV16 (0 << 4)
  29. #define ARK_WTCON_DIV32 (1 << 4)
  30. #define ARK_WTCON_DIV64 (2 << 4)
  31. #define ARK_WTCON_DIV128 (3 << 4)
  32. #define ARK_WTCON_DIVMASK (0x3 << 4)
  33. #define ARK_WTCON_PRESCALE_MAX 0xffff
  34. #define ARK_WATCHDOG_DEFAULT_TIME (15)
  35. struct ark_wdt {
  36. struct device *dev;
  37. void __iomem *reg_base;
  38. struct gpio_desc *reset_gpio;
  39. struct clk *clock;
  40. struct watchdog_device wdd;
  41. unsigned int count;
  42. spinlock_t lock;
  43. };
  44. static int wdt_timeout = ARK_WATCHDOG_DEFAULT_TIME;
  45. static bool nowayout = WATCHDOG_NOWAYOUT;
  46. static int soft_noboot = 1;
  47. module_param(wdt_timeout, int, 0);
  48. MODULE_PARM_DESC(wdt_timeout,
  49. "Watchdog timeout in seconds. (default = "
  50. __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
  51. module_param(nowayout, bool, 0);
  52. MODULE_PARM_DESC(nowayout,
  53. "Watchdog cannot be stopped once started (default="
  54. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  55. module_param(soft_noboot, int, 0);
  56. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
  57. static int ark_wdt_keepalive(struct watchdog_device *wdd)
  58. {
  59. struct ark_wdt *wdt = watchdog_get_drvdata(wdd);
  60. spin_lock(&wdt->lock);
  61. writel(wdt->count, wdt->reg_base + ARK_WTCNT);
  62. spin_unlock(&wdt->lock);
  63. return 0;
  64. }
  65. static void __ark_wdt_stop(struct ark_wdt *wdt)
  66. {
  67. unsigned long wtcon;
  68. wtcon = readl(wdt->reg_base + ARK_WTCON);
  69. wtcon &= ~(ARK_WTCON_ENABLE | ARK_WTCON_RSTEN);
  70. writel(wtcon, wdt->reg_base + ARK_WTCON);
  71. }
  72. static int ark_wdt_stop(struct watchdog_device *wdd)
  73. {
  74. struct ark_wdt *wdt = watchdog_get_drvdata(wdd);
  75. spin_lock(&wdt->lock);
  76. __ark_wdt_stop(wdt);
  77. spin_unlock(&wdt->lock);
  78. return 0;
  79. }
  80. static int ark_wdt_start(struct watchdog_device *wdd)
  81. {
  82. unsigned long wtcon;
  83. struct ark_wdt *wdt = watchdog_get_drvdata(wdd);
  84. spin_lock(&wdt->lock);
  85. __ark_wdt_stop(wdt);
  86. wtcon = readl(wdt->reg_base + ARK_WTCON);
  87. wtcon &= ~ARK_WTCON_DIVMASK;
  88. wtcon |= ARK_WTCON_ENABLE | ARK_WTCON_DIV128;
  89. if (soft_noboot) {
  90. wtcon |= ARK_WTCON_INTEN;
  91. wtcon &= ~ARK_WTCON_RSTEN;
  92. } else {
  93. wtcon &= ~ARK_WTCON_INTEN;
  94. wtcon |= ARK_WTCON_RSTEN;
  95. }
  96. dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
  97. wdt->count, wtcon);
  98. writel(wdt->count, wdt->reg_base + ARK_WTCNT);
  99. writel(wtcon, wdt->reg_base + ARK_WTCON);
  100. spin_unlock(&wdt->lock);
  101. return 0;
  102. }
  103. static unsigned int ark_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout_ms)
  104. {
  105. struct ark_wdt *wdt = watchdog_get_drvdata(wdd);
  106. unsigned long freq = clk_get_rate(wdt->clock);
  107. unsigned int count;
  108. unsigned int divisor = 1;
  109. freq = DIV_ROUND_UP(freq, 128);
  110. count = timeout_ms * DIV_ROUND_UP(freq, 1000);
  111. dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d(ms), freq=%lu\n",
  112. count, timeout_ms, freq);
  113. /* if the count is bigger than the watchdog register,
  114. then work out what we need to do (and if) we can
  115. actually make this value
  116. */
  117. if (count > ARK_WTCNT_MAXCNT) {
  118. divisor = DIV_ROUND_UP(count, ARK_WTCNT_MAXCNT);
  119. if (divisor > ARK_WTCON_PRESCALE_MAX) {
  120. dev_err(wdt->dev, "timeout %d(ms) too big\n", timeout_ms);
  121. return -EINVAL;
  122. }
  123. }
  124. dev_dbg(wdt->dev, "Heartbeat: timeout=%d(ms), divisor=%d, count=%d (%08x)\n",
  125. timeout_ms, divisor, count, DIV_ROUND_UP(count, divisor));
  126. count = DIV_ROUND_UP(count, divisor);
  127. wdt->count = count;
  128. /* update the pre-scaler */
  129. writel(divisor, wdt->reg_base + ARK_WTPSR);
  130. writel(count, wdt->reg_base + ARK_WTCNT);
  131. return (count * divisor) / freq;
  132. }
  133. static int ark_wdt_set_heartbeat(struct watchdog_device *wdd,
  134. unsigned int timeout)
  135. {
  136. if (timeout < 1)
  137. return -EINVAL;
  138. wdd->timeout = ark_wdt_set_timeout(wdd, timeout * 1000);
  139. return 0;
  140. }
  141. static int ark_wdt_restart(struct watchdog_device *wdd, unsigned long action,
  142. void *data)
  143. {
  144. struct ark_wdt *wdt = watchdog_get_drvdata(wdd);
  145. void __iomem *wdt_base = wdt->reg_base;
  146. #ifdef CONFIG_SOC_ARK1668E
  147. void __iomem *sys_base;
  148. #endif
  149. /* disable watchdog, to be safe */
  150. writel(0, wdt_base + ARK_WTCON);
  151. #ifdef CONFIG_SOC_ARK1668E
  152. if (wdt->reset_gpio)
  153. gpiod_direction_output(wdt->reset_gpio, 1);
  154. else
  155. ark_wdt_set_timeout(wdd, 2000);
  156. #else
  157. ark_wdt_set_timeout(wdd, 100);
  158. #endif
  159. /* set the watchdog to go and reset... */
  160. writel(ARK_WTCON_ENABLE | ARK_WTCON_DIV128 |
  161. ARK_WTCON_RSTEN, wdt_base + ARK_WTCON);
  162. #ifdef CONFIG_SOC_ARK1668E
  163. #define ARK1668E_SYSREG_BASE 0xe4900000
  164. #define ARK1668E_SOFT_RSTA 0x74
  165. #define ARK1668E_SOFT_RSTB 0x78
  166. sys_base = ioremap(ARK1668E_SYSREG_BASE, 0x1000);
  167. if (sys_base) {
  168. writel(0, sys_base + ARK1668E_SOFT_RSTA);
  169. writel(0, sys_base + ARK1668E_SOFT_RSTB);
  170. }
  171. #endif
  172. /* wait for reset to assert... */
  173. mdelay(3000);
  174. return 0;
  175. }
  176. static const struct watchdog_info ark_wdt_info = {
  177. .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
  178. .identity = "ark Watchdog",
  179. };
  180. static const struct watchdog_ops ark_wdt_ops = {
  181. .owner = THIS_MODULE,
  182. .start = ark_wdt_start,
  183. .stop = ark_wdt_stop,
  184. .ping = ark_wdt_keepalive,
  185. .restart = ark_wdt_restart,
  186. .set_timeout = ark_wdt_set_heartbeat,
  187. };
  188. /* interrupt handler code */
  189. static irqreturn_t ark_wdt_irq(int irqno, void *param)
  190. {
  191. struct ark_wdt *wdt = platform_get_drvdata(param);
  192. //dev_info(wdt->dev, "watchdog timer expired (irq)\n");
  193. ark_wdt_keepalive(&wdt->wdd);
  194. writel(0x1, wdt->reg_base + ARK_WTCLRINT);
  195. return IRQ_HANDLED;
  196. }
  197. static inline unsigned int ark_wdt_max_timeout(struct clk *clock)
  198. {
  199. unsigned long freq = clk_get_rate(clock);
  200. return ARK_WTCNT_MAXCNT / (freq / ARK_WTCON_PRESCALE_MAX
  201. / ARK_WTCON_MAXDIV);
  202. }
  203. static int ark_wdt_probe(struct platform_device *pdev)
  204. {
  205. struct device *dev = &pdev->dev;
  206. struct watchdog_device *wdd;
  207. struct ark_wdt *wdt;
  208. struct resource *res;
  209. void __iomem *regs;
  210. int ret;
  211. int irq;
  212. wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
  213. if (!wdt)
  214. return -ENOMEM;
  215. wdt->dev = dev;
  216. spin_lock_init(&wdt->lock);
  217. wdd = &wdt->wdd;
  218. wdd->timeout = wdt_timeout;
  219. wdd->info = &ark_wdt_info;
  220. wdd->ops = &ark_wdt_ops;
  221. watchdog_set_drvdata(wdd, wdt);
  222. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  223. regs = devm_ioremap_resource(&pdev->dev, res);
  224. if (IS_ERR(regs))
  225. return PTR_ERR(regs);
  226. wdt->reg_base = regs;
  227. wdt->clock = devm_clk_get(dev, NULL);
  228. if (IS_ERR(wdt->clock)) {
  229. dev_err(dev, "failed to find watchdog clock source\n");
  230. return PTR_ERR(wdt->clock);
  231. }
  232. wdt->reset_gpio = devm_gpiod_get(&pdev->dev, "reset", GPIOD_OUT_LOW);
  233. if (IS_ERR(wdt->reset_gpio))
  234. wdt->reset_gpio = NULL;
  235. wdt->wdd.min_timeout = 1;
  236. wdt->wdd.max_timeout = ark_wdt_max_timeout(wdt->clock);
  237. ret = watchdog_init_timeout(wdd, wdt_timeout, &pdev->dev);
  238. if (ret) {
  239. dev_err(&pdev->dev, "unable to set timeout value\n");
  240. return ret;
  241. }
  242. ret = ark_wdt_set_heartbeat(&wdt->wdd, wdt_timeout);
  243. if (ret) {
  244. dev_err(&pdev->dev, "failed to set timeout value\n");
  245. }
  246. irq = platform_get_irq(pdev, 0);
  247. if (irq < 0) {
  248. dev_err(&pdev->dev, "unable to get irq\n");
  249. return irq;
  250. }
  251. ret = devm_request_irq(dev, irq, ark_wdt_irq, 0, pdev->name, pdev);
  252. if (ret != 0) {
  253. dev_err(dev, "failed to install irq (%d)\n", ret);
  254. return ret;
  255. }
  256. watchdog_set_nowayout(wdd, nowayout);
  257. watchdog_set_restart_priority(&wdt->wdd, 128);
  258. ret = watchdog_register_device(wdd);
  259. if (ret) {
  260. dev_err(&pdev->dev, "failed to register watchdog device\n");
  261. return ret;
  262. }
  263. platform_set_drvdata(pdev, wdt);
  264. ark_wdt_start(&wdt->wdd);
  265. dev_info(&pdev->dev, "initialized (timeout = %d sec, nowayout = %d)\n",
  266. wdt_timeout, nowayout);
  267. return 0;
  268. }
  269. static int ark_wdt_remove(struct platform_device *pdev)
  270. {
  271. struct ark_wdt *wdt = platform_get_drvdata(pdev);
  272. ark_wdt_stop(&wdt->wdd);
  273. watchdog_unregister_device(&wdt->wdd);
  274. return 0;
  275. }
  276. static const struct of_device_id ark_wdt_of_match[] = {
  277. { .compatible = "arkmicro,ark-wdt", },
  278. { }
  279. };
  280. MODULE_DEVICE_TABLE(of, ark_wdt_of_match);
  281. static struct platform_driver ark_wdt_driver = {
  282. .probe = ark_wdt_probe,
  283. .remove = ark_wdt_remove,
  284. .driver = {
  285. .name = "ark_wdt",
  286. .of_match_table = ark_wdt_of_match,
  287. }
  288. };
  289. module_platform_driver(ark_wdt_driver);
  290. MODULE_AUTHOR("Sim");
  291. MODULE_DESCRIPTION("Arkmicro Watchdog Timer driver");
  292. MODULE_LICENSE("GPL v2");