prodigy_hifi.c 32 KB

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  1. /*
  2. * ALSA driver for ICEnsemble VT1724 (Envy24HT)
  3. *
  4. * Lowlevel functions for Audiotrak Prodigy 7.1 Hifi
  5. * based on pontis.c
  6. *
  7. * Copyright (c) 2007 Julian Scheel <julian@jusst.de>
  8. * Copyright (c) 2007 allank
  9. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/init.h>
  29. #include <linux/slab.h>
  30. #include <linux/mutex.h>
  31. #include <sound/core.h>
  32. #include <sound/info.h>
  33. #include <sound/tlv.h>
  34. #include "ice1712.h"
  35. #include "envy24ht.h"
  36. #include "prodigy_hifi.h"
  37. struct prodigy_hifi_spec {
  38. unsigned short master[2];
  39. unsigned short vol[8];
  40. };
  41. /* I2C addresses */
  42. #define WM_DEV 0x34
  43. /* WM8776 registers */
  44. #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
  45. #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
  46. #define WM_HP_MASTER 0x02 /* headphone master (both channels),
  47. override LLR */
  48. #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
  49. #define WM_DAC_ATTEN_R 0x04
  50. #define WM_DAC_MASTER 0x05
  51. #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
  52. #define WM_DAC_CTRL1 0x07
  53. #define WM_DAC_MUTE 0x08
  54. #define WM_DAC_CTRL2 0x09
  55. #define WM_DAC_INT 0x0a
  56. #define WM_ADC_INT 0x0b
  57. #define WM_MASTER_CTRL 0x0c
  58. #define WM_POWERDOWN 0x0d
  59. #define WM_ADC_ATTEN_L 0x0e
  60. #define WM_ADC_ATTEN_R 0x0f
  61. #define WM_ALC_CTRL1 0x10
  62. #define WM_ALC_CTRL2 0x11
  63. #define WM_ALC_CTRL3 0x12
  64. #define WM_NOISE_GATE 0x13
  65. #define WM_LIMITER 0x14
  66. #define WM_ADC_MUX 0x15
  67. #define WM_OUT_MUX 0x16
  68. #define WM_RESET 0x17
  69. /* Analog Recording Source :- Mic, LineIn, CD/Video, */
  70. /* implement capture source select control for WM8776 */
  71. #define WM_AIN1 "AIN1"
  72. #define WM_AIN2 "AIN2"
  73. #define WM_AIN3 "AIN3"
  74. #define WM_AIN4 "AIN4"
  75. #define WM_AIN5 "AIN5"
  76. /* GPIO pins of envy24ht connected to wm8766 */
  77. #define WM8766_SPI_CLK (1<<17) /* CLK, Pin97 on ICE1724 */
  78. #define WM8766_SPI_MD (1<<16) /* DATA VT1724 -> WM8766, Pin96 */
  79. #define WM8766_SPI_ML (1<<18) /* Latch, Pin98 */
  80. /* WM8766 registers */
  81. #define WM8766_DAC_CTRL 0x02 /* DAC Control */
  82. #define WM8766_INT_CTRL 0x03 /* Interface Control */
  83. #define WM8766_DAC_CTRL2 0x09
  84. #define WM8766_DAC_CTRL3 0x0a
  85. #define WM8766_RESET 0x1f
  86. #define WM8766_LDA1 0x00
  87. #define WM8766_LDA2 0x04
  88. #define WM8766_LDA3 0x06
  89. #define WM8766_RDA1 0x01
  90. #define WM8766_RDA2 0x05
  91. #define WM8766_RDA3 0x07
  92. #define WM8766_MUTE1 0x0C
  93. #define WM8766_MUTE2 0x0F
  94. /*
  95. * Prodigy HD2
  96. */
  97. #define AK4396_ADDR 0x00
  98. #define AK4396_CSN (1 << 8) /* CSN->GPIO8, pin 75 */
  99. #define AK4396_CCLK (1 << 9) /* CCLK->GPIO9, pin 76 */
  100. #define AK4396_CDTI (1 << 10) /* CDTI->GPIO10, pin 77 */
  101. /* ak4396 registers */
  102. #define AK4396_CTRL1 0x00
  103. #define AK4396_CTRL2 0x01
  104. #define AK4396_CTRL3 0x02
  105. #define AK4396_LCH_ATT 0x03
  106. #define AK4396_RCH_ATT 0x04
  107. /*
  108. * get the current register value of WM codec
  109. */
  110. static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
  111. {
  112. reg <<= 1;
  113. return ((unsigned short)ice->akm[0].images[reg] << 8) |
  114. ice->akm[0].images[reg + 1];
  115. }
  116. /*
  117. * set the register value of WM codec and remember it
  118. */
  119. static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
  120. {
  121. unsigned short cval;
  122. cval = (reg << 9) | val;
  123. snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
  124. }
  125. static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
  126. {
  127. wm_put_nocache(ice, reg, val);
  128. reg <<= 1;
  129. ice->akm[0].images[reg] = val >> 8;
  130. ice->akm[0].images[reg + 1] = val;
  131. }
  132. /*
  133. * write data in the SPI mode
  134. */
  135. static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
  136. {
  137. unsigned int tmp = snd_ice1712_gpio_read(ice);
  138. if (val)
  139. tmp |= bit;
  140. else
  141. tmp &= ~bit;
  142. snd_ice1712_gpio_write(ice, tmp);
  143. }
  144. /*
  145. * SPI implementation for WM8766 codec - only writing supported, no readback
  146. */
  147. static void wm8766_spi_send_word(struct snd_ice1712 *ice, unsigned int data)
  148. {
  149. int i;
  150. for (i = 0; i < 16; i++) {
  151. set_gpio_bit(ice, WM8766_SPI_CLK, 0);
  152. udelay(1);
  153. set_gpio_bit(ice, WM8766_SPI_MD, data & 0x8000);
  154. udelay(1);
  155. set_gpio_bit(ice, WM8766_SPI_CLK, 1);
  156. udelay(1);
  157. data <<= 1;
  158. }
  159. }
  160. static void wm8766_spi_write(struct snd_ice1712 *ice, unsigned int reg,
  161. unsigned int data)
  162. {
  163. unsigned int block;
  164. snd_ice1712_gpio_set_dir(ice, WM8766_SPI_MD|
  165. WM8766_SPI_CLK|WM8766_SPI_ML);
  166. snd_ice1712_gpio_set_mask(ice, ~(WM8766_SPI_MD|
  167. WM8766_SPI_CLK|WM8766_SPI_ML));
  168. /* latch must be low when writing */
  169. set_gpio_bit(ice, WM8766_SPI_ML, 0);
  170. block = (reg << 9) | (data & 0x1ff);
  171. wm8766_spi_send_word(ice, block); /* REGISTER ADDRESS */
  172. /* release latch */
  173. set_gpio_bit(ice, WM8766_SPI_ML, 1);
  174. udelay(1);
  175. /* restore */
  176. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  177. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  178. }
  179. /*
  180. * serial interface for ak4396 - only writing supported, no readback
  181. */
  182. static void ak4396_send_word(struct snd_ice1712 *ice, unsigned int data)
  183. {
  184. int i;
  185. for (i = 0; i < 16; i++) {
  186. set_gpio_bit(ice, AK4396_CCLK, 0);
  187. udelay(1);
  188. set_gpio_bit(ice, AK4396_CDTI, data & 0x8000);
  189. udelay(1);
  190. set_gpio_bit(ice, AK4396_CCLK, 1);
  191. udelay(1);
  192. data <<= 1;
  193. }
  194. }
  195. static void ak4396_write(struct snd_ice1712 *ice, unsigned int reg,
  196. unsigned int data)
  197. {
  198. unsigned int block;
  199. snd_ice1712_gpio_set_dir(ice, AK4396_CSN|AK4396_CCLK|AK4396_CDTI);
  200. snd_ice1712_gpio_set_mask(ice, ~(AK4396_CSN|AK4396_CCLK|AK4396_CDTI));
  201. /* latch must be low when writing */
  202. set_gpio_bit(ice, AK4396_CSN, 0);
  203. block = ((AK4396_ADDR & 0x03) << 14) | (1 << 13) |
  204. ((reg & 0x1f) << 8) | (data & 0xff);
  205. ak4396_send_word(ice, block); /* REGISTER ADDRESS */
  206. /* release latch */
  207. set_gpio_bit(ice, AK4396_CSN, 1);
  208. udelay(1);
  209. /* restore */
  210. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  211. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  212. }
  213. /*
  214. * ak4396 mixers
  215. */
  216. /*
  217. * DAC volume attenuation mixer control (-64dB to 0dB)
  218. */
  219. static int ak4396_dac_vol_info(struct snd_kcontrol *kcontrol,
  220. struct snd_ctl_elem_info *uinfo)
  221. {
  222. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  223. uinfo->count = 2;
  224. uinfo->value.integer.min = 0; /* mute */
  225. uinfo->value.integer.max = 0xFF; /* linear */
  226. return 0;
  227. }
  228. static int ak4396_dac_vol_get(struct snd_kcontrol *kcontrol,
  229. struct snd_ctl_elem_value *ucontrol)
  230. {
  231. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  232. struct prodigy_hifi_spec *spec = ice->spec;
  233. int i;
  234. for (i = 0; i < 2; i++)
  235. ucontrol->value.integer.value[i] = spec->vol[i];
  236. return 0;
  237. }
  238. static int ak4396_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  239. {
  240. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  241. struct prodigy_hifi_spec *spec = ice->spec;
  242. int i;
  243. int change = 0;
  244. mutex_lock(&ice->gpio_mutex);
  245. for (i = 0; i < 2; i++) {
  246. if (ucontrol->value.integer.value[i] != spec->vol[i]) {
  247. spec->vol[i] = ucontrol->value.integer.value[i];
  248. ak4396_write(ice, AK4396_LCH_ATT + i,
  249. spec->vol[i] & 0xff);
  250. change = 1;
  251. }
  252. }
  253. mutex_unlock(&ice->gpio_mutex);
  254. return change;
  255. }
  256. static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
  257. static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
  258. static struct snd_kcontrol_new prodigy_hd2_controls[] = {
  259. {
  260. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  261. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  262. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  263. .name = "Front Playback Volume",
  264. .info = ak4396_dac_vol_info,
  265. .get = ak4396_dac_vol_get,
  266. .put = ak4396_dac_vol_put,
  267. .tlv = { .p = ak4396_db_scale },
  268. },
  269. };
  270. /* --------------- */
  271. #define WM_VOL_MAX 255
  272. #define WM_VOL_MUTE 0x8000
  273. #define DAC_0dB 0xff
  274. #define DAC_RES 128
  275. #define DAC_MIN (DAC_0dB - DAC_RES)
  276. static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index,
  277. unsigned short vol, unsigned short master)
  278. {
  279. unsigned char nvol;
  280. if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
  281. nvol = 0;
  282. else {
  283. nvol = (((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 128)
  284. & WM_VOL_MAX;
  285. nvol = (nvol ? (nvol + DAC_MIN) : 0) & 0xff;
  286. }
  287. wm_put(ice, index, nvol);
  288. wm_put_nocache(ice, index, 0x100 | nvol);
  289. }
  290. static void wm8766_set_vol(struct snd_ice1712 *ice, unsigned int index,
  291. unsigned short vol, unsigned short master)
  292. {
  293. unsigned char nvol;
  294. if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
  295. nvol = 0;
  296. else {
  297. nvol = (((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 128)
  298. & WM_VOL_MAX;
  299. nvol = (nvol ? (nvol + DAC_MIN) : 0) & 0xff;
  300. }
  301. wm8766_spi_write(ice, index, (0x0100 | nvol));
  302. }
  303. /*
  304. * DAC volume attenuation mixer control (-64dB to 0dB)
  305. */
  306. static int wm_dac_vol_info(struct snd_kcontrol *kcontrol,
  307. struct snd_ctl_elem_info *uinfo)
  308. {
  309. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  310. uinfo->count = 2;
  311. uinfo->value.integer.min = 0; /* mute */
  312. uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
  313. return 0;
  314. }
  315. static int wm_dac_vol_get(struct snd_kcontrol *kcontrol,
  316. struct snd_ctl_elem_value *ucontrol)
  317. {
  318. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  319. struct prodigy_hifi_spec *spec = ice->spec;
  320. int i;
  321. for (i = 0; i < 2; i++)
  322. ucontrol->value.integer.value[i] =
  323. spec->vol[2 + i] & ~WM_VOL_MUTE;
  324. return 0;
  325. }
  326. static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  327. {
  328. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  329. struct prodigy_hifi_spec *spec = ice->spec;
  330. int i, idx, change = 0;
  331. mutex_lock(&ice->gpio_mutex);
  332. for (i = 0; i < 2; i++) {
  333. if (ucontrol->value.integer.value[i] != spec->vol[2 + i]) {
  334. idx = WM_DAC_ATTEN_L + i;
  335. spec->vol[2 + i] &= WM_VOL_MUTE;
  336. spec->vol[2 + i] |= ucontrol->value.integer.value[i];
  337. wm_set_vol(ice, idx, spec->vol[2 + i], spec->master[i]);
  338. change = 1;
  339. }
  340. }
  341. mutex_unlock(&ice->gpio_mutex);
  342. return change;
  343. }
  344. /*
  345. * WM8766 DAC volume attenuation mixer control
  346. */
  347. static int wm8766_vol_info(struct snd_kcontrol *kcontrol,
  348. struct snd_ctl_elem_info *uinfo)
  349. {
  350. int voices = kcontrol->private_value >> 8;
  351. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  352. uinfo->count = voices;
  353. uinfo->value.integer.min = 0; /* mute */
  354. uinfo->value.integer.max = DAC_RES; /* 0dB */
  355. return 0;
  356. }
  357. static int wm8766_vol_get(struct snd_kcontrol *kcontrol,
  358. struct snd_ctl_elem_value *ucontrol)
  359. {
  360. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  361. struct prodigy_hifi_spec *spec = ice->spec;
  362. int i, ofs, voices;
  363. voices = kcontrol->private_value >> 8;
  364. ofs = kcontrol->private_value & 0xff;
  365. for (i = 0; i < voices; i++)
  366. ucontrol->value.integer.value[i] = spec->vol[ofs + i];
  367. return 0;
  368. }
  369. static int wm8766_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  370. {
  371. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  372. struct prodigy_hifi_spec *spec = ice->spec;
  373. int i, idx, ofs, voices;
  374. int change = 0;
  375. voices = kcontrol->private_value >> 8;
  376. ofs = kcontrol->private_value & 0xff;
  377. mutex_lock(&ice->gpio_mutex);
  378. for (i = 0; i < voices; i++) {
  379. if (ucontrol->value.integer.value[i] != spec->vol[ofs + i]) {
  380. idx = WM8766_LDA1 + ofs + i;
  381. spec->vol[ofs + i] &= WM_VOL_MUTE;
  382. spec->vol[ofs + i] |= ucontrol->value.integer.value[i];
  383. wm8766_set_vol(ice, idx,
  384. spec->vol[ofs + i], spec->master[i]);
  385. change = 1;
  386. }
  387. }
  388. mutex_unlock(&ice->gpio_mutex);
  389. return change;
  390. }
  391. /*
  392. * Master volume attenuation mixer control / applied to WM8776+WM8766
  393. */
  394. static int wm_master_vol_info(struct snd_kcontrol *kcontrol,
  395. struct snd_ctl_elem_info *uinfo)
  396. {
  397. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  398. uinfo->count = 2;
  399. uinfo->value.integer.min = 0;
  400. uinfo->value.integer.max = DAC_RES;
  401. return 0;
  402. }
  403. static int wm_master_vol_get(struct snd_kcontrol *kcontrol,
  404. struct snd_ctl_elem_value *ucontrol)
  405. {
  406. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  407. struct prodigy_hifi_spec *spec = ice->spec;
  408. int i;
  409. for (i = 0; i < 2; i++)
  410. ucontrol->value.integer.value[i] = spec->master[i];
  411. return 0;
  412. }
  413. static int wm_master_vol_put(struct snd_kcontrol *kcontrol,
  414. struct snd_ctl_elem_value *ucontrol)
  415. {
  416. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  417. struct prodigy_hifi_spec *spec = ice->spec;
  418. int ch, change = 0;
  419. mutex_lock(&ice->gpio_mutex);
  420. for (ch = 0; ch < 2; ch++) {
  421. if (ucontrol->value.integer.value[ch] != spec->master[ch]) {
  422. spec->master[ch] = ucontrol->value.integer.value[ch];
  423. /* Apply to front DAC */
  424. wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
  425. spec->vol[2 + ch], spec->master[ch]);
  426. wm8766_set_vol(ice, WM8766_LDA1 + ch,
  427. spec->vol[0 + ch], spec->master[ch]);
  428. wm8766_set_vol(ice, WM8766_LDA2 + ch,
  429. spec->vol[4 + ch], spec->master[ch]);
  430. wm8766_set_vol(ice, WM8766_LDA3 + ch,
  431. spec->vol[6 + ch], spec->master[ch]);
  432. change = 1;
  433. }
  434. }
  435. mutex_unlock(&ice->gpio_mutex);
  436. return change;
  437. }
  438. /* KONSTI */
  439. static int wm_adc_mux_enum_info(struct snd_kcontrol *kcontrol,
  440. struct snd_ctl_elem_info *uinfo)
  441. {
  442. static const char * const texts[32] = {
  443. "NULL", WM_AIN1, WM_AIN2, WM_AIN1 "+" WM_AIN2,
  444. WM_AIN3, WM_AIN1 "+" WM_AIN3, WM_AIN2 "+" WM_AIN3,
  445. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3,
  446. WM_AIN4, WM_AIN1 "+" WM_AIN4, WM_AIN2 "+" WM_AIN4,
  447. WM_AIN1 "+" WM_AIN2 "+" WM_AIN4,
  448. WM_AIN3 "+" WM_AIN4, WM_AIN1 "+" WM_AIN3 "+" WM_AIN4,
  449. WM_AIN2 "+" WM_AIN3 "+" WM_AIN4,
  450. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN4,
  451. WM_AIN5, WM_AIN1 "+" WM_AIN5, WM_AIN2 "+" WM_AIN5,
  452. WM_AIN1 "+" WM_AIN2 "+" WM_AIN5,
  453. WM_AIN3 "+" WM_AIN5, WM_AIN1 "+" WM_AIN3 "+" WM_AIN5,
  454. WM_AIN2 "+" WM_AIN3 "+" WM_AIN5,
  455. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN5,
  456. WM_AIN4 "+" WM_AIN5, WM_AIN1 "+" WM_AIN4 "+" WM_AIN5,
  457. WM_AIN2 "+" WM_AIN4 "+" WM_AIN5,
  458. WM_AIN1 "+" WM_AIN2 "+" WM_AIN4 "+" WM_AIN5,
  459. WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
  460. WM_AIN1 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
  461. WM_AIN2 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
  462. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5
  463. };
  464. return snd_ctl_enum_info(uinfo, 1, 32, texts);
  465. }
  466. static int wm_adc_mux_enum_get(struct snd_kcontrol *kcontrol,
  467. struct snd_ctl_elem_value *ucontrol)
  468. {
  469. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  470. mutex_lock(&ice->gpio_mutex);
  471. ucontrol->value.enumerated.item[0] = wm_get(ice, WM_ADC_MUX) & 0x1f;
  472. mutex_unlock(&ice->gpio_mutex);
  473. return 0;
  474. }
  475. static int wm_adc_mux_enum_put(struct snd_kcontrol *kcontrol,
  476. struct snd_ctl_elem_value *ucontrol)
  477. {
  478. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  479. unsigned short oval, nval;
  480. int change = 0;
  481. mutex_lock(&ice->gpio_mutex);
  482. oval = wm_get(ice, WM_ADC_MUX);
  483. nval = (oval & 0xe0) | ucontrol->value.enumerated.item[0];
  484. if (nval != oval) {
  485. wm_put(ice, WM_ADC_MUX, nval);
  486. change = 1;
  487. }
  488. mutex_unlock(&ice->gpio_mutex);
  489. return change;
  490. }
  491. /* KONSTI */
  492. /*
  493. * ADC gain mixer control (-64dB to 0dB)
  494. */
  495. #define ADC_0dB 0xcf
  496. #define ADC_RES 128
  497. #define ADC_MIN (ADC_0dB - ADC_RES)
  498. static int wm_adc_vol_info(struct snd_kcontrol *kcontrol,
  499. struct snd_ctl_elem_info *uinfo)
  500. {
  501. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  502. uinfo->count = 2;
  503. uinfo->value.integer.min = 0; /* mute (-64dB) */
  504. uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
  505. return 0;
  506. }
  507. static int wm_adc_vol_get(struct snd_kcontrol *kcontrol,
  508. struct snd_ctl_elem_value *ucontrol)
  509. {
  510. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  511. unsigned short val;
  512. int i;
  513. mutex_lock(&ice->gpio_mutex);
  514. for (i = 0; i < 2; i++) {
  515. val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
  516. val = val > ADC_MIN ? (val - ADC_MIN) : 0;
  517. ucontrol->value.integer.value[i] = val;
  518. }
  519. mutex_unlock(&ice->gpio_mutex);
  520. return 0;
  521. }
  522. static int wm_adc_vol_put(struct snd_kcontrol *kcontrol,
  523. struct snd_ctl_elem_value *ucontrol)
  524. {
  525. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  526. unsigned short ovol, nvol;
  527. int i, idx, change = 0;
  528. mutex_lock(&ice->gpio_mutex);
  529. for (i = 0; i < 2; i++) {
  530. nvol = ucontrol->value.integer.value[i];
  531. nvol = nvol ? (nvol + ADC_MIN) : 0;
  532. idx = WM_ADC_ATTEN_L + i;
  533. ovol = wm_get(ice, idx) & 0xff;
  534. if (ovol != nvol) {
  535. wm_put(ice, idx, nvol);
  536. change = 1;
  537. }
  538. }
  539. mutex_unlock(&ice->gpio_mutex);
  540. return change;
  541. }
  542. /*
  543. * ADC input mux mixer control
  544. */
  545. #define wm_adc_mux_info snd_ctl_boolean_mono_info
  546. static int wm_adc_mux_get(struct snd_kcontrol *kcontrol,
  547. struct snd_ctl_elem_value *ucontrol)
  548. {
  549. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  550. int bit = kcontrol->private_value;
  551. mutex_lock(&ice->gpio_mutex);
  552. ucontrol->value.integer.value[0] =
  553. (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
  554. mutex_unlock(&ice->gpio_mutex);
  555. return 0;
  556. }
  557. static int wm_adc_mux_put(struct snd_kcontrol *kcontrol,
  558. struct snd_ctl_elem_value *ucontrol)
  559. {
  560. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  561. int bit = kcontrol->private_value;
  562. unsigned short oval, nval;
  563. int change;
  564. mutex_lock(&ice->gpio_mutex);
  565. nval = oval = wm_get(ice, WM_ADC_MUX);
  566. if (ucontrol->value.integer.value[0])
  567. nval |= (1 << bit);
  568. else
  569. nval &= ~(1 << bit);
  570. change = nval != oval;
  571. if (change) {
  572. wm_put(ice, WM_ADC_MUX, nval);
  573. }
  574. mutex_unlock(&ice->gpio_mutex);
  575. return 0;
  576. }
  577. /*
  578. * Analog bypass (In -> Out)
  579. */
  580. #define wm_bypass_info snd_ctl_boolean_mono_info
  581. static int wm_bypass_get(struct snd_kcontrol *kcontrol,
  582. struct snd_ctl_elem_value *ucontrol)
  583. {
  584. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  585. mutex_lock(&ice->gpio_mutex);
  586. ucontrol->value.integer.value[0] =
  587. (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
  588. mutex_unlock(&ice->gpio_mutex);
  589. return 0;
  590. }
  591. static int wm_bypass_put(struct snd_kcontrol *kcontrol,
  592. struct snd_ctl_elem_value *ucontrol)
  593. {
  594. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  595. unsigned short val, oval;
  596. int change = 0;
  597. mutex_lock(&ice->gpio_mutex);
  598. val = oval = wm_get(ice, WM_OUT_MUX);
  599. if (ucontrol->value.integer.value[0])
  600. val |= 0x04;
  601. else
  602. val &= ~0x04;
  603. if (val != oval) {
  604. wm_put(ice, WM_OUT_MUX, val);
  605. change = 1;
  606. }
  607. mutex_unlock(&ice->gpio_mutex);
  608. return change;
  609. }
  610. /*
  611. * Left/Right swap
  612. */
  613. #define wm_chswap_info snd_ctl_boolean_mono_info
  614. static int wm_chswap_get(struct snd_kcontrol *kcontrol,
  615. struct snd_ctl_elem_value *ucontrol)
  616. {
  617. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  618. mutex_lock(&ice->gpio_mutex);
  619. ucontrol->value.integer.value[0] =
  620. (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
  621. mutex_unlock(&ice->gpio_mutex);
  622. return 0;
  623. }
  624. static int wm_chswap_put(struct snd_kcontrol *kcontrol,
  625. struct snd_ctl_elem_value *ucontrol)
  626. {
  627. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  628. unsigned short val, oval;
  629. int change = 0;
  630. mutex_lock(&ice->gpio_mutex);
  631. oval = wm_get(ice, WM_DAC_CTRL1);
  632. val = oval & 0x0f;
  633. if (ucontrol->value.integer.value[0])
  634. val |= 0x60;
  635. else
  636. val |= 0x90;
  637. if (val != oval) {
  638. wm_put(ice, WM_DAC_CTRL1, val);
  639. wm_put_nocache(ice, WM_DAC_CTRL1, val);
  640. change = 1;
  641. }
  642. mutex_unlock(&ice->gpio_mutex);
  643. return change;
  644. }
  645. /*
  646. * mixers
  647. */
  648. static struct snd_kcontrol_new prodigy_hifi_controls[] = {
  649. {
  650. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  651. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  652. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  653. .name = "Master Playback Volume",
  654. .info = wm_master_vol_info,
  655. .get = wm_master_vol_get,
  656. .put = wm_master_vol_put,
  657. .tlv = { .p = db_scale_wm_dac }
  658. },
  659. {
  660. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  661. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  662. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  663. .name = "Front Playback Volume",
  664. .info = wm_dac_vol_info,
  665. .get = wm_dac_vol_get,
  666. .put = wm_dac_vol_put,
  667. .tlv = { .p = db_scale_wm_dac },
  668. },
  669. {
  670. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  671. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  672. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  673. .name = "Rear Playback Volume",
  674. .info = wm8766_vol_info,
  675. .get = wm8766_vol_get,
  676. .put = wm8766_vol_put,
  677. .private_value = (2 << 8) | 0,
  678. .tlv = { .p = db_scale_wm_dac },
  679. },
  680. {
  681. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  682. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  683. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  684. .name = "Center Playback Volume",
  685. .info = wm8766_vol_info,
  686. .get = wm8766_vol_get,
  687. .put = wm8766_vol_put,
  688. .private_value = (1 << 8) | 4,
  689. .tlv = { .p = db_scale_wm_dac }
  690. },
  691. {
  692. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  693. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  694. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  695. .name = "LFE Playback Volume",
  696. .info = wm8766_vol_info,
  697. .get = wm8766_vol_get,
  698. .put = wm8766_vol_put,
  699. .private_value = (1 << 8) | 5,
  700. .tlv = { .p = db_scale_wm_dac }
  701. },
  702. {
  703. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  704. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  705. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  706. .name = "Side Playback Volume",
  707. .info = wm8766_vol_info,
  708. .get = wm8766_vol_get,
  709. .put = wm8766_vol_put,
  710. .private_value = (2 << 8) | 6,
  711. .tlv = { .p = db_scale_wm_dac },
  712. },
  713. {
  714. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  715. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  716. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  717. .name = "Capture Volume",
  718. .info = wm_adc_vol_info,
  719. .get = wm_adc_vol_get,
  720. .put = wm_adc_vol_put,
  721. .tlv = { .p = db_scale_wm_dac },
  722. },
  723. {
  724. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  725. .name = "CD Capture Switch",
  726. .info = wm_adc_mux_info,
  727. .get = wm_adc_mux_get,
  728. .put = wm_adc_mux_put,
  729. .private_value = 0,
  730. },
  731. {
  732. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  733. .name = "Line Capture Switch",
  734. .info = wm_adc_mux_info,
  735. .get = wm_adc_mux_get,
  736. .put = wm_adc_mux_put,
  737. .private_value = 1,
  738. },
  739. {
  740. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  741. .name = "Analog Bypass Switch",
  742. .info = wm_bypass_info,
  743. .get = wm_bypass_get,
  744. .put = wm_bypass_put,
  745. },
  746. {
  747. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  748. .name = "Swap Output Channels",
  749. .info = wm_chswap_info,
  750. .get = wm_chswap_get,
  751. .put = wm_chswap_put,
  752. },
  753. {
  754. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  755. .name = "Analog Capture Source",
  756. .info = wm_adc_mux_enum_info,
  757. .get = wm_adc_mux_enum_get,
  758. .put = wm_adc_mux_enum_put,
  759. },
  760. };
  761. /*
  762. * WM codec registers
  763. */
  764. static void wm_proc_regs_write(struct snd_info_entry *entry,
  765. struct snd_info_buffer *buffer)
  766. {
  767. struct snd_ice1712 *ice = entry->private_data;
  768. char line[64];
  769. unsigned int reg, val;
  770. mutex_lock(&ice->gpio_mutex);
  771. while (!snd_info_get_line(buffer, line, sizeof(line))) {
  772. if (sscanf(line, "%x %x", &reg, &val) != 2)
  773. continue;
  774. if (reg <= 0x17 && val <= 0xffff)
  775. wm_put(ice, reg, val);
  776. }
  777. mutex_unlock(&ice->gpio_mutex);
  778. }
  779. static void wm_proc_regs_read(struct snd_info_entry *entry,
  780. struct snd_info_buffer *buffer)
  781. {
  782. struct snd_ice1712 *ice = entry->private_data;
  783. int reg, val;
  784. mutex_lock(&ice->gpio_mutex);
  785. for (reg = 0; reg <= 0x17; reg++) {
  786. val = wm_get(ice, reg);
  787. snd_iprintf(buffer, "%02x = %04x\n", reg, val);
  788. }
  789. mutex_unlock(&ice->gpio_mutex);
  790. }
  791. static void wm_proc_init(struct snd_ice1712 *ice)
  792. {
  793. struct snd_info_entry *entry;
  794. if (!snd_card_proc_new(ice->card, "wm_codec", &entry)) {
  795. snd_info_set_text_ops(entry, ice, wm_proc_regs_read);
  796. entry->mode |= 0200;
  797. entry->c.text.write = wm_proc_regs_write;
  798. }
  799. }
  800. static int prodigy_hifi_add_controls(struct snd_ice1712 *ice)
  801. {
  802. unsigned int i;
  803. int err;
  804. for (i = 0; i < ARRAY_SIZE(prodigy_hifi_controls); i++) {
  805. err = snd_ctl_add(ice->card,
  806. snd_ctl_new1(&prodigy_hifi_controls[i], ice));
  807. if (err < 0)
  808. return err;
  809. }
  810. wm_proc_init(ice);
  811. return 0;
  812. }
  813. static int prodigy_hd2_add_controls(struct snd_ice1712 *ice)
  814. {
  815. unsigned int i;
  816. int err;
  817. for (i = 0; i < ARRAY_SIZE(prodigy_hd2_controls); i++) {
  818. err = snd_ctl_add(ice->card,
  819. snd_ctl_new1(&prodigy_hd2_controls[i], ice));
  820. if (err < 0)
  821. return err;
  822. }
  823. wm_proc_init(ice);
  824. return 0;
  825. }
  826. static void wm8766_init(struct snd_ice1712 *ice)
  827. {
  828. static unsigned short wm8766_inits[] = {
  829. WM8766_RESET, 0x0000,
  830. WM8766_DAC_CTRL, 0x0120,
  831. WM8766_INT_CTRL, 0x0022, /* I2S Normal Mode, 24 bit */
  832. WM8766_DAC_CTRL2, 0x0001,
  833. WM8766_DAC_CTRL3, 0x0080,
  834. WM8766_LDA1, 0x0100,
  835. WM8766_LDA2, 0x0100,
  836. WM8766_LDA3, 0x0100,
  837. WM8766_RDA1, 0x0100,
  838. WM8766_RDA2, 0x0100,
  839. WM8766_RDA3, 0x0100,
  840. WM8766_MUTE1, 0x0000,
  841. WM8766_MUTE2, 0x0000,
  842. };
  843. unsigned int i;
  844. for (i = 0; i < ARRAY_SIZE(wm8766_inits); i += 2)
  845. wm8766_spi_write(ice, wm8766_inits[i], wm8766_inits[i + 1]);
  846. }
  847. static void wm8776_init(struct snd_ice1712 *ice)
  848. {
  849. static unsigned short wm8776_inits[] = {
  850. /* These come first to reduce init pop noise */
  851. WM_ADC_MUX, 0x0003, /* ADC mute */
  852. /* 0x00c0 replaced by 0x0003 */
  853. WM_DAC_MUTE, 0x0001, /* DAC softmute */
  854. WM_DAC_CTRL1, 0x0000, /* DAC mute */
  855. WM_POWERDOWN, 0x0008, /* All power-up except HP */
  856. WM_RESET, 0x0000, /* reset */
  857. };
  858. unsigned int i;
  859. for (i = 0; i < ARRAY_SIZE(wm8776_inits); i += 2)
  860. wm_put(ice, wm8776_inits[i], wm8776_inits[i + 1]);
  861. }
  862. #ifdef CONFIG_PM_SLEEP
  863. static int prodigy_hifi_resume(struct snd_ice1712 *ice)
  864. {
  865. static unsigned short wm8776_reinit_registers[] = {
  866. WM_MASTER_CTRL,
  867. WM_DAC_INT,
  868. WM_ADC_INT,
  869. WM_OUT_MUX,
  870. WM_HP_ATTEN_L,
  871. WM_HP_ATTEN_R,
  872. WM_PHASE_SWAP,
  873. WM_DAC_CTRL2,
  874. WM_ADC_ATTEN_L,
  875. WM_ADC_ATTEN_R,
  876. WM_ALC_CTRL1,
  877. WM_ALC_CTRL2,
  878. WM_ALC_CTRL3,
  879. WM_NOISE_GATE,
  880. WM_ADC_MUX,
  881. /* no DAC attenuation here */
  882. };
  883. struct prodigy_hifi_spec *spec = ice->spec;
  884. int i, ch;
  885. mutex_lock(&ice->gpio_mutex);
  886. /* reinitialize WM8776 and re-apply old register values */
  887. wm8776_init(ice);
  888. schedule_timeout_uninterruptible(1);
  889. for (i = 0; i < ARRAY_SIZE(wm8776_reinit_registers); i++)
  890. wm_put(ice, wm8776_reinit_registers[i],
  891. wm_get(ice, wm8776_reinit_registers[i]));
  892. /* reinitialize WM8766 and re-apply volumes for all DACs */
  893. wm8766_init(ice);
  894. for (ch = 0; ch < 2; ch++) {
  895. wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
  896. spec->vol[2 + ch], spec->master[ch]);
  897. wm8766_set_vol(ice, WM8766_LDA1 + ch,
  898. spec->vol[0 + ch], spec->master[ch]);
  899. wm8766_set_vol(ice, WM8766_LDA2 + ch,
  900. spec->vol[4 + ch], spec->master[ch]);
  901. wm8766_set_vol(ice, WM8766_LDA3 + ch,
  902. spec->vol[6 + ch], spec->master[ch]);
  903. }
  904. /* unmute WM8776 DAC */
  905. wm_put(ice, WM_DAC_MUTE, 0x00);
  906. wm_put(ice, WM_DAC_CTRL1, 0x90);
  907. mutex_unlock(&ice->gpio_mutex);
  908. return 0;
  909. }
  910. #endif
  911. /*
  912. * initialize the chip
  913. */
  914. static int prodigy_hifi_init(struct snd_ice1712 *ice)
  915. {
  916. static unsigned short wm8776_defaults[] = {
  917. WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
  918. WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  919. WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  920. WM_DAC_CTRL1, 0x0090, /* DAC L/R */
  921. WM_OUT_MUX, 0x0001, /* OUT DAC */
  922. WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
  923. WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
  924. WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
  925. WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
  926. WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
  927. WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
  928. WM_PHASE_SWAP, 0x0000, /* phase normal */
  929. #if 0
  930. WM_DAC_MASTER, 0x0100, /* DAC master muted */
  931. #endif
  932. WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
  933. WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
  934. WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
  935. #if 1
  936. WM_ALC_CTRL1, 0x007b, /* */
  937. WM_ALC_CTRL2, 0x0000, /* */
  938. WM_ALC_CTRL3, 0x0000, /* */
  939. WM_NOISE_GATE, 0x0000, /* */
  940. #endif
  941. WM_DAC_MUTE, 0x0000, /* DAC unmute */
  942. WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
  943. };
  944. struct prodigy_hifi_spec *spec;
  945. unsigned int i;
  946. ice->vt1720 = 0;
  947. ice->vt1724 = 1;
  948. ice->num_total_dacs = 8;
  949. ice->num_total_adcs = 1;
  950. /* HACK - use this as the SPDIF source.
  951. * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
  952. */
  953. ice->gpio.saved[0] = 0;
  954. /* to remember the register values */
  955. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  956. if (! ice->akm)
  957. return -ENOMEM;
  958. ice->akm_codecs = 1;
  959. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  960. if (!spec)
  961. return -ENOMEM;
  962. ice->spec = spec;
  963. /* initialize WM8776 codec */
  964. wm8776_init(ice);
  965. schedule_timeout_uninterruptible(1);
  966. for (i = 0; i < ARRAY_SIZE(wm8776_defaults); i += 2)
  967. wm_put(ice, wm8776_defaults[i], wm8776_defaults[i + 1]);
  968. wm8766_init(ice);
  969. #ifdef CONFIG_PM_SLEEP
  970. ice->pm_resume = &prodigy_hifi_resume;
  971. ice->pm_suspend_enabled = 1;
  972. #endif
  973. return 0;
  974. }
  975. /*
  976. * initialize the chip
  977. */
  978. static void ak4396_init(struct snd_ice1712 *ice)
  979. {
  980. static unsigned short ak4396_inits[] = {
  981. AK4396_CTRL1, 0x87, /* I2S Normal Mode, 24 bit */
  982. AK4396_CTRL2, 0x02,
  983. AK4396_CTRL3, 0x00,
  984. AK4396_LCH_ATT, 0x00,
  985. AK4396_RCH_ATT, 0x00,
  986. };
  987. unsigned int i;
  988. /* initialize ak4396 codec */
  989. /* reset codec */
  990. ak4396_write(ice, AK4396_CTRL1, 0x86);
  991. msleep(100);
  992. ak4396_write(ice, AK4396_CTRL1, 0x87);
  993. for (i = 0; i < ARRAY_SIZE(ak4396_inits); i += 2)
  994. ak4396_write(ice, ak4396_inits[i], ak4396_inits[i+1]);
  995. }
  996. #ifdef CONFIG_PM_SLEEP
  997. static int prodigy_hd2_resume(struct snd_ice1712 *ice)
  998. {
  999. /* initialize ak4396 codec and restore previous mixer volumes */
  1000. struct prodigy_hifi_spec *spec = ice->spec;
  1001. int i;
  1002. mutex_lock(&ice->gpio_mutex);
  1003. ak4396_init(ice);
  1004. for (i = 0; i < 2; i++)
  1005. ak4396_write(ice, AK4396_LCH_ATT + i, spec->vol[i] & 0xff);
  1006. mutex_unlock(&ice->gpio_mutex);
  1007. return 0;
  1008. }
  1009. #endif
  1010. static int prodigy_hd2_init(struct snd_ice1712 *ice)
  1011. {
  1012. struct prodigy_hifi_spec *spec;
  1013. ice->vt1720 = 0;
  1014. ice->vt1724 = 1;
  1015. ice->num_total_dacs = 1;
  1016. ice->num_total_adcs = 1;
  1017. /* HACK - use this as the SPDIF source.
  1018. * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
  1019. */
  1020. ice->gpio.saved[0] = 0;
  1021. /* to remember the register values */
  1022. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  1023. if (! ice->akm)
  1024. return -ENOMEM;
  1025. ice->akm_codecs = 1;
  1026. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1027. if (!spec)
  1028. return -ENOMEM;
  1029. ice->spec = spec;
  1030. #ifdef CONFIG_PM_SLEEP
  1031. ice->pm_resume = &prodigy_hd2_resume;
  1032. ice->pm_suspend_enabled = 1;
  1033. #endif
  1034. ak4396_init(ice);
  1035. return 0;
  1036. }
  1037. static unsigned char prodigy71hifi_eeprom[] = {
  1038. 0x4b, /* SYSCONF: clock 512, spdif-in/ADC, 4DACs */
  1039. 0x80, /* ACLINK: I2S */
  1040. 0xfc, /* I2S: vol, 96k, 24bit, 192k */
  1041. 0xc3, /* SPDIF: out-en, out-int, spdif-in */
  1042. 0xff, /* GPIO_DIR */
  1043. 0xff, /* GPIO_DIR1 */
  1044. 0x5f, /* GPIO_DIR2 */
  1045. 0x00, /* GPIO_MASK */
  1046. 0x00, /* GPIO_MASK1 */
  1047. 0x00, /* GPIO_MASK2 */
  1048. 0x00, /* GPIO_STATE */
  1049. 0x00, /* GPIO_STATE1 */
  1050. 0x00, /* GPIO_STATE2 */
  1051. };
  1052. static unsigned char prodigyhd2_eeprom[] = {
  1053. 0x4b, /* SYSCONF: clock 512, spdif-in/ADC, 4DACs */
  1054. 0x80, /* ACLINK: I2S */
  1055. 0xfc, /* I2S: vol, 96k, 24bit, 192k */
  1056. 0xc3, /* SPDIF: out-en, out-int, spdif-in */
  1057. 0xff, /* GPIO_DIR */
  1058. 0xff, /* GPIO_DIR1 */
  1059. 0x5f, /* GPIO_DIR2 */
  1060. 0x00, /* GPIO_MASK */
  1061. 0x00, /* GPIO_MASK1 */
  1062. 0x00, /* GPIO_MASK2 */
  1063. 0x00, /* GPIO_STATE */
  1064. 0x00, /* GPIO_STATE1 */
  1065. 0x00, /* GPIO_STATE2 */
  1066. };
  1067. static unsigned char fortissimo4_eeprom[] = {
  1068. 0x43, /* SYSCONF: clock 512, ADC, 4DACs */
  1069. 0x80, /* ACLINK: I2S */
  1070. 0xfc, /* I2S: vol, 96k, 24bit, 192k */
  1071. 0xc1, /* SPDIF: out-en, out-int */
  1072. 0xff, /* GPIO_DIR */
  1073. 0xff, /* GPIO_DIR1 */
  1074. 0x5f, /* GPIO_DIR2 */
  1075. 0x00, /* GPIO_MASK */
  1076. 0x00, /* GPIO_MASK1 */
  1077. 0x00, /* GPIO_MASK2 */
  1078. 0x00, /* GPIO_STATE */
  1079. 0x00, /* GPIO_STATE1 */
  1080. 0x00, /* GPIO_STATE2 */
  1081. };
  1082. /* entry point */
  1083. struct snd_ice1712_card_info snd_vt1724_prodigy_hifi_cards[] = {
  1084. {
  1085. .subvendor = VT1724_SUBDEVICE_PRODIGY_HIFI,
  1086. .name = "Audiotrak Prodigy 7.1 HiFi",
  1087. .model = "prodigy71hifi",
  1088. .chip_init = prodigy_hifi_init,
  1089. .build_controls = prodigy_hifi_add_controls,
  1090. .eeprom_size = sizeof(prodigy71hifi_eeprom),
  1091. .eeprom_data = prodigy71hifi_eeprom,
  1092. .driver = "Prodigy71HIFI",
  1093. },
  1094. {
  1095. .subvendor = VT1724_SUBDEVICE_PRODIGY_HD2,
  1096. .name = "Audiotrak Prodigy HD2",
  1097. .model = "prodigyhd2",
  1098. .chip_init = prodigy_hd2_init,
  1099. .build_controls = prodigy_hd2_add_controls,
  1100. .eeprom_size = sizeof(prodigyhd2_eeprom),
  1101. .eeprom_data = prodigyhd2_eeprom,
  1102. .driver = "Prodigy71HD2",
  1103. },
  1104. {
  1105. .subvendor = VT1724_SUBDEVICE_FORTISSIMO4,
  1106. .name = "Hercules Fortissimo IV",
  1107. .model = "fortissimo4",
  1108. .chip_init = prodigy_hifi_init,
  1109. .build_controls = prodigy_hifi_add_controls,
  1110. .eeprom_size = sizeof(fortissimo4_eeprom),
  1111. .eeprom_data = fortissimo4_eeprom,
  1112. .driver = "Fortissimo4",
  1113. },
  1114. { } /* terminator */
  1115. };