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linux-arkmicro
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sound
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arkmicro
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ark1668_i2s_sddac_regs.h

ark1668_i2s_sddac_regs.h 3.6 KB
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  1. /* 
    2. 

  2.  * ark_i2s_sddac_regs.h
    3. 

  3.  *
    4. 

  4.  */
    5. 

  5. #define ARK_SYS_PAD_CTRL06						0x1d8
    6. 

  6. #define ARK_SYS_I2S_DATA_DIR_OUT				(1 << 31)
    7. 

  7. #define ARK_SYS_I2S_BCLK_MASK					(0xf << 20)
    8. 

  8. #define ARK_SYS_I2S_MCLK_MASK					(0xf << 16)
    9. 

  9. #define ARK_SYS_I2S_SADATA_MASK				(0xf << 12)
    10. 

  10. #define ARK_SYS_I2S_SYNC_MASK					(0xf << 8)
    11. 

  11. 

  12. #define ARK_SYS_I2S_BCLK					(0x4 << 20)
    13. 

  13. #define ARK_SYS_I2S_MCLK					(0x4 << 16)
    14. 

  14. #define ARK_SYS_I2S_SADATA				(0x4 << 12)
    15. 

  15. #define ARK_SYS_I2S_SYNC					(0x4 << 8)
    16. 

  16. 

  17. 

  18. #define ARK_SYS_PAD_CTRL09						0x1e4
    19. 

  19. #define ARK_SYS_I2S2_BCLK							(3 << 28)
    20. 

  20. #define ARK_SYS_I2S2_SADATA						(3 << 26)
    21. 

  21. #define ARK_SYS_I2S2_SYNC						(3 << 24)
    22. 

  22. 

  23. #define ARK_SYS_PAD_CTRL0A						0x1e8
    24. 

  24. 

  25. 

  26. #define ARK_SYS_PAD_CTRL0C						0x1f0
    27. 

  27. #define ARK_SYS_I2S_MCLK_AUX				(1 << 10)
    28. 

  28. /* Register definition */
    29. 

  29. 

  30. #define ARK_I2SSDDAC_SACR0					0x00
    31. 

  31. #define ARK_I2SSDDAC_SACR0_I2SEN			(1 << 0)
    32. 

  32. #define ARK_I2SSDDAC_SACR0_SYNCD			(1 << 1)
    33. 

  33. #define ARK_I2SSDDAC_SACR0_BCKD		 		(1 << 2)
    34. 

  34. #define ARK_I2SSDDAC_SACR0_TDMAENA 			(1 << 3)
    35. 

  35. #define ARK_I2SSDDAC_SACR0_RESET	 		(1 << 4)
    36. 

  36. #define ARK_I2SSDDAC_SACR0_LOOPBACK			(1 << 5)
    37. 

  37. #define ARK_I2SSDDAC_SACR0_RDMAENA			(1 << 6)
    38. 

  38. #define ARK_I2SSDDAC_SACR0_DACCLK_EDGE		(1 << 7)
    39. 

  39. #define ARK_I2SSDDAC_SACR0_TFTH				(0xF << 8)
    40. 

  40. #define ARK_I2SSDDAC_SACR0_RFTH				(0x10 << 16)
    41. 

  41. #define ARK_I2SSDDAC_SACR0_VREF_PD			(1 << 21)
    42. 

  42. #define ARK_I2SSDDAC_SACR0_DAC_PD			(1 << 22)
    43. 

  43. #define ARK_I2SSDDAC_SACR0_SARADC_EN		(1 << 23)
    44. 

  44. #define ARK_I2SSDDAC_SACR0_SARADC_DATA		(1 << 24)
    45. 

  45. #define ARK_I2SSDDAC_SACR0_SARADC_POW_EN	(1 << 25)
    46. 

  46. #define ARK_I2SSDDAC_SACR0_MIC_LINE_SEL		(1 << 26)
    47. 

  47. #define ARK_I2SSDDAC_SACR0_ADC_PGA_OP		(1 << 27)
    48. 

  48. #define ARK_I2SSDDAC_SACR0_SARADC_VREF		(1 << 28)
    49. 

  49. 

  50. #define ARK_I2SSDDAC_SACR1					0x04
    51. 

  51. #define ARK_I2SSDDAC_SACR1_DIS_REC			(1 << 0)
    52. 

  52. #define ARK_I2SSDDAC_SACR1_DIS_PLAY			(1 << 1)
    53. 

  53. 

  54. #define ARK_I2SSDDAC_DACR0					0x08
    55. 

  55. #define ARK_I2SSDDAC_DACR0_LVOL				(0x7f << 0)
    56. 

  56. #define ARK_I2SSDDAC_DACR0_RVOL				(0x7f << 8)
    57. 

  57. 

  58. #define ARK_I2SSDDAC_SASR0					0x0C
    59. 

  59. #define ARK_I2SSDDAC_SASR0_TNF				(1 << 0)
    60. 

  60. #define ARK_I2SSDDAC_SASR0_RNE				(1 << 1)
    61. 

  61. #define ARK_I2SSDDAC_SASR0_BSY				(1 << 2)
    62. 

  62. #define ARK_I2SSDDAC_SASR0_TFS				(1 << 3)
    63. 

  63. #define ARK_I2SSDDAC_SASR0_RFS				(1 << 4)
    64. 

  64. #define ARK_I2SSDDAC_SASR0_TUR				(1 << 5)
    65. 

  65. #define ARK_I2SSDDAC_SASR0_ROR				(1 << 6)
    66. 

  66. #define ARK_I2SSDDAC_SASR0_TFL				(0x3F << 8)
    67. 

  67. #define ARK_I2SSDDAC_SASR0_RFL				(0x3F << 16)
    68. 

  68. 

  69. #define ARK_I2SSDDAC_DACR1					0x10
    70. 

  70. #define ARK_I2SSDDAC_DACR1_VOL_TH			(0x1F << 0)
    71. 

  71. #define ARK_I2SSDDAC_DACR1_LRSW				(1 << 5)
    72. 

  72. 

  73. /* Interrupt Mask */
    74. 

  74. #define ARK_I2SSDDAC_SAIMR					0x14
    75. 

  75. #define ARK_I2SSDDAC_SAIMR_TFS				(1 << 3)
    76. 

  76. #define ARK_I2SSDDAC_SAIMR_RFS				(1 << 4)
    77. 

  77. #define ARK_I2SSDDAC_SAIMR_TUR				(1 << 5)
    78. 

  78. #define ARK_I2SSDDAC_SAIMR_ROR				(1 << 6)
    79. 

  79. 

  80. /* Interrupt Clear */
    81. 

  81. #define ARK_I2SSDDAC_SAICR					0x18
    82. 

  82. #define ARK_I2SSDDAC_SAICR_TXCR				(1 << 3)
    83. 

  83. #define ARK_I2SSDDAC_SAICR_RXCR				(1 << 4)
    84. 

  84. #define ARK_I2SSDDAC_SAICR_TUR				(1 << 5)
    85. 

  85. #define ARK_I2SSDDAC_SAICR_ROR				(1 << 6)
    86. 

  86. 

  87. /* SARADC Control Register */
    88. 

  88. #define ARK_I2SSDDAC_ADCR0					0x1C
    89. 

  89. #define ARK_I2SSDDAC_ADCR0_LCH_VOL			(0xF << 0)
    90. 

  90. #define ARK_I2SSDDAC_ADCR0_RCH_VOL			(0xF << 4)
    91. 

  91. #define ARK_I2SSDDAC_ADCR0_MIC_ENH			(1 << 8)
    92. 

  92. #define ARK_I2SSDDAC_ADCR0_LCH_FILTER		(0x3 << 9)
    93. 

  93. #define ARK_I2SSDDAC_ADCR0_RCH_FILTER		(0x3 << 11)
    94. 

  94. 

  95. /* Serial Audio Data Register (TX and RX FIFO Access) */
    96. 

  96. #define ARK_I2SSDDAC_SADR					0x80
    97. 

  97. 

  98. 

  99. /* FIFO Size */
    100. 

  100. #define ARK_I2S_TXFIFO_SIZE					32
    101. 

  101. #define ARK_I2S_RXFIFO_SIZE					32
    102. 

  102. 

  103. /* DMA Port Number */
    104. 

  104. #define ARK_I2S_DMA_TX 						1 	/* TODO: refer to Arkmicro DMA */
    105. 

  105. #define ARK_I2S_DMA_RX						2	/* TODO: refer to Arkmicro DMA */
    106. 

  106. 

  107. /* TX and RX thershold */
    108. 

  108. #define ARK_I2S_TX_TH						15
    109. 

  109. #define ARK_I2S_RX_TH						16
    110. 

  110.