pipeline.json 27 KB

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  1. [
  2. {
  3. "EventCode": "0x14",
  4. "Counter": "0,1,2,3",
  5. "UMask": "0x1",
  6. "EventName": "ARITH.CYCLES_DIV_BUSY",
  7. "SampleAfterValue": "2000000",
  8. "BriefDescription": "Cycles the divider is busy"
  9. },
  10. {
  11. "EventCode": "0x14",
  12. "Invert": "1",
  13. "Counter": "0,1,2,3",
  14. "UMask": "0x1",
  15. "EventName": "ARITH.DIV",
  16. "SampleAfterValue": "2000000",
  17. "BriefDescription": "Divide Operations executed",
  18. "CounterMask": "1",
  19. "EdgeDetect": "1"
  20. },
  21. {
  22. "EventCode": "0x14",
  23. "Counter": "0,1,2,3",
  24. "UMask": "0x2",
  25. "EventName": "ARITH.MUL",
  26. "SampleAfterValue": "2000000",
  27. "BriefDescription": "Multiply operations executed"
  28. },
  29. {
  30. "EventCode": "0xE6",
  31. "Counter": "0,1,2,3",
  32. "UMask": "0x2",
  33. "EventName": "BACLEAR.BAD_TARGET",
  34. "SampleAfterValue": "2000000",
  35. "BriefDescription": "BACLEAR asserted with bad target address"
  36. },
  37. {
  38. "EventCode": "0xE6",
  39. "Counter": "0,1,2,3",
  40. "UMask": "0x1",
  41. "EventName": "BACLEAR.CLEAR",
  42. "SampleAfterValue": "2000000",
  43. "BriefDescription": "BACLEAR asserted, regardless of cause "
  44. },
  45. {
  46. "EventCode": "0xA7",
  47. "Counter": "0,1,2,3",
  48. "UMask": "0x1",
  49. "EventName": "BACLEAR_FORCE_IQ",
  50. "SampleAfterValue": "2000000",
  51. "BriefDescription": "Instruction queue forced BACLEAR"
  52. },
  53. {
  54. "EventCode": "0xE0",
  55. "Counter": "0,1,2,3",
  56. "UMask": "0x1",
  57. "EventName": "BR_INST_DECODED",
  58. "SampleAfterValue": "2000000",
  59. "BriefDescription": "Branch instructions decoded"
  60. },
  61. {
  62. "EventCode": "0x88",
  63. "Counter": "0,1,2,3",
  64. "UMask": "0x7f",
  65. "EventName": "BR_INST_EXEC.ANY",
  66. "SampleAfterValue": "200000",
  67. "BriefDescription": "Branch instructions executed"
  68. },
  69. {
  70. "EventCode": "0x88",
  71. "Counter": "0,1,2,3",
  72. "UMask": "0x1",
  73. "EventName": "BR_INST_EXEC.COND",
  74. "SampleAfterValue": "200000",
  75. "BriefDescription": "Conditional branch instructions executed"
  76. },
  77. {
  78. "EventCode": "0x88",
  79. "Counter": "0,1,2,3",
  80. "UMask": "0x2",
  81. "EventName": "BR_INST_EXEC.DIRECT",
  82. "SampleAfterValue": "200000",
  83. "BriefDescription": "Unconditional branches executed"
  84. },
  85. {
  86. "EventCode": "0x88",
  87. "Counter": "0,1,2,3",
  88. "UMask": "0x10",
  89. "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
  90. "SampleAfterValue": "20000",
  91. "BriefDescription": "Unconditional call branches executed"
  92. },
  93. {
  94. "EventCode": "0x88",
  95. "Counter": "0,1,2,3",
  96. "UMask": "0x20",
  97. "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
  98. "SampleAfterValue": "20000",
  99. "BriefDescription": "Indirect call branches executed"
  100. },
  101. {
  102. "EventCode": "0x88",
  103. "Counter": "0,1,2,3",
  104. "UMask": "0x4",
  105. "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
  106. "SampleAfterValue": "20000",
  107. "BriefDescription": "Indirect non call branches executed"
  108. },
  109. {
  110. "EventCode": "0x88",
  111. "Counter": "0,1,2,3",
  112. "UMask": "0x30",
  113. "EventName": "BR_INST_EXEC.NEAR_CALLS",
  114. "SampleAfterValue": "20000",
  115. "BriefDescription": "Call branches executed"
  116. },
  117. {
  118. "EventCode": "0x88",
  119. "Counter": "0,1,2,3",
  120. "UMask": "0x7",
  121. "EventName": "BR_INST_EXEC.NON_CALLS",
  122. "SampleAfterValue": "200000",
  123. "BriefDescription": "All non call branches executed"
  124. },
  125. {
  126. "EventCode": "0x88",
  127. "Counter": "0,1,2,3",
  128. "UMask": "0x8",
  129. "EventName": "BR_INST_EXEC.RETURN_NEAR",
  130. "SampleAfterValue": "20000",
  131. "BriefDescription": "Indirect return branches executed"
  132. },
  133. {
  134. "EventCode": "0x88",
  135. "Counter": "0,1,2,3",
  136. "UMask": "0x40",
  137. "EventName": "BR_INST_EXEC.TAKEN",
  138. "SampleAfterValue": "200000",
  139. "BriefDescription": "Taken branches executed"
  140. },
  141. {
  142. "PEBS": "1",
  143. "EventCode": "0xC4",
  144. "Counter": "0,1,2,3",
  145. "UMask": "0x4",
  146. "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
  147. "SampleAfterValue": "200000",
  148. "BriefDescription": "Retired branch instructions (Precise Event)"
  149. },
  150. {
  151. "PEBS": "1",
  152. "EventCode": "0xC4",
  153. "Counter": "0,1,2,3",
  154. "UMask": "0x1",
  155. "EventName": "BR_INST_RETIRED.CONDITIONAL",
  156. "SampleAfterValue": "200000",
  157. "BriefDescription": "Retired conditional branch instructions (Precise Event)"
  158. },
  159. {
  160. "PEBS": "1",
  161. "EventCode": "0xC4",
  162. "Counter": "0,1,2,3",
  163. "UMask": "0x2",
  164. "EventName": "BR_INST_RETIRED.NEAR_CALL",
  165. "SampleAfterValue": "20000",
  166. "BriefDescription": "Retired near call instructions (Precise Event)"
  167. },
  168. {
  169. "EventCode": "0x89",
  170. "Counter": "0,1,2,3",
  171. "UMask": "0x7f",
  172. "EventName": "BR_MISP_EXEC.ANY",
  173. "SampleAfterValue": "20000",
  174. "BriefDescription": "Mispredicted branches executed"
  175. },
  176. {
  177. "EventCode": "0x89",
  178. "Counter": "0,1,2,3",
  179. "UMask": "0x1",
  180. "EventName": "BR_MISP_EXEC.COND",
  181. "SampleAfterValue": "20000",
  182. "BriefDescription": "Mispredicted conditional branches executed"
  183. },
  184. {
  185. "EventCode": "0x89",
  186. "Counter": "0,1,2,3",
  187. "UMask": "0x2",
  188. "EventName": "BR_MISP_EXEC.DIRECT",
  189. "SampleAfterValue": "20000",
  190. "BriefDescription": "Mispredicted unconditional branches executed"
  191. },
  192. {
  193. "EventCode": "0x89",
  194. "Counter": "0,1,2,3",
  195. "UMask": "0x10",
  196. "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
  197. "SampleAfterValue": "2000",
  198. "BriefDescription": "Mispredicted non call branches executed"
  199. },
  200. {
  201. "EventCode": "0x89",
  202. "Counter": "0,1,2,3",
  203. "UMask": "0x20",
  204. "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
  205. "SampleAfterValue": "2000",
  206. "BriefDescription": "Mispredicted indirect call branches executed"
  207. },
  208. {
  209. "EventCode": "0x89",
  210. "Counter": "0,1,2,3",
  211. "UMask": "0x4",
  212. "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
  213. "SampleAfterValue": "2000",
  214. "BriefDescription": "Mispredicted indirect non call branches executed"
  215. },
  216. {
  217. "EventCode": "0x89",
  218. "Counter": "0,1,2,3",
  219. "UMask": "0x30",
  220. "EventName": "BR_MISP_EXEC.NEAR_CALLS",
  221. "SampleAfterValue": "2000",
  222. "BriefDescription": "Mispredicted call branches executed"
  223. },
  224. {
  225. "EventCode": "0x89",
  226. "Counter": "0,1,2,3",
  227. "UMask": "0x7",
  228. "EventName": "BR_MISP_EXEC.NON_CALLS",
  229. "SampleAfterValue": "20000",
  230. "BriefDescription": "Mispredicted non call branches executed"
  231. },
  232. {
  233. "EventCode": "0x89",
  234. "Counter": "0,1,2,3",
  235. "UMask": "0x8",
  236. "EventName": "BR_MISP_EXEC.RETURN_NEAR",
  237. "SampleAfterValue": "2000",
  238. "BriefDescription": "Mispredicted return branches executed"
  239. },
  240. {
  241. "EventCode": "0x89",
  242. "Counter": "0,1,2,3",
  243. "UMask": "0x40",
  244. "EventName": "BR_MISP_EXEC.TAKEN",
  245. "SampleAfterValue": "20000",
  246. "BriefDescription": "Mispredicted taken branches executed"
  247. },
  248. {
  249. "PEBS": "1",
  250. "EventCode": "0xC5",
  251. "Counter": "0,1,2,3",
  252. "UMask": "0x4",
  253. "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
  254. "SampleAfterValue": "20000",
  255. "BriefDescription": "Mispredicted retired branch instructions (Precise Event)"
  256. },
  257. {
  258. "PEBS": "1",
  259. "EventCode": "0xC5",
  260. "Counter": "0,1,2,3",
  261. "UMask": "0x1",
  262. "EventName": "BR_MISP_RETIRED.CONDITIONAL",
  263. "SampleAfterValue": "20000",
  264. "BriefDescription": "Mispredicted conditional retired branches (Precise Event)"
  265. },
  266. {
  267. "PEBS": "1",
  268. "EventCode": "0xC5",
  269. "Counter": "0,1,2,3",
  270. "UMask": "0x2",
  271. "EventName": "BR_MISP_RETIRED.NEAR_CALL",
  272. "SampleAfterValue": "2000",
  273. "BriefDescription": "Mispredicted near retired calls (Precise Event)"
  274. },
  275. {
  276. "EventCode": "0x0",
  277. "Counter": "Fixed counter 3",
  278. "UMask": "0x0",
  279. "EventName": "CPU_CLK_UNHALTED.REF",
  280. "SampleAfterValue": "2000000",
  281. "BriefDescription": "Reference cycles when thread is not halted (fixed counter)"
  282. },
  283. {
  284. "EventCode": "0x3C",
  285. "Counter": "0,1,2,3",
  286. "UMask": "0x1",
  287. "EventName": "CPU_CLK_UNHALTED.REF_P",
  288. "SampleAfterValue": "100000",
  289. "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
  290. },
  291. {
  292. "EventCode": "0x0",
  293. "Counter": "Fixed counter 2",
  294. "UMask": "0x0",
  295. "EventName": "CPU_CLK_UNHALTED.THREAD",
  296. "SampleAfterValue": "2000000",
  297. "BriefDescription": "Cycles when thread is not halted (fixed counter)"
  298. },
  299. {
  300. "EventCode": "0x3C",
  301. "Counter": "0,1,2,3",
  302. "UMask": "0x0",
  303. "EventName": "CPU_CLK_UNHALTED.THREAD_P",
  304. "SampleAfterValue": "2000000",
  305. "BriefDescription": "Cycles when thread is not halted (programmable counter)"
  306. },
  307. {
  308. "EventCode": "0x3C",
  309. "Invert": "1",
  310. "Counter": "0,1,2,3",
  311. "UMask": "0x0",
  312. "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
  313. "SampleAfterValue": "2000000",
  314. "BriefDescription": "Total CPU cycles",
  315. "CounterMask": "2"
  316. },
  317. {
  318. "EventCode": "0x87",
  319. "Counter": "0,1,2,3",
  320. "UMask": "0xf",
  321. "EventName": "ILD_STALL.ANY",
  322. "SampleAfterValue": "2000000",
  323. "BriefDescription": "Any Instruction Length Decoder stall cycles"
  324. },
  325. {
  326. "EventCode": "0x87",
  327. "Counter": "0,1,2,3",
  328. "UMask": "0x4",
  329. "EventName": "ILD_STALL.IQ_FULL",
  330. "SampleAfterValue": "2000000",
  331. "BriefDescription": "Instruction Queue full stall cycles"
  332. },
  333. {
  334. "EventCode": "0x87",
  335. "Counter": "0,1,2,3",
  336. "UMask": "0x1",
  337. "EventName": "ILD_STALL.LCP",
  338. "SampleAfterValue": "2000000",
  339. "BriefDescription": "Length Change Prefix stall cycles"
  340. },
  341. {
  342. "EventCode": "0x87",
  343. "Counter": "0,1,2,3",
  344. "UMask": "0x2",
  345. "EventName": "ILD_STALL.MRU",
  346. "SampleAfterValue": "2000000",
  347. "BriefDescription": "Stall cycles due to BPU MRU bypass"
  348. },
  349. {
  350. "EventCode": "0x87",
  351. "Counter": "0,1,2,3",
  352. "UMask": "0x8",
  353. "EventName": "ILD_STALL.REGEN",
  354. "SampleAfterValue": "2000000",
  355. "BriefDescription": "Regen stall cycles"
  356. },
  357. {
  358. "EventCode": "0x18",
  359. "Counter": "0,1,2,3",
  360. "UMask": "0x1",
  361. "EventName": "INST_DECODED.DEC0",
  362. "SampleAfterValue": "2000000",
  363. "BriefDescription": "Instructions that must be decoded by decoder 0"
  364. },
  365. {
  366. "EventCode": "0x1E",
  367. "Counter": "0,1,2,3",
  368. "UMask": "0x1",
  369. "EventName": "INST_QUEUE_WRITE_CYCLES",
  370. "SampleAfterValue": "2000000",
  371. "BriefDescription": "Cycles instructions are written to the instruction queue"
  372. },
  373. {
  374. "EventCode": "0x17",
  375. "Counter": "0,1,2,3",
  376. "UMask": "0x1",
  377. "EventName": "INST_QUEUE_WRITES",
  378. "SampleAfterValue": "2000000",
  379. "BriefDescription": "Instructions written to instruction queue."
  380. },
  381. {
  382. "EventCode": "0x0",
  383. "Counter": "Fixed counter 1",
  384. "UMask": "0x0",
  385. "EventName": "INST_RETIRED.ANY",
  386. "SampleAfterValue": "2000000",
  387. "BriefDescription": "Instructions retired (fixed counter)"
  388. },
  389. {
  390. "PEBS": "1",
  391. "EventCode": "0xC0",
  392. "Counter": "0,1,2,3",
  393. "UMask": "0x1",
  394. "EventName": "INST_RETIRED.ANY_P",
  395. "SampleAfterValue": "2000000",
  396. "BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
  397. },
  398. {
  399. "PEBS": "1",
  400. "EventCode": "0xC0",
  401. "Counter": "0,1,2,3",
  402. "UMask": "0x4",
  403. "EventName": "INST_RETIRED.MMX",
  404. "SampleAfterValue": "2000000",
  405. "BriefDescription": "Retired MMX instructions (Precise Event)"
  406. },
  407. {
  408. "PEBS": "1",
  409. "EventCode": "0xC0",
  410. "Invert": "1",
  411. "Counter": "0,1,2,3",
  412. "UMask": "0x1",
  413. "EventName": "INST_RETIRED.TOTAL_CYCLES",
  414. "SampleAfterValue": "2000000",
  415. "BriefDescription": "Total cycles (Precise Event)",
  416. "CounterMask": "16"
  417. },
  418. {
  419. "PEBS": "1",
  420. "EventCode": "0xC0",
  421. "Counter": "0,1,2,3",
  422. "UMask": "0x2",
  423. "EventName": "INST_RETIRED.X87",
  424. "SampleAfterValue": "2000000",
  425. "BriefDescription": "Retired floating-point operations (Precise Event)"
  426. },
  427. {
  428. "EventCode": "0x4C",
  429. "Counter": "0,1",
  430. "UMask": "0x1",
  431. "EventName": "LOAD_HIT_PRE",
  432. "SampleAfterValue": "200000",
  433. "BriefDescription": "Load operations conflicting with software prefetches"
  434. },
  435. {
  436. "EventCode": "0xA8",
  437. "Counter": "0,1,2,3",
  438. "UMask": "0x1",
  439. "EventName": "LSD.ACTIVE",
  440. "SampleAfterValue": "2000000",
  441. "BriefDescription": "Cycles when uops were delivered by the LSD",
  442. "CounterMask": "1"
  443. },
  444. {
  445. "EventCode": "0xA8",
  446. "Invert": "1",
  447. "Counter": "0,1,2,3",
  448. "UMask": "0x1",
  449. "EventName": "LSD.INACTIVE",
  450. "SampleAfterValue": "2000000",
  451. "BriefDescription": "Cycles no uops were delivered by the LSD",
  452. "CounterMask": "1"
  453. },
  454. {
  455. "EventCode": "0x20",
  456. "Counter": "0,1,2,3",
  457. "UMask": "0x1",
  458. "EventName": "LSD_OVERFLOW",
  459. "SampleAfterValue": "2000000",
  460. "BriefDescription": "Loops that can't stream from the instruction queue"
  461. },
  462. {
  463. "EventCode": "0xC3",
  464. "Counter": "0,1,2,3",
  465. "UMask": "0x1",
  466. "EventName": "MACHINE_CLEARS.CYCLES",
  467. "SampleAfterValue": "20000",
  468. "BriefDescription": "Cycles machine clear asserted"
  469. },
  470. {
  471. "EventCode": "0xC3",
  472. "Counter": "0,1,2,3",
  473. "UMask": "0x2",
  474. "EventName": "MACHINE_CLEARS.MEM_ORDER",
  475. "SampleAfterValue": "20000",
  476. "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts"
  477. },
  478. {
  479. "EventCode": "0xC3",
  480. "Counter": "0,1,2,3",
  481. "UMask": "0x4",
  482. "EventName": "MACHINE_CLEARS.SMC",
  483. "SampleAfterValue": "20000",
  484. "BriefDescription": "Self-Modifying Code detected"
  485. },
  486. {
  487. "EventCode": "0xA2",
  488. "Counter": "0,1,2,3",
  489. "UMask": "0x1",
  490. "EventName": "RESOURCE_STALLS.ANY",
  491. "SampleAfterValue": "2000000",
  492. "BriefDescription": "Resource related stall cycles"
  493. },
  494. {
  495. "EventCode": "0xA2",
  496. "Counter": "0,1,2,3",
  497. "UMask": "0x20",
  498. "EventName": "RESOURCE_STALLS.FPCW",
  499. "SampleAfterValue": "2000000",
  500. "BriefDescription": "FPU control word write stall cycles"
  501. },
  502. {
  503. "EventCode": "0xA2",
  504. "Counter": "0,1,2,3",
  505. "UMask": "0x2",
  506. "EventName": "RESOURCE_STALLS.LOAD",
  507. "SampleAfterValue": "2000000",
  508. "BriefDescription": "Load buffer stall cycles"
  509. },
  510. {
  511. "EventCode": "0xA2",
  512. "Counter": "0,1,2,3",
  513. "UMask": "0x40",
  514. "EventName": "RESOURCE_STALLS.MXCSR",
  515. "SampleAfterValue": "2000000",
  516. "BriefDescription": "MXCSR rename stall cycles"
  517. },
  518. {
  519. "EventCode": "0xA2",
  520. "Counter": "0,1,2,3",
  521. "UMask": "0x80",
  522. "EventName": "RESOURCE_STALLS.OTHER",
  523. "SampleAfterValue": "2000000",
  524. "BriefDescription": "Other Resource related stall cycles"
  525. },
  526. {
  527. "EventCode": "0xA2",
  528. "Counter": "0,1,2,3",
  529. "UMask": "0x10",
  530. "EventName": "RESOURCE_STALLS.ROB_FULL",
  531. "SampleAfterValue": "2000000",
  532. "BriefDescription": "ROB full stall cycles"
  533. },
  534. {
  535. "EventCode": "0xA2",
  536. "Counter": "0,1,2,3",
  537. "UMask": "0x4",
  538. "EventName": "RESOURCE_STALLS.RS_FULL",
  539. "SampleAfterValue": "2000000",
  540. "BriefDescription": "Reservation Station full stall cycles"
  541. },
  542. {
  543. "EventCode": "0xA2",
  544. "Counter": "0,1,2,3",
  545. "UMask": "0x8",
  546. "EventName": "RESOURCE_STALLS.STORE",
  547. "SampleAfterValue": "2000000",
  548. "BriefDescription": "Store buffer stall cycles"
  549. },
  550. {
  551. "PEBS": "1",
  552. "EventCode": "0xC7",
  553. "Counter": "0,1,2,3",
  554. "UMask": "0x4",
  555. "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
  556. "SampleAfterValue": "200000",
  557. "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)"
  558. },
  559. {
  560. "PEBS": "1",
  561. "EventCode": "0xC7",
  562. "Counter": "0,1,2,3",
  563. "UMask": "0x1",
  564. "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
  565. "SampleAfterValue": "200000",
  566. "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)"
  567. },
  568. {
  569. "PEBS": "1",
  570. "EventCode": "0xC7",
  571. "Counter": "0,1,2,3",
  572. "UMask": "0x8",
  573. "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
  574. "SampleAfterValue": "200000",
  575. "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)"
  576. },
  577. {
  578. "PEBS": "1",
  579. "EventCode": "0xC7",
  580. "Counter": "0,1,2,3",
  581. "UMask": "0x2",
  582. "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
  583. "SampleAfterValue": "200000",
  584. "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)"
  585. },
  586. {
  587. "PEBS": "1",
  588. "EventCode": "0xC7",
  589. "Counter": "0,1,2,3",
  590. "UMask": "0x10",
  591. "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
  592. "SampleAfterValue": "200000",
  593. "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)"
  594. },
  595. {
  596. "EventCode": "0xDB",
  597. "Counter": "0,1,2,3",
  598. "UMask": "0x1",
  599. "EventName": "UOP_UNFUSION",
  600. "SampleAfterValue": "2000000",
  601. "BriefDescription": "Uop unfusions due to FP exceptions"
  602. },
  603. {
  604. "EventCode": "0xD1",
  605. "Counter": "0,1,2,3",
  606. "UMask": "0x4",
  607. "EventName": "UOPS_DECODED.ESP_FOLDING",
  608. "SampleAfterValue": "2000000",
  609. "BriefDescription": "Stack pointer instructions decoded"
  610. },
  611. {
  612. "EventCode": "0xD1",
  613. "Counter": "0,1,2,3",
  614. "UMask": "0x8",
  615. "EventName": "UOPS_DECODED.ESP_SYNC",
  616. "SampleAfterValue": "2000000",
  617. "BriefDescription": "Stack pointer sync operations"
  618. },
  619. {
  620. "EventCode": "0xD1",
  621. "Counter": "0,1,2,3",
  622. "UMask": "0x2",
  623. "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
  624. "SampleAfterValue": "2000000",
  625. "BriefDescription": "Uops decoded by Microcode Sequencer",
  626. "CounterMask": "1"
  627. },
  628. {
  629. "EventCode": "0xD1",
  630. "Invert": "1",
  631. "Counter": "0,1,2,3",
  632. "UMask": "0x1",
  633. "EventName": "UOPS_DECODED.STALL_CYCLES",
  634. "SampleAfterValue": "2000000",
  635. "BriefDescription": "Cycles no Uops are decoded",
  636. "CounterMask": "1"
  637. },
  638. {
  639. "EventCode": "0xB1",
  640. "Counter": "0,1,2,3",
  641. "UMask": "0x3f",
  642. "AnyThread": "1",
  643. "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
  644. "SampleAfterValue": "2000000",
  645. "BriefDescription": "Cycles Uops executed on any port (core count)",
  646. "CounterMask": "1"
  647. },
  648. {
  649. "EventCode": "0xB1",
  650. "Counter": "0,1,2,3",
  651. "UMask": "0x1f",
  652. "AnyThread": "1",
  653. "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
  654. "SampleAfterValue": "2000000",
  655. "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
  656. "CounterMask": "1"
  657. },
  658. {
  659. "EventCode": "0xB1",
  660. "Invert": "1",
  661. "Counter": "0,1,2,3",
  662. "UMask": "0x3f",
  663. "AnyThread": "1",
  664. "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
  665. "SampleAfterValue": "2000000",
  666. "BriefDescription": "Uops executed on any port (core count)",
  667. "CounterMask": "1",
  668. "EdgeDetect": "1"
  669. },
  670. {
  671. "EventCode": "0xB1",
  672. "Invert": "1",
  673. "Counter": "0,1,2,3",
  674. "UMask": "0x1f",
  675. "AnyThread": "1",
  676. "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
  677. "SampleAfterValue": "2000000",
  678. "BriefDescription": "Uops executed on ports 0-4 (core count)",
  679. "CounterMask": "1",
  680. "EdgeDetect": "1"
  681. },
  682. {
  683. "EventCode": "0xB1",
  684. "Invert": "1",
  685. "Counter": "0,1,2,3",
  686. "UMask": "0x3f",
  687. "AnyThread": "1",
  688. "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
  689. "SampleAfterValue": "2000000",
  690. "BriefDescription": "Cycles no Uops issued on any port (core count)",
  691. "CounterMask": "1"
  692. },
  693. {
  694. "EventCode": "0xB1",
  695. "Invert": "1",
  696. "Counter": "0,1,2,3",
  697. "UMask": "0x1f",
  698. "AnyThread": "1",
  699. "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
  700. "SampleAfterValue": "2000000",
  701. "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
  702. "CounterMask": "1"
  703. },
  704. {
  705. "EventCode": "0xB1",
  706. "Counter": "0,1,2,3",
  707. "UMask": "0x1",
  708. "EventName": "UOPS_EXECUTED.PORT0",
  709. "SampleAfterValue": "2000000",
  710. "BriefDescription": "Uops executed on port 0"
  711. },
  712. {
  713. "EventCode": "0xB1",
  714. "Counter": "0,1,2,3",
  715. "UMask": "0x40",
  716. "EventName": "UOPS_EXECUTED.PORT015",
  717. "SampleAfterValue": "2000000",
  718. "BriefDescription": "Uops issued on ports 0, 1 or 5"
  719. },
  720. {
  721. "EventCode": "0xB1",
  722. "Invert": "1",
  723. "Counter": "0,1,2,3",
  724. "UMask": "0x40",
  725. "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
  726. "SampleAfterValue": "2000000",
  727. "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
  728. "CounterMask": "1"
  729. },
  730. {
  731. "EventCode": "0xB1",
  732. "Counter": "0,1,2,3",
  733. "UMask": "0x2",
  734. "EventName": "UOPS_EXECUTED.PORT1",
  735. "SampleAfterValue": "2000000",
  736. "BriefDescription": "Uops executed on port 1"
  737. },
  738. {
  739. "EventCode": "0xB1",
  740. "Counter": "0,1,2,3",
  741. "UMask": "0x4",
  742. "AnyThread": "1",
  743. "EventName": "UOPS_EXECUTED.PORT2_CORE",
  744. "SampleAfterValue": "2000000",
  745. "BriefDescription": "Uops executed on port 2 (core count)"
  746. },
  747. {
  748. "EventCode": "0xB1",
  749. "Counter": "0,1,2,3",
  750. "UMask": "0x80",
  751. "AnyThread": "1",
  752. "EventName": "UOPS_EXECUTED.PORT234_CORE",
  753. "SampleAfterValue": "2000000",
  754. "BriefDescription": "Uops issued on ports 2, 3 or 4"
  755. },
  756. {
  757. "EventCode": "0xB1",
  758. "Counter": "0,1,2,3",
  759. "UMask": "0x8",
  760. "AnyThread": "1",
  761. "EventName": "UOPS_EXECUTED.PORT3_CORE",
  762. "SampleAfterValue": "2000000",
  763. "BriefDescription": "Uops executed on port 3 (core count)"
  764. },
  765. {
  766. "EventCode": "0xB1",
  767. "Counter": "0,1,2,3",
  768. "UMask": "0x10",
  769. "AnyThread": "1",
  770. "EventName": "UOPS_EXECUTED.PORT4_CORE",
  771. "SampleAfterValue": "2000000",
  772. "BriefDescription": "Uops executed on port 4 (core count)"
  773. },
  774. {
  775. "EventCode": "0xB1",
  776. "Counter": "0,1,2,3",
  777. "UMask": "0x20",
  778. "EventName": "UOPS_EXECUTED.PORT5",
  779. "SampleAfterValue": "2000000",
  780. "BriefDescription": "Uops executed on port 5"
  781. },
  782. {
  783. "EventCode": "0xE",
  784. "Counter": "0,1,2,3",
  785. "UMask": "0x1",
  786. "EventName": "UOPS_ISSUED.ANY",
  787. "SampleAfterValue": "2000000",
  788. "BriefDescription": "Uops issued"
  789. },
  790. {
  791. "EventCode": "0xE",
  792. "Invert": "1",
  793. "Counter": "0,1,2,3",
  794. "UMask": "0x1",
  795. "AnyThread": "1",
  796. "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
  797. "SampleAfterValue": "2000000",
  798. "BriefDescription": "Cycles no Uops were issued on any thread",
  799. "CounterMask": "1"
  800. },
  801. {
  802. "EventCode": "0xE",
  803. "Counter": "0,1,2,3",
  804. "UMask": "0x1",
  805. "AnyThread": "1",
  806. "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
  807. "SampleAfterValue": "2000000",
  808. "BriefDescription": "Cycles Uops were issued on either thread",
  809. "CounterMask": "1"
  810. },
  811. {
  812. "EventCode": "0xE",
  813. "Counter": "0,1,2,3",
  814. "UMask": "0x2",
  815. "EventName": "UOPS_ISSUED.FUSED",
  816. "SampleAfterValue": "2000000",
  817. "BriefDescription": "Fused Uops issued"
  818. },
  819. {
  820. "EventCode": "0xE",
  821. "Invert": "1",
  822. "Counter": "0,1,2,3",
  823. "UMask": "0x1",
  824. "EventName": "UOPS_ISSUED.STALL_CYCLES",
  825. "SampleAfterValue": "2000000",
  826. "BriefDescription": "Cycles no Uops were issued",
  827. "CounterMask": "1"
  828. },
  829. {
  830. "PEBS": "1",
  831. "EventCode": "0xC2",
  832. "Counter": "0,1,2,3",
  833. "UMask": "0x1",
  834. "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
  835. "SampleAfterValue": "2000000",
  836. "BriefDescription": "Cycles Uops are being retired",
  837. "CounterMask": "1"
  838. },
  839. {
  840. "PEBS": "1",
  841. "EventCode": "0xC2",
  842. "Counter": "0,1,2,3",
  843. "UMask": "0x1",
  844. "EventName": "UOPS_RETIRED.ANY",
  845. "SampleAfterValue": "2000000",
  846. "BriefDescription": "Uops retired (Precise Event)"
  847. },
  848. {
  849. "PEBS": "1",
  850. "EventCode": "0xC2",
  851. "Counter": "0,1,2,3",
  852. "UMask": "0x4",
  853. "EventName": "UOPS_RETIRED.MACRO_FUSED",
  854. "SampleAfterValue": "2000000",
  855. "BriefDescription": "Macro-fused Uops retired (Precise Event)"
  856. },
  857. {
  858. "PEBS": "1",
  859. "EventCode": "0xC2",
  860. "Counter": "0,1,2,3",
  861. "UMask": "0x2",
  862. "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
  863. "SampleAfterValue": "2000000",
  864. "BriefDescription": "Retirement slots used (Precise Event)"
  865. },
  866. {
  867. "PEBS": "1",
  868. "EventCode": "0xC2",
  869. "Invert": "1",
  870. "Counter": "0,1,2,3",
  871. "UMask": "0x1",
  872. "EventName": "UOPS_RETIRED.STALL_CYCLES",
  873. "SampleAfterValue": "2000000",
  874. "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
  875. "CounterMask": "1"
  876. },
  877. {
  878. "PEBS": "1",
  879. "EventCode": "0xC2",
  880. "Invert": "1",
  881. "Counter": "0,1,2,3",
  882. "UMask": "0x1",
  883. "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
  884. "SampleAfterValue": "2000000",
  885. "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
  886. "CounterMask": "16"
  887. },
  888. {
  889. "PEBS": "2",
  890. "EventCode": "0xC0",
  891. "Invert": "1",
  892. "Counter": "0,1,2,3",
  893. "UMask": "0x1",
  894. "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
  895. "SampleAfterValue": "2000000",
  896. "BriefDescription": "Total cycles (Precise Event)",
  897. "CounterMask": "16"
  898. }
  899. ]