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fsl_serdes.h

fsl_serdes.h 2.4 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * Copyright 2010 Freescale Semiconductor, Inc.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef __FSL_SERDES_H
    7. 

  7. #define __FSL_SERDES_H
    8. 

  8. 

  9. #include <config.h>
    10. 

  10. 

  11. enum srds_prtcl {
    12. 

  12. 	/*
    13. 

  13. 	 * Nobody will check whether the device 'NONE' has been configured,
    14. 

  14. 	 * So use it to indicate if the serdes_prtcl_map has been initialized.
    15. 

  15. 	 */
    16. 

  16. 	NONE = 0,
    17. 

  17. 	PCIE1,
    18. 

  18. 	PCIE2,
    19. 

  19. 	PCIE3,
    20. 

  20. 	PCIE4,
    21. 

  21. 	SATA1,
    22. 

  22. 	SATA2,
    23. 

  23. 	SRIO1,
    24. 

  24. 	SRIO2,
    25. 

  25. 	SGMII_FM1_DTSEC1,
    26. 

  26. 	SGMII_FM1_DTSEC2,
    27. 

  27. 	SGMII_FM1_DTSEC3,
    28. 

  28. 	SGMII_FM1_DTSEC4,
    29. 

  29. 	SGMII_FM1_DTSEC5,
    30. 

  30. 	SGMII_FM1_DTSEC6,
    31. 

  31. 	SGMII_FM1_DTSEC9,
    32. 

  32. 	SGMII_FM1_DTSEC10,
    33. 

  33. 	SGMII_FM2_DTSEC1,
    34. 

  34. 	SGMII_FM2_DTSEC2,
    35. 

  35. 	SGMII_FM2_DTSEC3,
    36. 

  36. 	SGMII_FM2_DTSEC4,
    37. 

  37. 	SGMII_FM2_DTSEC5,
    38. 

  38. 	SGMII_FM2_DTSEC6,
    39. 

  39. 	SGMII_FM2_DTSEC9,
    40. 

  40. 	SGMII_FM2_DTSEC10,
    41. 

  41. 	SGMII_TSEC1,
    42. 

  42. 	SGMII_TSEC2,
    43. 

  43. 	SGMII_TSEC3,
    44. 

  44. 	SGMII_TSEC4,
    45. 

  45. 	XAUI_FM1,
    46. 

  46. 	XAUI_FM2,
    47. 

  47. 	AURORA,
    48. 

  48. 	CPRI1,
    49. 

  49. 	CPRI2,
    50. 

  50. 	CPRI3,
    51. 

  51. 	CPRI4,
    52. 

  52. 	CPRI5,
    53. 

  53. 	CPRI6,
    54. 

  54. 	CPRI7,
    55. 

  55. 	CPRI8,
    56. 

  56. 	XAUI_FM1_MAC9,
    57. 

  57. 	XAUI_FM1_MAC10,
    58. 

  58. 	XAUI_FM2_MAC9,
    59. 

  59. 	XAUI_FM2_MAC10,
    60. 

  60. 	HIGIG_FM1_MAC9,
    61. 

  61. 	HIGIG_FM1_MAC10,
    62. 

  62. 	HIGIG_FM2_MAC9,
    63. 

  63. 	HIGIG_FM2_MAC10,
    64. 

  64. 	QSGMII_FM1_A,		/* A indicates MACs 1-4 */
    65. 

  65. 	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
    66. 

  66. 	QSGMII_FM2_A,
    67. 

  67. 	QSGMII_FM2_B,
    68. 

  68. 	XFI_FM1_MAC1,
    69. 

  69. 	XFI_FM1_MAC2,
    70. 

  70. 	XFI_FM1_MAC9,
    71. 

  71. 	XFI_FM1_MAC10,
    72. 

  72. 	XFI_FM2_MAC9,
    73. 

  73. 	XFI_FM2_MAC10,
    74. 

  74. 	INTERLAKEN,
    75. 

  75. 	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
    76. 

  76. 	QSGMII_SW1_B,
    77. 

  77. 	SGMII_2500_FM1_DTSEC1,
    78. 

  78. 	SGMII_2500_FM1_DTSEC2,
    79. 

  79. 	SGMII_2500_FM1_DTSEC3,
    80. 

  80. 	SGMII_2500_FM1_DTSEC4,
    81. 

  81. 	SGMII_2500_FM1_DTSEC5,
    82. 

  82. 	SGMII_2500_FM1_DTSEC6,
    83. 

  83. 	SGMII_2500_FM1_DTSEC9,
    84. 

  84. 	SGMII_2500_FM1_DTSEC10,
    85. 

  85. 	SGMII_2500_FM2_DTSEC1,
    86. 

  86. 	SGMII_2500_FM2_DTSEC2,
    87. 

  87. 	SGMII_2500_FM2_DTSEC3,
    88. 

  88. 	SGMII_2500_FM2_DTSEC4,
    89. 

  89. 	SGMII_2500_FM2_DTSEC5,
    90. 

  90. 	SGMII_2500_FM2_DTSEC6,
    91. 

  91. 	SGMII_2500_FM2_DTSEC9,
    92. 

  92. 	SGMII_2500_FM2_DTSEC10,
    93. 

  93. 	SGMII_SW1_MAC1,
    94. 

  94. 	SGMII_SW1_MAC2,
    95. 

  95. 	SGMII_SW1_MAC3,
    96. 

  96. 	SGMII_SW1_MAC4,
    97. 

  97. 	SGMII_SW1_MAC5,
    98. 

  98. 	SGMII_SW1_MAC6,
    99. 

  99. 	SERDES_PRCTL_COUNT	/* Keep this item the last one */
    100. 

  100. };
    101. 

  101. 

  102. enum srds {
    103. 

  103. 	FSL_SRDS_1  = 0,
    104. 

  104. 	FSL_SRDS_2  = 1,
    105. 

  105. 	FSL_SRDS_3  = 2,
    106. 

  106. 	FSL_SRDS_4  = 3,
    107. 

  107. };
    108. 

  108. 

  109. int is_serdes_configured(enum srds_prtcl device);
    110. 

  110. void fsl_serdes_init(void);
    111. 

  111. const char *serdes_clock_to_string(u32 clock);
    112. 

  112. 

  113. #ifdef CONFIG_FSL_CORENET
    114. 

  114. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
    115. 

  115. int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
    116. 

  116. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
    117. 

  117. #else
    118. 

  118. int serdes_get_first_lane(enum srds_prtcl device);
    119. 

  119. #endif
    120. 

  120. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
    121. 

  121. void serdes_reset_rx(enum srds_prtcl device);
    122. 

  122. #endif
    123. 

  123. #endif
    124. 

  124. 

  125. #endif /* __FSL_SERDES_H */
    126.