ark1668_hardware.h 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. /*
  2. * linux/arch/arm/mach-ark1680/include/mach/hardware.h
  3. *
  4. * Copyright(c) 2012 Hong Kong Applied Science and Technology
  5. * Research Institute Company Limited (ASTRI)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version 2
  10. * of the License, or (at your option) any later version.
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  19. * MA 02110-1301, USA.
  20. *
  21. * Name:
  22. * hardware.h
  23. *
  24. * Description:
  25. *
  26. *
  27. * Author:
  28. * Jack Tang
  29. *
  30. * Remarks:
  31. *
  32. */
  33. #ifndef _ASM_ARCH_HARDWARE_H_
  34. #define _ASM_ARCH_HARDWARE_H_
  35. /* ============================================================================
  36. * System Memory Base
  37. * ============================================================================
  38. */
  39. #define IROM_BASE 0x00000000
  40. #define IRAM_BASE 0xc0000000
  41. #define DDRII_MEM_BASE 0x00000000
  42. #define NAND_BASE 0xEC000000
  43. #define SDHC0_BASE 0xEC400000
  44. #define SDHC1_BASE 0xEC800000 //SD0
  45. //#define SDHC1_BASE 0xE800000 //SD1
  46. #define SDHC2_BASE 0xECC00000
  47. #define DDR_DATA_BASE 0x20000000
  48. #define DDR_BASE_ADDR DDRII_BASE
  49. #define DMA_BASE 0xE0000000
  50. #define USB_BASE 0xE0100000
  51. #define JPEG_BASE 0xE0200000
  52. #define TSDEMUX_BASE 0xE0300000
  53. #define USB1_BASE 0xE0400000
  54. #define LCD_BASE 0xE0500000
  55. #define POST_SCALER_BASE 0xE0600000
  56. #define PRE_SCALER_BASE 0xE0700000
  57. #define ITU656_BASE 0xE0800000
  58. #define MFC_BASE 0xE0900000
  59. #define DDRII_BASE 0xE0A00000
  60. #define VICH_BASE 0xE0B00000
  61. #define VICL_BASE 0xE0C00000
  62. #define DEINTERLACE_BASE 0xE0D00000
  63. #define M2MDMA_BASE 0xE0E00000 /* V2D */
  64. #define GPU_BASE 0xE0F00000 /* D3D */
  65. #define I2S_BASE 0xE4000000
  66. #define SSI_BASE 0xE4100000
  67. #define UART0_BASE 0xE4200000
  68. #define IIC_BASE 0xE4300000
  69. #define RPC_BASE 0xE4400000
  70. #define ADC_BASE 0xE4500000
  71. #define GPIO_BASE 0xE4600000
  72. #define RC_BASE 0xE4700000
  73. #define UART5_BASE 0xE4800000
  74. #define SYS_BASE 0xE4900000
  75. #define TIMER_BASE 0xE4A00000
  76. #define WDT_BASE 0xE4B00000
  77. #define RTC_BASE 0xE4C00000
  78. #define PWM_BASE 0xE4D00000
  79. #define UART1_BASE 0xE4E00000
  80. #define UART4_BASE 0xE4F00000
  81. #define UART2_BASE 0xE8000000
  82. #define UART3_BASE 0xE8100000
  83. #define ITU656IN_BASE ITU656_BASE
  84. #endif /* _ASM_ARCH_HARDWARE_H_ */