i2c-efm32.c 12 KB

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  1. /*
  2. * Copyright (C) 2014 Uwe Kleine-Koenig for Pengutronix
  3. *
  4. * This program is free software; you can redistribute it and/or modify it under
  5. * the terms of the GNU General Public License version 2 as published by the
  6. * Free Software Foundation.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/err.h>
  14. #include <linux/clk.h>
  15. #define DRIVER_NAME "efm32-i2c"
  16. #define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
  17. #define REG_CTRL 0x00
  18. #define REG_CTRL_EN 0x00001
  19. #define REG_CTRL_SLAVE 0x00002
  20. #define REG_CTRL_AUTOACK 0x00004
  21. #define REG_CTRL_AUTOSE 0x00008
  22. #define REG_CTRL_AUTOSN 0x00010
  23. #define REG_CTRL_ARBDIS 0x00020
  24. #define REG_CTRL_GCAMEN 0x00040
  25. #define REG_CTRL_CLHR__MASK 0x00300
  26. #define REG_CTRL_BITO__MASK 0x03000
  27. #define REG_CTRL_BITO_OFF 0x00000
  28. #define REG_CTRL_BITO_40PCC 0x01000
  29. #define REG_CTRL_BITO_80PCC 0x02000
  30. #define REG_CTRL_BITO_160PCC 0x03000
  31. #define REG_CTRL_GIBITO 0x08000
  32. #define REG_CTRL_CLTO__MASK 0x70000
  33. #define REG_CTRL_CLTO_OFF 0x00000
  34. #define REG_CMD 0x04
  35. #define REG_CMD_START 0x00001
  36. #define REG_CMD_STOP 0x00002
  37. #define REG_CMD_ACK 0x00004
  38. #define REG_CMD_NACK 0x00008
  39. #define REG_CMD_CONT 0x00010
  40. #define REG_CMD_ABORT 0x00020
  41. #define REG_CMD_CLEARTX 0x00040
  42. #define REG_CMD_CLEARPC 0x00080
  43. #define REG_STATE 0x08
  44. #define REG_STATE_BUSY 0x00001
  45. #define REG_STATE_MASTER 0x00002
  46. #define REG_STATE_TRANSMITTER 0x00004
  47. #define REG_STATE_NACKED 0x00008
  48. #define REG_STATE_BUSHOLD 0x00010
  49. #define REG_STATE_STATE__MASK 0x000e0
  50. #define REG_STATE_STATE_IDLE 0x00000
  51. #define REG_STATE_STATE_WAIT 0x00020
  52. #define REG_STATE_STATE_START 0x00040
  53. #define REG_STATE_STATE_ADDR 0x00060
  54. #define REG_STATE_STATE_ADDRACK 0x00080
  55. #define REG_STATE_STATE_DATA 0x000a0
  56. #define REG_STATE_STATE_DATAACK 0x000c0
  57. #define REG_STATUS 0x0c
  58. #define REG_STATUS_PSTART 0x00001
  59. #define REG_STATUS_PSTOP 0x00002
  60. #define REG_STATUS_PACK 0x00004
  61. #define REG_STATUS_PNACK 0x00008
  62. #define REG_STATUS_PCONT 0x00010
  63. #define REG_STATUS_PABORT 0x00020
  64. #define REG_STATUS_TXC 0x00040
  65. #define REG_STATUS_TXBL 0x00080
  66. #define REG_STATUS_RXDATAV 0x00100
  67. #define REG_CLKDIV 0x10
  68. #define REG_CLKDIV_DIV__MASK 0x001ff
  69. #define REG_CLKDIV_DIV(div) MASK_VAL(REG_CLKDIV_DIV__MASK, (div))
  70. #define REG_SADDR 0x14
  71. #define REG_SADDRMASK 0x18
  72. #define REG_RXDATA 0x1c
  73. #define REG_RXDATAP 0x20
  74. #define REG_TXDATA 0x24
  75. #define REG_IF 0x28
  76. #define REG_IF_START 0x00001
  77. #define REG_IF_RSTART 0x00002
  78. #define REG_IF_ADDR 0x00004
  79. #define REG_IF_TXC 0x00008
  80. #define REG_IF_TXBL 0x00010
  81. #define REG_IF_RXDATAV 0x00020
  82. #define REG_IF_ACK 0x00040
  83. #define REG_IF_NACK 0x00080
  84. #define REG_IF_MSTOP 0x00100
  85. #define REG_IF_ARBLOST 0x00200
  86. #define REG_IF_BUSERR 0x00400
  87. #define REG_IF_BUSHOLD 0x00800
  88. #define REG_IF_TXOF 0x01000
  89. #define REG_IF_RXUF 0x02000
  90. #define REG_IF_BITO 0x04000
  91. #define REG_IF_CLTO 0x08000
  92. #define REG_IF_SSTOP 0x10000
  93. #define REG_IFS 0x2c
  94. #define REG_IFC 0x30
  95. #define REG_IFC__MASK 0x1ffcf
  96. #define REG_IEN 0x34
  97. #define REG_ROUTE 0x38
  98. #define REG_ROUTE_SDAPEN 0x00001
  99. #define REG_ROUTE_SCLPEN 0x00002
  100. #define REG_ROUTE_LOCATION__MASK 0x00700
  101. #define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
  102. struct efm32_i2c_ddata {
  103. struct i2c_adapter adapter;
  104. struct clk *clk;
  105. void __iomem *base;
  106. unsigned int irq;
  107. u8 location;
  108. unsigned long frequency;
  109. /* transfer data */
  110. struct completion done;
  111. struct i2c_msg *msgs;
  112. size_t num_msgs;
  113. size_t current_word, current_msg;
  114. int retval;
  115. };
  116. static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset)
  117. {
  118. return readl(ddata->base + offset);
  119. }
  120. static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata,
  121. unsigned offset, u32 value)
  122. {
  123. writel(value, ddata->base + offset);
  124. }
  125. static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata)
  126. {
  127. struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
  128. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_START);
  129. efm32_i2c_write32(ddata, REG_TXDATA, i2c_8bit_addr_from_msg(cur_msg));
  130. }
  131. static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata)
  132. {
  133. struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
  134. if (ddata->current_word >= cur_msg->len) {
  135. /* cur_msg completely transferred */
  136. ddata->current_word = 0;
  137. ddata->current_msg += 1;
  138. if (ddata->current_msg >= ddata->num_msgs) {
  139. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
  140. complete(&ddata->done);
  141. } else {
  142. efm32_i2c_send_next_msg(ddata);
  143. }
  144. } else {
  145. efm32_i2c_write32(ddata, REG_TXDATA,
  146. cur_msg->buf[ddata->current_word++]);
  147. }
  148. }
  149. static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata)
  150. {
  151. struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
  152. cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, REG_RXDATA);
  153. ddata->current_word += 1;
  154. if (ddata->current_word >= cur_msg->len) {
  155. /* cur_msg completely transferred */
  156. ddata->current_word = 0;
  157. ddata->current_msg += 1;
  158. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_NACK);
  159. if (ddata->current_msg >= ddata->num_msgs) {
  160. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
  161. complete(&ddata->done);
  162. } else {
  163. efm32_i2c_send_next_msg(ddata);
  164. }
  165. } else {
  166. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ACK);
  167. }
  168. }
  169. static irqreturn_t efm32_i2c_irq(int irq, void *dev_id)
  170. {
  171. struct efm32_i2c_ddata *ddata = dev_id;
  172. struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
  173. u32 irqflag = efm32_i2c_read32(ddata, REG_IF);
  174. u32 state = efm32_i2c_read32(ddata, REG_STATE);
  175. efm32_i2c_write32(ddata, REG_IFC, irqflag & REG_IFC__MASK);
  176. switch (state & REG_STATE_STATE__MASK) {
  177. case REG_STATE_STATE_IDLE:
  178. /* arbitration lost? */
  179. ddata->retval = -EAGAIN;
  180. complete(&ddata->done);
  181. break;
  182. case REG_STATE_STATE_WAIT:
  183. /*
  184. * huh, this shouldn't happen.
  185. * Reset hardware state and get out
  186. */
  187. ddata->retval = -EIO;
  188. efm32_i2c_write32(ddata, REG_CMD,
  189. REG_CMD_STOP | REG_CMD_ABORT |
  190. REG_CMD_CLEARTX | REG_CMD_CLEARPC);
  191. complete(&ddata->done);
  192. break;
  193. case REG_STATE_STATE_START:
  194. /* "caller" is expected to send an address */
  195. break;
  196. case REG_STATE_STATE_ADDR:
  197. /* wait for Ack or NAck of slave */
  198. break;
  199. case REG_STATE_STATE_ADDRACK:
  200. if (state & REG_STATE_NACKED) {
  201. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
  202. ddata->retval = -ENXIO;
  203. complete(&ddata->done);
  204. } else if (cur_msg->flags & I2C_M_RD) {
  205. /* wait for slave to send first data byte */
  206. } else {
  207. efm32_i2c_send_next_byte(ddata);
  208. }
  209. break;
  210. case REG_STATE_STATE_DATA:
  211. if (cur_msg->flags & I2C_M_RD) {
  212. efm32_i2c_recv_next_byte(ddata);
  213. } else {
  214. /* wait for Ack or Nack of slave */
  215. }
  216. break;
  217. case REG_STATE_STATE_DATAACK:
  218. if (state & REG_STATE_NACKED) {
  219. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
  220. complete(&ddata->done);
  221. } else {
  222. efm32_i2c_send_next_byte(ddata);
  223. }
  224. }
  225. return IRQ_HANDLED;
  226. }
  227. static int efm32_i2c_master_xfer(struct i2c_adapter *adap,
  228. struct i2c_msg *msgs, int num)
  229. {
  230. struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap);
  231. int ret;
  232. if (ddata->msgs)
  233. return -EBUSY;
  234. ddata->msgs = msgs;
  235. ddata->num_msgs = num;
  236. ddata->current_word = 0;
  237. ddata->current_msg = 0;
  238. ddata->retval = -EIO;
  239. reinit_completion(&ddata->done);
  240. dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x\n",
  241. efm32_i2c_read32(ddata, REG_STATE),
  242. efm32_i2c_read32(ddata, REG_STATUS));
  243. efm32_i2c_send_next_msg(ddata);
  244. wait_for_completion(&ddata->done);
  245. if (ddata->current_msg >= ddata->num_msgs)
  246. ret = ddata->num_msgs;
  247. else
  248. ret = ddata->retval;
  249. return ret;
  250. }
  251. static u32 efm32_i2c_functionality(struct i2c_adapter *adap)
  252. {
  253. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  254. }
  255. static const struct i2c_algorithm efm32_i2c_algo = {
  256. .master_xfer = efm32_i2c_master_xfer,
  257. .functionality = efm32_i2c_functionality,
  258. };
  259. static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata)
  260. {
  261. u32 reg = efm32_i2c_read32(ddata, REG_ROUTE);
  262. return (reg & REG_ROUTE_LOCATION__MASK) >>
  263. __ffs(REG_ROUTE_LOCATION__MASK);
  264. }
  265. static int efm32_i2c_probe(struct platform_device *pdev)
  266. {
  267. struct efm32_i2c_ddata *ddata;
  268. struct resource *res;
  269. unsigned long rate;
  270. struct device_node *np = pdev->dev.of_node;
  271. u32 location, frequency;
  272. int ret;
  273. u32 clkdiv;
  274. if (!np)
  275. return -EINVAL;
  276. ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
  277. if (!ddata)
  278. return -ENOMEM;
  279. platform_set_drvdata(pdev, ddata);
  280. init_completion(&ddata->done);
  281. strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name));
  282. ddata->adapter.owner = THIS_MODULE;
  283. ddata->adapter.algo = &efm32_i2c_algo;
  284. ddata->adapter.dev.parent = &pdev->dev;
  285. ddata->adapter.dev.of_node = pdev->dev.of_node;
  286. i2c_set_adapdata(&ddata->adapter, ddata);
  287. ddata->clk = devm_clk_get(&pdev->dev, NULL);
  288. if (IS_ERR(ddata->clk)) {
  289. ret = PTR_ERR(ddata->clk);
  290. dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
  291. return ret;
  292. }
  293. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  294. if (!res) {
  295. dev_err(&pdev->dev, "failed to determine base address\n");
  296. return -ENODEV;
  297. }
  298. if (resource_size(res) < 0x42) {
  299. dev_err(&pdev->dev, "memory resource too small\n");
  300. return -EINVAL;
  301. }
  302. ddata->base = devm_ioremap_resource(&pdev->dev, res);
  303. if (IS_ERR(ddata->base))
  304. return PTR_ERR(ddata->base);
  305. ret = platform_get_irq(pdev, 0);
  306. if (ret <= 0) {
  307. dev_err(&pdev->dev, "failed to get irq (%d)\n", ret);
  308. if (!ret)
  309. ret = -EINVAL;
  310. return ret;
  311. }
  312. ddata->irq = ret;
  313. ret = clk_prepare_enable(ddata->clk);
  314. if (ret < 0) {
  315. dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
  316. return ret;
  317. }
  318. ret = of_property_read_u32(np, "energymicro,location", &location);
  319. if (ret)
  320. /* fall back to wrongly namespaced property */
  321. ret = of_property_read_u32(np, "efm32,location", &location);
  322. if (!ret) {
  323. dev_dbg(&pdev->dev, "using location %u\n", location);
  324. } else {
  325. /* default to location configured in hardware */
  326. location = efm32_i2c_get_configured_location(ddata);
  327. dev_info(&pdev->dev, "fall back to location %u\n", location);
  328. }
  329. ddata->location = location;
  330. ret = of_property_read_u32(np, "clock-frequency", &frequency);
  331. if (!ret) {
  332. dev_dbg(&pdev->dev, "using frequency %u\n", frequency);
  333. } else {
  334. frequency = 100000;
  335. dev_info(&pdev->dev, "defaulting to 100 kHz\n");
  336. }
  337. ddata->frequency = frequency;
  338. rate = clk_get_rate(ddata->clk);
  339. if (!rate) {
  340. dev_err(&pdev->dev, "there is no input clock available\n");
  341. ret = -EINVAL;
  342. goto err_disable_clk;
  343. }
  344. clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1;
  345. if (clkdiv >= 0x200) {
  346. dev_err(&pdev->dev,
  347. "input clock too fast (%lu) to divide down to bus freq (%lu)",
  348. rate, ddata->frequency);
  349. ret = -EINVAL;
  350. goto err_disable_clk;
  351. }
  352. dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu\n",
  353. rate, ddata->frequency, (unsigned long)clkdiv);
  354. efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv));
  355. efm32_i2c_write32(ddata, REG_ROUTE, REG_ROUTE_SDAPEN |
  356. REG_ROUTE_SCLPEN |
  357. REG_ROUTE_LOCATION(ddata->location));
  358. efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN |
  359. REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO);
  360. efm32_i2c_write32(ddata, REG_IFC, REG_IFC__MASK);
  361. efm32_i2c_write32(ddata, REG_IEN, REG_IF_TXC | REG_IF_ACK | REG_IF_NACK
  362. | REG_IF_ARBLOST | REG_IF_BUSERR | REG_IF_RXDATAV);
  363. /* to make bus idle */
  364. efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ABORT);
  365. ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata);
  366. if (ret < 0) {
  367. dev_err(&pdev->dev, "failed to request irq (%d)\n", ret);
  368. goto err_disable_clk;
  369. }
  370. ret = i2c_add_adapter(&ddata->adapter);
  371. if (ret) {
  372. free_irq(ddata->irq, ddata);
  373. err_disable_clk:
  374. clk_disable_unprepare(ddata->clk);
  375. }
  376. return ret;
  377. }
  378. static int efm32_i2c_remove(struct platform_device *pdev)
  379. {
  380. struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev);
  381. i2c_del_adapter(&ddata->adapter);
  382. free_irq(ddata->irq, ddata);
  383. clk_disable_unprepare(ddata->clk);
  384. return 0;
  385. }
  386. static const struct of_device_id efm32_i2c_dt_ids[] = {
  387. {
  388. .compatible = "energymicro,efm32-i2c",
  389. }, {
  390. /* sentinel */
  391. }
  392. };
  393. MODULE_DEVICE_TABLE(of, efm32_i2c_dt_ids);
  394. static struct platform_driver efm32_i2c_driver = {
  395. .probe = efm32_i2c_probe,
  396. .remove = efm32_i2c_remove,
  397. .driver = {
  398. .name = DRIVER_NAME,
  399. .of_match_table = efm32_i2c_dt_ids,
  400. },
  401. };
  402. module_platform_driver(efm32_i2c_driver);
  403. MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
  404. MODULE_DESCRIPTION("EFM32 i2c driver");
  405. MODULE_LICENSE("GPL v2");
  406. MODULE_ALIAS("platform:" DRIVER_NAME);