i2c-thunderx-pcidrv.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259
  1. /*
  2. * Cavium ThunderX i2c driver.
  3. *
  4. * Copyright (C) 2015,2016 Cavium Inc.
  5. * Authors: Fred Martin <fmartin@caviumnetworks.com>
  6. * Jan Glauber <jglauber@cavium.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/acpi.h>
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/i2c.h>
  16. #include <linux/i2c-smbus.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/pci.h>
  22. #include "i2c-octeon-core.h"
  23. #define DRV_NAME "i2c-thunderx"
  24. #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012
  25. #define SYS_FREQ_DEFAULT 700000000
  26. #define TWSI_INT_ENA_W1C 0x1028
  27. #define TWSI_INT_ENA_W1S 0x1030
  28. /*
  29. * Enable the CORE interrupt.
  30. * The interrupt will be asserted when there is non-STAT_IDLE state in the
  31. * SW_TWSI_EOP_TWSI_STAT register.
  32. */
  33. static void thunder_i2c_int_enable(struct octeon_i2c *i2c)
  34. {
  35. octeon_i2c_writeq_flush(TWSI_INT_CORE_INT,
  36. i2c->twsi_base + TWSI_INT_ENA_W1S);
  37. }
  38. /*
  39. * Disable the CORE interrupt.
  40. */
  41. static void thunder_i2c_int_disable(struct octeon_i2c *i2c)
  42. {
  43. octeon_i2c_writeq_flush(TWSI_INT_CORE_INT,
  44. i2c->twsi_base + TWSI_INT_ENA_W1C);
  45. }
  46. static void thunder_i2c_hlc_int_enable(struct octeon_i2c *i2c)
  47. {
  48. octeon_i2c_writeq_flush(TWSI_INT_ST_INT | TWSI_INT_TS_INT,
  49. i2c->twsi_base + TWSI_INT_ENA_W1S);
  50. }
  51. static void thunder_i2c_hlc_int_disable(struct octeon_i2c *i2c)
  52. {
  53. octeon_i2c_writeq_flush(TWSI_INT_ST_INT | TWSI_INT_TS_INT,
  54. i2c->twsi_base + TWSI_INT_ENA_W1C);
  55. }
  56. static u32 thunderx_i2c_functionality(struct i2c_adapter *adap)
  57. {
  58. return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
  59. I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
  60. }
  61. static const struct i2c_algorithm thunderx_i2c_algo = {
  62. .master_xfer = octeon_i2c_xfer,
  63. .functionality = thunderx_i2c_functionality,
  64. };
  65. static const struct i2c_adapter thunderx_i2c_ops = {
  66. .owner = THIS_MODULE,
  67. .name = "ThunderX adapter",
  68. .algo = &thunderx_i2c_algo,
  69. };
  70. static void thunder_i2c_clock_enable(struct device *dev, struct octeon_i2c *i2c)
  71. {
  72. int ret;
  73. if (acpi_disabled) {
  74. /* DT */
  75. i2c->clk = clk_get(dev, NULL);
  76. if (IS_ERR(i2c->clk)) {
  77. i2c->clk = NULL;
  78. goto skip;
  79. }
  80. ret = clk_prepare_enable(i2c->clk);
  81. if (ret)
  82. goto skip;
  83. i2c->sys_freq = clk_get_rate(i2c->clk);
  84. } else {
  85. /* ACPI */
  86. device_property_read_u32(dev, "sclk", &i2c->sys_freq);
  87. }
  88. skip:
  89. if (!i2c->sys_freq)
  90. i2c->sys_freq = SYS_FREQ_DEFAULT;
  91. }
  92. static void thunder_i2c_clock_disable(struct device *dev, struct clk *clk)
  93. {
  94. if (!clk)
  95. return;
  96. clk_disable_unprepare(clk);
  97. clk_put(clk);
  98. }
  99. static int thunder_i2c_smbus_setup_of(struct octeon_i2c *i2c,
  100. struct device_node *node)
  101. {
  102. if (!node)
  103. return -EINVAL;
  104. i2c->alert_data.irq = irq_of_parse_and_map(node, 0);
  105. if (!i2c->alert_data.irq)
  106. return -EINVAL;
  107. i2c->ara = i2c_setup_smbus_alert(&i2c->adap, &i2c->alert_data);
  108. if (!i2c->ara)
  109. return -ENODEV;
  110. return 0;
  111. }
  112. static int thunder_i2c_smbus_setup(struct octeon_i2c *i2c,
  113. struct device_node *node)
  114. {
  115. /* TODO: ACPI support */
  116. if (!acpi_disabled)
  117. return -EOPNOTSUPP;
  118. return thunder_i2c_smbus_setup_of(i2c, node);
  119. }
  120. static void thunder_i2c_smbus_remove(struct octeon_i2c *i2c)
  121. {
  122. i2c_unregister_device(i2c->ara);
  123. }
  124. static int thunder_i2c_probe_pci(struct pci_dev *pdev,
  125. const struct pci_device_id *ent)
  126. {
  127. struct device *dev = &pdev->dev;
  128. struct octeon_i2c *i2c;
  129. int ret;
  130. i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
  131. if (!i2c)
  132. return -ENOMEM;
  133. i2c->roff.sw_twsi = 0x1000;
  134. i2c->roff.twsi_int = 0x1010;
  135. i2c->roff.sw_twsi_ext = 0x1018;
  136. i2c->dev = dev;
  137. pci_set_drvdata(pdev, i2c);
  138. ret = pcim_enable_device(pdev);
  139. if (ret)
  140. return ret;
  141. ret = pci_request_regions(pdev, DRV_NAME);
  142. if (ret)
  143. return ret;
  144. i2c->twsi_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
  145. if (!i2c->twsi_base)
  146. return -EINVAL;
  147. thunder_i2c_clock_enable(dev, i2c);
  148. ret = device_property_read_u32(dev, "clock-frequency", &i2c->twsi_freq);
  149. if (ret)
  150. i2c->twsi_freq = 100000;
  151. init_waitqueue_head(&i2c->queue);
  152. i2c->int_enable = thunder_i2c_int_enable;
  153. i2c->int_disable = thunder_i2c_int_disable;
  154. i2c->hlc_int_enable = thunder_i2c_hlc_int_enable;
  155. i2c->hlc_int_disable = thunder_i2c_hlc_int_disable;
  156. ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
  157. if (ret < 0)
  158. goto error;
  159. ret = devm_request_irq(dev, pci_irq_vector(pdev, 0), octeon_i2c_isr, 0,
  160. DRV_NAME, i2c);
  161. if (ret)
  162. goto error;
  163. ret = octeon_i2c_init_lowlevel(i2c);
  164. if (ret)
  165. goto error;
  166. octeon_i2c_set_clock(i2c);
  167. i2c->adap = thunderx_i2c_ops;
  168. i2c->adap.retries = 5;
  169. i2c->adap.class = I2C_CLASS_HWMON;
  170. i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
  171. i2c->adap.dev.parent = dev;
  172. i2c->adap.dev.of_node = pdev->dev.of_node;
  173. snprintf(i2c->adap.name, sizeof(i2c->adap.name),
  174. "Cavium ThunderX i2c adapter at %s", dev_name(dev));
  175. i2c_set_adapdata(&i2c->adap, i2c);
  176. ret = i2c_add_adapter(&i2c->adap);
  177. if (ret)
  178. goto error;
  179. dev_info(i2c->dev, "Probed. Set system clock to %u\n", i2c->sys_freq);
  180. ret = thunder_i2c_smbus_setup(i2c, pdev->dev.of_node);
  181. if (ret)
  182. dev_info(dev, "SMBUS alert not active on this bus\n");
  183. return 0;
  184. error:
  185. thunder_i2c_clock_disable(dev, i2c->clk);
  186. return ret;
  187. }
  188. static void thunder_i2c_remove_pci(struct pci_dev *pdev)
  189. {
  190. struct octeon_i2c *i2c = pci_get_drvdata(pdev);
  191. thunder_i2c_smbus_remove(i2c);
  192. thunder_i2c_clock_disable(&pdev->dev, i2c->clk);
  193. i2c_del_adapter(&i2c->adap);
  194. }
  195. static const struct pci_device_id thunder_i2c_pci_id_table[] = {
  196. { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_TWSI) },
  197. { 0, }
  198. };
  199. MODULE_DEVICE_TABLE(pci, thunder_i2c_pci_id_table);
  200. static struct pci_driver thunder_i2c_pci_driver = {
  201. .name = DRV_NAME,
  202. .id_table = thunder_i2c_pci_id_table,
  203. .probe = thunder_i2c_probe_pci,
  204. .remove = thunder_i2c_remove_pci,
  205. };
  206. module_pci_driver(thunder_i2c_pci_driver);
  207. MODULE_LICENSE("GPL");
  208. MODULE_AUTHOR("Fred Martin <fmartin@caviumnetworks.com>");
  209. MODULE_DESCRIPTION("I2C-Bus adapter for Cavium ThunderX SOC");