adxl345_core.c 7.5 KB

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  1. /*
  2. * ADXL345 3-Axis Digital Accelerometer IIO core driver
  3. *
  4. * Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com>
  5. *
  6. * This file is subject to the terms and conditions of version 2 of
  7. * the GNU General Public License. See the file COPYING in the main
  8. * directory of this archive for more details.
  9. *
  10. * Datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
  11. */
  12. #include <linux/module.h>
  13. #include <linux/regmap.h>
  14. #include <linux/iio/iio.h>
  15. #include <linux/iio/sysfs.h>
  16. #include "adxl345.h"
  17. #define ADXL345_REG_DEVID 0x00
  18. #define ADXL345_REG_OFSX 0x1e
  19. #define ADXL345_REG_OFSY 0x1f
  20. #define ADXL345_REG_OFSZ 0x20
  21. #define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
  22. #define ADXL345_REG_BW_RATE 0x2C
  23. #define ADXL345_REG_POWER_CTL 0x2D
  24. #define ADXL345_REG_DATA_FORMAT 0x31
  25. #define ADXL345_REG_DATAX0 0x32
  26. #define ADXL345_REG_DATAY0 0x34
  27. #define ADXL345_REG_DATAZ0 0x36
  28. #define ADXL345_REG_DATA_AXIS(index) \
  29. (ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
  30. #define ADXL345_BW_RATE GENMASK(3, 0)
  31. #define ADXL345_BASE_RATE_NANO_HZ 97656250LL
  32. #define NHZ_PER_HZ 1000000000LL
  33. #define ADXL345_POWER_CTL_MEASURE BIT(3)
  34. #define ADXL345_POWER_CTL_STANDBY 0x00
  35. #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */
  36. #define ADXL345_DATA_FORMAT_2G 0
  37. #define ADXL345_DATA_FORMAT_4G 1
  38. #define ADXL345_DATA_FORMAT_8G 2
  39. #define ADXL345_DATA_FORMAT_16G 3
  40. #define ADXL345_DEVID 0xE5
  41. /*
  42. * In full-resolution mode, scale factor is maintained at ~4 mg/LSB
  43. * in all g ranges.
  44. *
  45. * At +/- 16g with 13-bit resolution, scale is computed as:
  46. * (16 + 16) * 9.81 / (2^13 - 1) = 0.0383
  47. */
  48. static const int adxl345_uscale = 38300;
  49. /*
  50. * The Datasheet lists a resolution of Resolution is ~49 mg per LSB. That's
  51. * ~480mm/s**2 per LSB.
  52. */
  53. static const int adxl375_uscale = 480000;
  54. struct adxl345_data {
  55. struct regmap *regmap;
  56. u8 data_range;
  57. enum adxl345_device_type type;
  58. };
  59. #define ADXL345_CHANNEL(index, axis) { \
  60. .type = IIO_ACCEL, \
  61. .modified = 1, \
  62. .channel2 = IIO_MOD_##axis, \
  63. .address = index, \
  64. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  65. BIT(IIO_CHAN_INFO_CALIBBIAS), \
  66. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  67. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  68. }
  69. static const struct iio_chan_spec adxl345_channels[] = {
  70. ADXL345_CHANNEL(0, X),
  71. ADXL345_CHANNEL(1, Y),
  72. ADXL345_CHANNEL(2, Z),
  73. };
  74. static int adxl345_read_raw(struct iio_dev *indio_dev,
  75. struct iio_chan_spec const *chan,
  76. int *val, int *val2, long mask)
  77. {
  78. struct adxl345_data *data = iio_priv(indio_dev);
  79. __le16 accel;
  80. long long samp_freq_nhz;
  81. unsigned int regval;
  82. int ret;
  83. switch (mask) {
  84. case IIO_CHAN_INFO_RAW:
  85. /*
  86. * Data is stored in adjacent registers:
  87. * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
  88. * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
  89. */
  90. ret = regmap_bulk_read(data->regmap,
  91. ADXL345_REG_DATA_AXIS(chan->address),
  92. &accel, sizeof(accel));
  93. if (ret < 0)
  94. return ret;
  95. *val = sign_extend32(le16_to_cpu(accel), 12);
  96. return IIO_VAL_INT;
  97. case IIO_CHAN_INFO_SCALE:
  98. *val = 0;
  99. switch (data->type) {
  100. case ADXL345:
  101. *val2 = adxl345_uscale;
  102. break;
  103. case ADXL375:
  104. *val2 = adxl375_uscale;
  105. break;
  106. }
  107. return IIO_VAL_INT_PLUS_MICRO;
  108. case IIO_CHAN_INFO_CALIBBIAS:
  109. ret = regmap_read(data->regmap,
  110. ADXL345_REG_OFS_AXIS(chan->address), &regval);
  111. if (ret < 0)
  112. return ret;
  113. /*
  114. * 8-bit resolution at +/- 2g, that is 4x accel data scale
  115. * factor
  116. */
  117. *val = sign_extend32(regval, 7) * 4;
  118. return IIO_VAL_INT;
  119. case IIO_CHAN_INFO_SAMP_FREQ:
  120. ret = regmap_read(data->regmap, ADXL345_REG_BW_RATE, &regval);
  121. if (ret < 0)
  122. return ret;
  123. samp_freq_nhz = ADXL345_BASE_RATE_NANO_HZ <<
  124. (regval & ADXL345_BW_RATE);
  125. *val = div_s64_rem(samp_freq_nhz, NHZ_PER_HZ, val2);
  126. return IIO_VAL_INT_PLUS_NANO;
  127. }
  128. return -EINVAL;
  129. }
  130. static int adxl345_write_raw(struct iio_dev *indio_dev,
  131. struct iio_chan_spec const *chan,
  132. int val, int val2, long mask)
  133. {
  134. struct adxl345_data *data = iio_priv(indio_dev);
  135. s64 n;
  136. switch (mask) {
  137. case IIO_CHAN_INFO_CALIBBIAS:
  138. /*
  139. * 8-bit resolution at +/- 2g, that is 4x accel data scale
  140. * factor
  141. */
  142. return regmap_write(data->regmap,
  143. ADXL345_REG_OFS_AXIS(chan->address),
  144. val / 4);
  145. case IIO_CHAN_INFO_SAMP_FREQ:
  146. n = div_s64(val * NHZ_PER_HZ + val2, ADXL345_BASE_RATE_NANO_HZ);
  147. return regmap_update_bits(data->regmap, ADXL345_REG_BW_RATE,
  148. ADXL345_BW_RATE,
  149. clamp_val(ilog2(n), 0,
  150. ADXL345_BW_RATE));
  151. }
  152. return -EINVAL;
  153. }
  154. static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev,
  155. struct iio_chan_spec const *chan,
  156. long mask)
  157. {
  158. switch (mask) {
  159. case IIO_CHAN_INFO_CALIBBIAS:
  160. return IIO_VAL_INT;
  161. case IIO_CHAN_INFO_SAMP_FREQ:
  162. return IIO_VAL_INT_PLUS_NANO;
  163. default:
  164. return -EINVAL;
  165. }
  166. }
  167. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
  168. "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200"
  169. );
  170. static struct attribute *adxl345_attrs[] = {
  171. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  172. NULL,
  173. };
  174. static const struct attribute_group adxl345_attrs_group = {
  175. .attrs = adxl345_attrs,
  176. };
  177. static const struct iio_info adxl345_info = {
  178. .attrs = &adxl345_attrs_group,
  179. .read_raw = adxl345_read_raw,
  180. .write_raw = adxl345_write_raw,
  181. .write_raw_get_fmt = adxl345_write_raw_get_fmt,
  182. };
  183. int adxl345_core_probe(struct device *dev, struct regmap *regmap,
  184. enum adxl345_device_type type, const char *name)
  185. {
  186. struct adxl345_data *data;
  187. struct iio_dev *indio_dev;
  188. u32 regval;
  189. int ret;
  190. ret = regmap_read(regmap, ADXL345_REG_DEVID, &regval);
  191. if (ret < 0) {
  192. dev_err(dev, "Error reading device ID: %d\n", ret);
  193. return ret;
  194. }
  195. if (regval != ADXL345_DEVID) {
  196. dev_err(dev, "Invalid device ID: %x, expected %x\n",
  197. regval, ADXL345_DEVID);
  198. return -ENODEV;
  199. }
  200. indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
  201. if (!indio_dev)
  202. return -ENOMEM;
  203. data = iio_priv(indio_dev);
  204. dev_set_drvdata(dev, indio_dev);
  205. data->regmap = regmap;
  206. data->type = type;
  207. /* Enable full-resolution mode */
  208. data->data_range = ADXL345_DATA_FORMAT_FULL_RES;
  209. ret = regmap_write(data->regmap, ADXL345_REG_DATA_FORMAT,
  210. data->data_range);
  211. if (ret < 0) {
  212. dev_err(dev, "Failed to set data range: %d\n", ret);
  213. return ret;
  214. }
  215. indio_dev->dev.parent = dev;
  216. indio_dev->name = name;
  217. indio_dev->info = &adxl345_info;
  218. indio_dev->modes = INDIO_DIRECT_MODE;
  219. indio_dev->channels = adxl345_channels;
  220. indio_dev->num_channels = ARRAY_SIZE(adxl345_channels);
  221. /* Enable measurement mode */
  222. ret = regmap_write(data->regmap, ADXL345_REG_POWER_CTL,
  223. ADXL345_POWER_CTL_MEASURE);
  224. if (ret < 0) {
  225. dev_err(dev, "Failed to enable measurement mode: %d\n", ret);
  226. return ret;
  227. }
  228. ret = iio_device_register(indio_dev);
  229. if (ret < 0) {
  230. dev_err(dev, "iio_device_register failed: %d\n", ret);
  231. regmap_write(data->regmap, ADXL345_REG_POWER_CTL,
  232. ADXL345_POWER_CTL_STANDBY);
  233. }
  234. return ret;
  235. }
  236. EXPORT_SYMBOL_GPL(adxl345_core_probe);
  237. int adxl345_core_remove(struct device *dev)
  238. {
  239. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  240. struct adxl345_data *data = iio_priv(indio_dev);
  241. iio_device_unregister(indio_dev);
  242. return regmap_write(data->regmap, ADXL345_REG_POWER_CTL,
  243. ADXL345_POWER_CTL_STANDBY);
  244. }
  245. EXPORT_SYMBOL_GPL(adxl345_core_remove);
  246. MODULE_AUTHOR("Eva Rachel Retuya <eraretuya@gmail.com>");
  247. MODULE_DESCRIPTION("ADXL345 3-Axis Digital Accelerometer core driver");
  248. MODULE_LICENSE("GPL v2");