mcp3422.c 10 KB

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  1. /*
  2. * mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family
  3. *
  4. * Copyright (C) 2013, Angelo Compagnucci
  5. * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com>
  6. *
  7. * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf
  8. * http://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf
  9. * http://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf
  10. *
  11. * This driver exports the value of analog input voltage to sysfs, the
  12. * voltage unit is nV.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. */
  19. #include <linux/err.h>
  20. #include <linux/i2c.h>
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/sysfs.h>
  24. #include <linux/of.h>
  25. #include <linux/iio/iio.h>
  26. #include <linux/iio/sysfs.h>
  27. /* Masks */
  28. #define MCP3422_CHANNEL_MASK 0x60
  29. #define MCP3422_PGA_MASK 0x03
  30. #define MCP3422_SRATE_MASK 0x0C
  31. #define MCP3422_SRATE_240 0x0
  32. #define MCP3422_SRATE_60 0x1
  33. #define MCP3422_SRATE_15 0x2
  34. #define MCP3422_SRATE_3 0x3
  35. #define MCP3422_PGA_1 0
  36. #define MCP3422_PGA_2 1
  37. #define MCP3422_PGA_4 2
  38. #define MCP3422_PGA_8 3
  39. #define MCP3422_CONT_SAMPLING 0x10
  40. #define MCP3422_CHANNEL(config) (((config) & MCP3422_CHANNEL_MASK) >> 5)
  41. #define MCP3422_PGA(config) ((config) & MCP3422_PGA_MASK)
  42. #define MCP3422_SAMPLE_RATE(config) (((config) & MCP3422_SRATE_MASK) >> 2)
  43. #define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK)
  44. #define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK)
  45. #define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK)
  46. #define MCP3422_CHAN(_index) \
  47. { \
  48. .type = IIO_VOLTAGE, \
  49. .indexed = 1, \
  50. .channel = _index, \
  51. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
  52. | BIT(IIO_CHAN_INFO_SCALE), \
  53. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  54. }
  55. static const int mcp3422_scales[4][4] = {
  56. { 1000000, 500000, 250000, 125000 },
  57. { 250000, 125000, 62500, 31250 },
  58. { 62500, 31250, 15625, 7812 },
  59. { 15625, 7812, 3906, 1953 } };
  60. /* Constant msleep times for data acquisitions */
  61. static const int mcp3422_read_times[4] = {
  62. [MCP3422_SRATE_240] = 1000 / 240,
  63. [MCP3422_SRATE_60] = 1000 / 60,
  64. [MCP3422_SRATE_15] = 1000 / 15,
  65. [MCP3422_SRATE_3] = 1000 / 3 };
  66. /* sample rates to integer conversion table */
  67. static const int mcp3422_sample_rates[4] = {
  68. [MCP3422_SRATE_240] = 240,
  69. [MCP3422_SRATE_60] = 60,
  70. [MCP3422_SRATE_15] = 15,
  71. [MCP3422_SRATE_3] = 3 };
  72. /* sample rates to sign extension table */
  73. static const int mcp3422_sign_extend[4] = {
  74. [MCP3422_SRATE_240] = 11,
  75. [MCP3422_SRATE_60] = 13,
  76. [MCP3422_SRATE_15] = 15,
  77. [MCP3422_SRATE_3] = 17 };
  78. /* Client data (each client gets its own) */
  79. struct mcp3422 {
  80. struct i2c_client *i2c;
  81. u8 id;
  82. u8 config;
  83. u8 pga[4];
  84. struct mutex lock;
  85. };
  86. static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig)
  87. {
  88. int ret;
  89. ret = i2c_master_send(adc->i2c, &newconfig, 1);
  90. if (ret > 0) {
  91. adc->config = newconfig;
  92. ret = 0;
  93. }
  94. return ret;
  95. }
  96. static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config)
  97. {
  98. int ret = 0;
  99. u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
  100. u8 buf[4] = {0, 0, 0, 0};
  101. u32 temp;
  102. if (sample_rate == MCP3422_SRATE_3) {
  103. ret = i2c_master_recv(adc->i2c, buf, 4);
  104. temp = buf[0] << 16 | buf[1] << 8 | buf[2];
  105. *config = buf[3];
  106. } else {
  107. ret = i2c_master_recv(adc->i2c, buf, 3);
  108. temp = buf[0] << 8 | buf[1];
  109. *config = buf[2];
  110. }
  111. *value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]);
  112. return ret;
  113. }
  114. static int mcp3422_read_channel(struct mcp3422 *adc,
  115. struct iio_chan_spec const *channel, int *value)
  116. {
  117. int ret;
  118. u8 config;
  119. u8 req_channel = channel->channel;
  120. mutex_lock(&adc->lock);
  121. if (req_channel != MCP3422_CHANNEL(adc->config)) {
  122. config = adc->config;
  123. config &= ~MCP3422_CHANNEL_MASK;
  124. config |= MCP3422_CHANNEL_VALUE(req_channel);
  125. config &= ~MCP3422_PGA_MASK;
  126. config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
  127. ret = mcp3422_update_config(adc, config);
  128. if (ret < 0) {
  129. mutex_unlock(&adc->lock);
  130. return ret;
  131. }
  132. msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]);
  133. }
  134. ret = mcp3422_read(adc, value, &config);
  135. mutex_unlock(&adc->lock);
  136. return ret;
  137. }
  138. static int mcp3422_read_raw(struct iio_dev *iio,
  139. struct iio_chan_spec const *channel, int *val1,
  140. int *val2, long mask)
  141. {
  142. struct mcp3422 *adc = iio_priv(iio);
  143. int err;
  144. u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
  145. u8 pga = MCP3422_PGA(adc->config);
  146. switch (mask) {
  147. case IIO_CHAN_INFO_RAW:
  148. err = mcp3422_read_channel(adc, channel, val1);
  149. if (err < 0)
  150. return -EINVAL;
  151. return IIO_VAL_INT;
  152. case IIO_CHAN_INFO_SCALE:
  153. *val1 = 0;
  154. *val2 = mcp3422_scales[sample_rate][pga];
  155. return IIO_VAL_INT_PLUS_NANO;
  156. case IIO_CHAN_INFO_SAMP_FREQ:
  157. *val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)];
  158. return IIO_VAL_INT;
  159. default:
  160. break;
  161. }
  162. return -EINVAL;
  163. }
  164. static int mcp3422_write_raw(struct iio_dev *iio,
  165. struct iio_chan_spec const *channel, int val1,
  166. int val2, long mask)
  167. {
  168. struct mcp3422 *adc = iio_priv(iio);
  169. u8 temp;
  170. u8 config = adc->config;
  171. u8 req_channel = channel->channel;
  172. u8 sample_rate = MCP3422_SAMPLE_RATE(config);
  173. u8 i;
  174. switch (mask) {
  175. case IIO_CHAN_INFO_SCALE:
  176. if (val1 != 0)
  177. return -EINVAL;
  178. for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) {
  179. if (val2 == mcp3422_scales[sample_rate][i]) {
  180. adc->pga[req_channel] = i;
  181. config &= ~MCP3422_CHANNEL_MASK;
  182. config |= MCP3422_CHANNEL_VALUE(req_channel);
  183. config &= ~MCP3422_PGA_MASK;
  184. config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
  185. return mcp3422_update_config(adc, config);
  186. }
  187. }
  188. return -EINVAL;
  189. case IIO_CHAN_INFO_SAMP_FREQ:
  190. switch (val1) {
  191. case 240:
  192. temp = MCP3422_SRATE_240;
  193. break;
  194. case 60:
  195. temp = MCP3422_SRATE_60;
  196. break;
  197. case 15:
  198. temp = MCP3422_SRATE_15;
  199. break;
  200. case 3:
  201. if (adc->id > 4)
  202. return -EINVAL;
  203. temp = MCP3422_SRATE_3;
  204. break;
  205. default:
  206. return -EINVAL;
  207. }
  208. config &= ~MCP3422_CHANNEL_MASK;
  209. config |= MCP3422_CHANNEL_VALUE(req_channel);
  210. config &= ~MCP3422_SRATE_MASK;
  211. config |= MCP3422_SAMPLE_RATE_VALUE(temp);
  212. return mcp3422_update_config(adc, config);
  213. default:
  214. break;
  215. }
  216. return -EINVAL;
  217. }
  218. static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev,
  219. struct iio_chan_spec const *chan, long mask)
  220. {
  221. switch (mask) {
  222. case IIO_CHAN_INFO_SCALE:
  223. return IIO_VAL_INT_PLUS_NANO;
  224. case IIO_CHAN_INFO_SAMP_FREQ:
  225. return IIO_VAL_INT_PLUS_MICRO;
  226. default:
  227. return -EINVAL;
  228. }
  229. }
  230. static ssize_t mcp3422_show_samp_freqs(struct device *dev,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
  234. if (adc->id > 4)
  235. return sprintf(buf, "240 60 15\n");
  236. return sprintf(buf, "240 60 15 3\n");
  237. }
  238. static ssize_t mcp3422_show_scales(struct device *dev,
  239. struct device_attribute *attr, char *buf)
  240. {
  241. struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
  242. u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
  243. return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n",
  244. mcp3422_scales[sample_rate][0],
  245. mcp3422_scales[sample_rate][1],
  246. mcp3422_scales[sample_rate][2],
  247. mcp3422_scales[sample_rate][3]);
  248. }
  249. static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO,
  250. mcp3422_show_samp_freqs, NULL, 0);
  251. static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
  252. mcp3422_show_scales, NULL, 0);
  253. static struct attribute *mcp3422_attributes[] = {
  254. &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
  255. &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
  256. NULL,
  257. };
  258. static const struct attribute_group mcp3422_attribute_group = {
  259. .attrs = mcp3422_attributes,
  260. };
  261. static const struct iio_chan_spec mcp3421_channels[] = {
  262. MCP3422_CHAN(0),
  263. };
  264. static const struct iio_chan_spec mcp3422_channels[] = {
  265. MCP3422_CHAN(0),
  266. MCP3422_CHAN(1),
  267. };
  268. static const struct iio_chan_spec mcp3424_channels[] = {
  269. MCP3422_CHAN(0),
  270. MCP3422_CHAN(1),
  271. MCP3422_CHAN(2),
  272. MCP3422_CHAN(3),
  273. };
  274. static const struct iio_info mcp3422_info = {
  275. .read_raw = mcp3422_read_raw,
  276. .write_raw = mcp3422_write_raw,
  277. .write_raw_get_fmt = mcp3422_write_raw_get_fmt,
  278. .attrs = &mcp3422_attribute_group,
  279. };
  280. static int mcp3422_probe(struct i2c_client *client,
  281. const struct i2c_device_id *id)
  282. {
  283. struct iio_dev *indio_dev;
  284. struct mcp3422 *adc;
  285. int err;
  286. u8 config;
  287. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
  288. return -EOPNOTSUPP;
  289. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc));
  290. if (!indio_dev)
  291. return -ENOMEM;
  292. adc = iio_priv(indio_dev);
  293. adc->i2c = client;
  294. adc->id = (u8)(id->driver_data);
  295. mutex_init(&adc->lock);
  296. indio_dev->dev.parent = &client->dev;
  297. indio_dev->dev.of_node = client->dev.of_node;
  298. indio_dev->name = dev_name(&client->dev);
  299. indio_dev->modes = INDIO_DIRECT_MODE;
  300. indio_dev->info = &mcp3422_info;
  301. switch (adc->id) {
  302. case 1:
  303. case 5:
  304. indio_dev->channels = mcp3421_channels;
  305. indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels);
  306. break;
  307. case 2:
  308. case 3:
  309. case 6:
  310. case 7:
  311. indio_dev->channels = mcp3422_channels;
  312. indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels);
  313. break;
  314. case 4:
  315. case 8:
  316. indio_dev->channels = mcp3424_channels;
  317. indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels);
  318. break;
  319. }
  320. /* meaningful default configuration */
  321. config = (MCP3422_CONT_SAMPLING
  322. | MCP3422_CHANNEL_VALUE(0)
  323. | MCP3422_PGA_VALUE(MCP3422_PGA_1)
  324. | MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240));
  325. err = mcp3422_update_config(adc, config);
  326. if (err < 0)
  327. return err;
  328. err = devm_iio_device_register(&client->dev, indio_dev);
  329. if (err < 0)
  330. return err;
  331. i2c_set_clientdata(client, indio_dev);
  332. return 0;
  333. }
  334. static const struct i2c_device_id mcp3422_id[] = {
  335. { "mcp3421", 1 },
  336. { "mcp3422", 2 },
  337. { "mcp3423", 3 },
  338. { "mcp3424", 4 },
  339. { "mcp3425", 5 },
  340. { "mcp3426", 6 },
  341. { "mcp3427", 7 },
  342. { "mcp3428", 8 },
  343. { }
  344. };
  345. MODULE_DEVICE_TABLE(i2c, mcp3422_id);
  346. #ifdef CONFIG_OF
  347. static const struct of_device_id mcp3422_of_match[] = {
  348. { .compatible = "mcp3422" },
  349. { }
  350. };
  351. MODULE_DEVICE_TABLE(of, mcp3422_of_match);
  352. #endif
  353. static struct i2c_driver mcp3422_driver = {
  354. .driver = {
  355. .name = "mcp3422",
  356. .of_match_table = of_match_ptr(mcp3422_of_match),
  357. },
  358. .probe = mcp3422_probe,
  359. .id_table = mcp3422_id,
  360. };
  361. module_i2c_driver(mcp3422_driver);
  362. MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
  363. MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver");
  364. MODULE_LICENSE("GPL v2");