mpu3050-core.c 33 KB

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  1. /*
  2. * MPU3050 gyroscope driver
  3. *
  4. * Copyright (C) 2016 Linaro Ltd.
  5. * Author: Linus Walleij <linus.walleij@linaro.org>
  6. *
  7. * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
  8. * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
  9. * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
  10. * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
  11. *
  12. * TODO: add support for setting up the low pass 3dB frequency.
  13. */
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/iio/buffer.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/sysfs.h>
  20. #include <linux/iio/trigger.h>
  21. #include <linux/iio/trigger_consumer.h>
  22. #include <linux/iio/triggered_buffer.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/module.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/random.h>
  27. #include <linux/slab.h>
  28. #include "mpu3050.h"
  29. #define MPU3050_CHIP_ID 0x68
  30. #define MPU3050_CHIP_ID_MASK 0x7E
  31. /*
  32. * Register map: anything suffixed *_H is a big-endian high byte and always
  33. * followed by the corresponding low byte (*_L) even though these are not
  34. * explicitly included in the register definitions.
  35. */
  36. #define MPU3050_CHIP_ID_REG 0x00
  37. #define MPU3050_PRODUCT_ID_REG 0x01
  38. #define MPU3050_XG_OFFS_TC 0x05
  39. #define MPU3050_YG_OFFS_TC 0x08
  40. #define MPU3050_ZG_OFFS_TC 0x0B
  41. #define MPU3050_X_OFFS_USR_H 0x0C
  42. #define MPU3050_Y_OFFS_USR_H 0x0E
  43. #define MPU3050_Z_OFFS_USR_H 0x10
  44. #define MPU3050_FIFO_EN 0x12
  45. #define MPU3050_AUX_VDDIO 0x13
  46. #define MPU3050_SLV_ADDR 0x14
  47. #define MPU3050_SMPLRT_DIV 0x15
  48. #define MPU3050_DLPF_FS_SYNC 0x16
  49. #define MPU3050_INT_CFG 0x17
  50. #define MPU3050_AUX_ADDR 0x18
  51. #define MPU3050_INT_STATUS 0x1A
  52. #define MPU3050_TEMP_H 0x1B
  53. #define MPU3050_XOUT_H 0x1D
  54. #define MPU3050_YOUT_H 0x1F
  55. #define MPU3050_ZOUT_H 0x21
  56. #define MPU3050_DMP_CFG1 0x35
  57. #define MPU3050_DMP_CFG2 0x36
  58. #define MPU3050_BANK_SEL 0x37
  59. #define MPU3050_MEM_START_ADDR 0x38
  60. #define MPU3050_MEM_R_W 0x39
  61. #define MPU3050_FIFO_COUNT_H 0x3A
  62. #define MPU3050_FIFO_R 0x3C
  63. #define MPU3050_USR_CTRL 0x3D
  64. #define MPU3050_PWR_MGM 0x3E
  65. /* MPU memory bank read options */
  66. #define MPU3050_MEM_PRFTCH BIT(5)
  67. #define MPU3050_MEM_USER_BANK BIT(4)
  68. /* Bits 8-11 select memory bank */
  69. #define MPU3050_MEM_RAM_BANK_0 0
  70. #define MPU3050_MEM_RAM_BANK_1 1
  71. #define MPU3050_MEM_RAM_BANK_2 2
  72. #define MPU3050_MEM_RAM_BANK_3 3
  73. #define MPU3050_MEM_OTP_BANK_0 4
  74. #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
  75. /* Register bits */
  76. /* FIFO Enable */
  77. #define MPU3050_FIFO_EN_FOOTER BIT(0)
  78. #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
  79. #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
  80. #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
  81. #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
  82. #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
  83. #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
  84. #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
  85. /*
  86. * Digital Low Pass filter (DLPF)
  87. * Full Scale (FS)
  88. * and Synchronization
  89. */
  90. #define MPU3050_EXT_SYNC_NONE 0x00
  91. #define MPU3050_EXT_SYNC_TEMP 0x20
  92. #define MPU3050_EXT_SYNC_GYROX 0x40
  93. #define MPU3050_EXT_SYNC_GYROY 0x60
  94. #define MPU3050_EXT_SYNC_GYROZ 0x80
  95. #define MPU3050_EXT_SYNC_ACCELX 0xA0
  96. #define MPU3050_EXT_SYNC_ACCELY 0xC0
  97. #define MPU3050_EXT_SYNC_ACCELZ 0xE0
  98. #define MPU3050_EXT_SYNC_MASK 0xE0
  99. #define MPU3050_EXT_SYNC_SHIFT 5
  100. #define MPU3050_FS_250DPS 0x00
  101. #define MPU3050_FS_500DPS 0x08
  102. #define MPU3050_FS_1000DPS 0x10
  103. #define MPU3050_FS_2000DPS 0x18
  104. #define MPU3050_FS_MASK 0x18
  105. #define MPU3050_FS_SHIFT 3
  106. #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
  107. #define MPU3050_DLPF_CFG_188HZ 0x01
  108. #define MPU3050_DLPF_CFG_98HZ 0x02
  109. #define MPU3050_DLPF_CFG_42HZ 0x03
  110. #define MPU3050_DLPF_CFG_20HZ 0x04
  111. #define MPU3050_DLPF_CFG_10HZ 0x05
  112. #define MPU3050_DLPF_CFG_5HZ 0x06
  113. #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
  114. #define MPU3050_DLPF_CFG_MASK 0x07
  115. #define MPU3050_DLPF_CFG_SHIFT 0
  116. /* Interrupt config */
  117. #define MPU3050_INT_RAW_RDY_EN BIT(0)
  118. #define MPU3050_INT_DMP_DONE_EN BIT(1)
  119. #define MPU3050_INT_MPU_RDY_EN BIT(2)
  120. #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
  121. #define MPU3050_INT_LATCH_EN BIT(5)
  122. #define MPU3050_INT_OPEN BIT(6)
  123. #define MPU3050_INT_ACTL BIT(7)
  124. /* Interrupt status */
  125. #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
  126. #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
  127. #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
  128. #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
  129. /* USR_CTRL */
  130. #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
  131. #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
  132. #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
  133. #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
  134. #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
  135. /* PWR_MGM */
  136. #define MPU3050_PWR_MGM_PLL_X 0x01
  137. #define MPU3050_PWR_MGM_PLL_Y 0x02
  138. #define MPU3050_PWR_MGM_PLL_Z 0x03
  139. #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
  140. #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
  141. #define MPU3050_PWR_MGM_STBY_YG BIT(4)
  142. #define MPU3050_PWR_MGM_STBY_XG BIT(5)
  143. #define MPU3050_PWR_MGM_SLEEP BIT(6)
  144. #define MPU3050_PWR_MGM_RESET BIT(7)
  145. #define MPU3050_PWR_MGM_MASK 0xff
  146. /*
  147. * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
  148. * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
  149. * in two's complement.
  150. */
  151. static unsigned int mpu3050_fs_precision[] = {
  152. IIO_DEGREE_TO_RAD(250),
  153. IIO_DEGREE_TO_RAD(500),
  154. IIO_DEGREE_TO_RAD(1000),
  155. IIO_DEGREE_TO_RAD(2000)
  156. };
  157. /*
  158. * Regulator names
  159. */
  160. static const char mpu3050_reg_vdd[] = "vdd";
  161. static const char mpu3050_reg_vlogic[] = "vlogic";
  162. static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
  163. {
  164. unsigned int freq;
  165. if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
  166. freq = 8000;
  167. else
  168. freq = 1000;
  169. freq /= (mpu3050->divisor + 1);
  170. return freq;
  171. }
  172. static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
  173. {
  174. __be16 raw_val[3];
  175. int ret;
  176. int i;
  177. /* Reset */
  178. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  179. MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
  180. if (ret)
  181. return ret;
  182. /* Turn on the Z-axis PLL */
  183. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  184. MPU3050_PWR_MGM_CLKSEL_MASK,
  185. MPU3050_PWR_MGM_PLL_Z);
  186. if (ret)
  187. return ret;
  188. /* Write calibration offset registers */
  189. for (i = 0; i < 3; i++)
  190. raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
  191. ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
  192. sizeof(raw_val));
  193. if (ret)
  194. return ret;
  195. /* Set low pass filter (sample rate), sync and full scale */
  196. ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
  197. MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
  198. mpu3050->fullscale << MPU3050_FS_SHIFT |
  199. mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
  200. if (ret)
  201. return ret;
  202. /* Set up sampling frequency */
  203. ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
  204. if (ret)
  205. return ret;
  206. /*
  207. * Max 50 ms start-up time after setting DLPF_FS_SYNC
  208. * according to the data sheet, then wait for the next sample
  209. * at this frequency T = 1000/f ms.
  210. */
  211. msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
  212. return 0;
  213. }
  214. static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
  215. {
  216. int ret;
  217. u8 divisor;
  218. enum mpu3050_lpf lpf;
  219. lpf = mpu3050->lpf;
  220. divisor = mpu3050->divisor;
  221. mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
  222. mpu3050->divisor = 0; /* Divide by 1 */
  223. ret = mpu3050_start_sampling(mpu3050);
  224. mpu3050->lpf = lpf;
  225. mpu3050->divisor = divisor;
  226. return ret;
  227. }
  228. static int mpu3050_read_raw(struct iio_dev *indio_dev,
  229. struct iio_chan_spec const *chan,
  230. int *val, int *val2,
  231. long mask)
  232. {
  233. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  234. int ret;
  235. __be16 raw_val;
  236. switch (mask) {
  237. case IIO_CHAN_INFO_OFFSET:
  238. switch (chan->type) {
  239. case IIO_TEMP:
  240. /*
  241. * The temperature scaling is (x+23000)/280 Celsius
  242. * for the "best fit straight line" temperature range
  243. * of -30C..85C. The 23000 includes room temperature
  244. * offset of +35C, 280 is the precision scale and x is
  245. * the 16-bit signed integer reported by hardware.
  246. *
  247. * Temperature value itself represents temperature of
  248. * the sensor die.
  249. */
  250. *val = 23000;
  251. return IIO_VAL_INT;
  252. default:
  253. return -EINVAL;
  254. }
  255. case IIO_CHAN_INFO_CALIBBIAS:
  256. switch (chan->type) {
  257. case IIO_ANGL_VEL:
  258. *val = mpu3050->calibration[chan->scan_index-1];
  259. return IIO_VAL_INT;
  260. default:
  261. return -EINVAL;
  262. }
  263. case IIO_CHAN_INFO_SAMP_FREQ:
  264. *val = mpu3050_get_freq(mpu3050);
  265. return IIO_VAL_INT;
  266. case IIO_CHAN_INFO_SCALE:
  267. switch (chan->type) {
  268. case IIO_TEMP:
  269. /* Millidegrees, see about temperature scaling above */
  270. *val = 1000;
  271. *val2 = 280;
  272. return IIO_VAL_FRACTIONAL;
  273. case IIO_ANGL_VEL:
  274. /*
  275. * Convert to the corresponding full scale in
  276. * radians. All 16 bits are used with sign to
  277. * span the available scale: to account for the one
  278. * missing value if we multiply by 1/S16_MAX, instead
  279. * multiply with 2/U16_MAX.
  280. */
  281. *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
  282. *val2 = U16_MAX;
  283. return IIO_VAL_FRACTIONAL;
  284. default:
  285. return -EINVAL;
  286. }
  287. case IIO_CHAN_INFO_RAW:
  288. /* Resume device */
  289. pm_runtime_get_sync(mpu3050->dev);
  290. mutex_lock(&mpu3050->lock);
  291. ret = mpu3050_set_8khz_samplerate(mpu3050);
  292. if (ret)
  293. goto out_read_raw_unlock;
  294. switch (chan->type) {
  295. case IIO_TEMP:
  296. ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
  297. &raw_val, sizeof(raw_val));
  298. if (ret) {
  299. dev_err(mpu3050->dev,
  300. "error reading temperature\n");
  301. goto out_read_raw_unlock;
  302. }
  303. *val = (s16)be16_to_cpu(raw_val);
  304. ret = IIO_VAL_INT;
  305. goto out_read_raw_unlock;
  306. case IIO_ANGL_VEL:
  307. ret = regmap_bulk_read(mpu3050->map,
  308. MPU3050_AXIS_REGS(chan->scan_index-1),
  309. &raw_val,
  310. sizeof(raw_val));
  311. if (ret) {
  312. dev_err(mpu3050->dev,
  313. "error reading axis data\n");
  314. goto out_read_raw_unlock;
  315. }
  316. *val = be16_to_cpu(raw_val);
  317. ret = IIO_VAL_INT;
  318. goto out_read_raw_unlock;
  319. default:
  320. ret = -EINVAL;
  321. goto out_read_raw_unlock;
  322. }
  323. default:
  324. break;
  325. }
  326. return -EINVAL;
  327. out_read_raw_unlock:
  328. mutex_unlock(&mpu3050->lock);
  329. pm_runtime_mark_last_busy(mpu3050->dev);
  330. pm_runtime_put_autosuspend(mpu3050->dev);
  331. return ret;
  332. }
  333. static int mpu3050_write_raw(struct iio_dev *indio_dev,
  334. const struct iio_chan_spec *chan,
  335. int val, int val2, long mask)
  336. {
  337. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  338. /*
  339. * Couldn't figure out a way to precalculate these at compile time.
  340. */
  341. unsigned int fs250 =
  342. DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
  343. U16_MAX);
  344. unsigned int fs500 =
  345. DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
  346. U16_MAX);
  347. unsigned int fs1000 =
  348. DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
  349. U16_MAX);
  350. unsigned int fs2000 =
  351. DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
  352. U16_MAX);
  353. switch (mask) {
  354. case IIO_CHAN_INFO_CALIBBIAS:
  355. if (chan->type != IIO_ANGL_VEL)
  356. return -EINVAL;
  357. mpu3050->calibration[chan->scan_index-1] = val;
  358. return 0;
  359. case IIO_CHAN_INFO_SAMP_FREQ:
  360. /*
  361. * The max samplerate is 8000 Hz, the minimum
  362. * 1000 / 256 ~= 4 Hz
  363. */
  364. if (val < 4 || val > 8000)
  365. return -EINVAL;
  366. /*
  367. * Above 1000 Hz we must turn off the digital low pass filter
  368. * so we get a base frequency of 8kHz to the divider
  369. */
  370. if (val > 1000) {
  371. mpu3050->lpf = LPF_256_HZ_NOLPF;
  372. mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
  373. return 0;
  374. }
  375. mpu3050->lpf = LPF_188_HZ;
  376. mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
  377. return 0;
  378. case IIO_CHAN_INFO_SCALE:
  379. if (chan->type != IIO_ANGL_VEL)
  380. return -EINVAL;
  381. /*
  382. * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
  383. * which means we need to round to the closest radians
  384. * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
  385. * rad/s. The scale is then for the 16 bits used to cover
  386. * it 2/(2^16) of that.
  387. */
  388. /* Just too large, set the max range */
  389. if (val != 0) {
  390. mpu3050->fullscale = FS_2000_DPS;
  391. return 0;
  392. }
  393. /*
  394. * Now we're dealing with fractions below zero in millirad/s
  395. * do some integer interpolation and match with the closest
  396. * fullscale in the table.
  397. */
  398. if (val2 <= fs250 ||
  399. val2 < ((fs500 + fs250) / 2))
  400. mpu3050->fullscale = FS_250_DPS;
  401. else if (val2 <= fs500 ||
  402. val2 < ((fs1000 + fs500) / 2))
  403. mpu3050->fullscale = FS_500_DPS;
  404. else if (val2 <= fs1000 ||
  405. val2 < ((fs2000 + fs1000) / 2))
  406. mpu3050->fullscale = FS_1000_DPS;
  407. else
  408. /* Catch-all */
  409. mpu3050->fullscale = FS_2000_DPS;
  410. return 0;
  411. default:
  412. break;
  413. }
  414. return -EINVAL;
  415. }
  416. static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
  417. {
  418. const struct iio_poll_func *pf = p;
  419. struct iio_dev *indio_dev = pf->indio_dev;
  420. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  421. int ret;
  422. /*
  423. * Temperature 1*16 bits
  424. * Three axes 3*16 bits
  425. * Timestamp 64 bits (4*16 bits)
  426. * Sum total 8*16 bits
  427. */
  428. __be16 hw_values[8];
  429. s64 timestamp;
  430. unsigned int datums_from_fifo = 0;
  431. /*
  432. * If we're using the hardware trigger, get the precise timestamp from
  433. * the top half of the threaded IRQ handler. Otherwise get the
  434. * timestamp here so it will be close in time to the actual values
  435. * read from the registers.
  436. */
  437. if (iio_trigger_using_own(indio_dev))
  438. timestamp = mpu3050->hw_timestamp;
  439. else
  440. timestamp = iio_get_time_ns(indio_dev);
  441. mutex_lock(&mpu3050->lock);
  442. /* Using the hardware IRQ trigger? Check the buffer then. */
  443. if (mpu3050->hw_irq_trigger) {
  444. __be16 raw_fifocnt;
  445. u16 fifocnt;
  446. /* X, Y, Z + temperature */
  447. unsigned int bytes_per_datum = 8;
  448. bool fifo_overflow = false;
  449. ret = regmap_bulk_read(mpu3050->map,
  450. MPU3050_FIFO_COUNT_H,
  451. &raw_fifocnt,
  452. sizeof(raw_fifocnt));
  453. if (ret)
  454. goto out_trigger_unlock;
  455. fifocnt = be16_to_cpu(raw_fifocnt);
  456. if (fifocnt == 512) {
  457. dev_info(mpu3050->dev,
  458. "FIFO overflow! Emptying and resetting FIFO\n");
  459. fifo_overflow = true;
  460. /* Reset and enable the FIFO */
  461. ret = regmap_update_bits(mpu3050->map,
  462. MPU3050_USR_CTRL,
  463. MPU3050_USR_CTRL_FIFO_EN |
  464. MPU3050_USR_CTRL_FIFO_RST,
  465. MPU3050_USR_CTRL_FIFO_EN |
  466. MPU3050_USR_CTRL_FIFO_RST);
  467. if (ret) {
  468. dev_info(mpu3050->dev, "error resetting FIFO\n");
  469. goto out_trigger_unlock;
  470. }
  471. mpu3050->pending_fifo_footer = false;
  472. }
  473. if (fifocnt)
  474. dev_dbg(mpu3050->dev,
  475. "%d bytes in the FIFO\n",
  476. fifocnt);
  477. while (!fifo_overflow && fifocnt > bytes_per_datum) {
  478. unsigned int toread;
  479. unsigned int offset;
  480. __be16 fifo_values[5];
  481. /*
  482. * If there is a FIFO footer in the pipe, first clear
  483. * that out. This follows the complex algorithm in the
  484. * datasheet that states that you may never leave the
  485. * FIFO empty after the first reading: you have to
  486. * always leave two footer bytes in it. The footer is
  487. * in practice just two zero bytes.
  488. */
  489. if (mpu3050->pending_fifo_footer) {
  490. toread = bytes_per_datum + 2;
  491. offset = 0;
  492. } else {
  493. toread = bytes_per_datum;
  494. offset = 1;
  495. /* Put in some dummy value */
  496. fifo_values[0] = 0xAAAA;
  497. }
  498. ret = regmap_bulk_read(mpu3050->map,
  499. MPU3050_FIFO_R,
  500. &fifo_values[offset],
  501. toread);
  502. if (ret)
  503. goto out_trigger_unlock;
  504. dev_dbg(mpu3050->dev,
  505. "%04x %04x %04x %04x %04x\n",
  506. fifo_values[0],
  507. fifo_values[1],
  508. fifo_values[2],
  509. fifo_values[3],
  510. fifo_values[4]);
  511. /* Index past the footer (fifo_values[0]) and push */
  512. iio_push_to_buffers_with_timestamp(indio_dev,
  513. &fifo_values[1],
  514. timestamp);
  515. fifocnt -= toread;
  516. datums_from_fifo++;
  517. mpu3050->pending_fifo_footer = true;
  518. /*
  519. * If we're emptying the FIFO, just make sure to
  520. * check if something new appeared.
  521. */
  522. if (fifocnt < bytes_per_datum) {
  523. ret = regmap_bulk_read(mpu3050->map,
  524. MPU3050_FIFO_COUNT_H,
  525. &raw_fifocnt,
  526. sizeof(raw_fifocnt));
  527. if (ret)
  528. goto out_trigger_unlock;
  529. fifocnt = be16_to_cpu(raw_fifocnt);
  530. }
  531. if (fifocnt < bytes_per_datum)
  532. dev_dbg(mpu3050->dev,
  533. "%d bytes left in the FIFO\n",
  534. fifocnt);
  535. /*
  536. * At this point, the timestamp that triggered the
  537. * hardware interrupt is no longer valid for what
  538. * we are reading (the interrupt likely fired for
  539. * the value on the top of the FIFO), so set the
  540. * timestamp to zero and let userspace deal with it.
  541. */
  542. timestamp = 0;
  543. }
  544. }
  545. /*
  546. * If we picked some datums from the FIFO that's enough, else
  547. * fall through and just read from the current value registers.
  548. * This happens in two cases:
  549. *
  550. * - We are using some other trigger (external, like an HRTimer)
  551. * than the sensor's own sample generator. In this case the
  552. * sensor is just set to the max sampling frequency and we give
  553. * the trigger a copy of the latest value every time we get here.
  554. *
  555. * - The hardware trigger is active but unused and we actually use
  556. * another trigger which calls here with a frequency higher
  557. * than what the device provides data. We will then just read
  558. * duplicate values directly from the hardware registers.
  559. */
  560. if (datums_from_fifo) {
  561. dev_dbg(mpu3050->dev,
  562. "read %d datums from the FIFO\n",
  563. datums_from_fifo);
  564. goto out_trigger_unlock;
  565. }
  566. ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values,
  567. sizeof(hw_values));
  568. if (ret) {
  569. dev_err(mpu3050->dev,
  570. "error reading axis data\n");
  571. goto out_trigger_unlock;
  572. }
  573. iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp);
  574. out_trigger_unlock:
  575. mutex_unlock(&mpu3050->lock);
  576. iio_trigger_notify_done(indio_dev->trig);
  577. return IRQ_HANDLED;
  578. }
  579. static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
  580. {
  581. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  582. pm_runtime_get_sync(mpu3050->dev);
  583. /* Unless we have OUR trigger active, run at full speed */
  584. if (!mpu3050->hw_irq_trigger)
  585. return mpu3050_set_8khz_samplerate(mpu3050);
  586. return 0;
  587. }
  588. static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
  589. {
  590. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  591. pm_runtime_mark_last_busy(mpu3050->dev);
  592. pm_runtime_put_autosuspend(mpu3050->dev);
  593. return 0;
  594. }
  595. static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
  596. .preenable = mpu3050_buffer_preenable,
  597. .postenable = iio_triggered_buffer_postenable,
  598. .predisable = iio_triggered_buffer_predisable,
  599. .postdisable = mpu3050_buffer_postdisable,
  600. };
  601. static const struct iio_mount_matrix *
  602. mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
  603. const struct iio_chan_spec *chan)
  604. {
  605. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  606. return &mpu3050->orientation;
  607. }
  608. static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
  609. IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
  610. { },
  611. };
  612. #define MPU3050_AXIS_CHANNEL(axis, index) \
  613. { \
  614. .type = IIO_ANGL_VEL, \
  615. .modified = 1, \
  616. .channel2 = IIO_MOD_##axis, \
  617. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  618. BIT(IIO_CHAN_INFO_CALIBBIAS), \
  619. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  620. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
  621. .ext_info = mpu3050_ext_info, \
  622. .scan_index = index, \
  623. .scan_type = { \
  624. .sign = 's', \
  625. .realbits = 16, \
  626. .storagebits = 16, \
  627. .endianness = IIO_BE, \
  628. }, \
  629. }
  630. static const struct iio_chan_spec mpu3050_channels[] = {
  631. {
  632. .type = IIO_TEMP,
  633. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  634. BIT(IIO_CHAN_INFO_SCALE) |
  635. BIT(IIO_CHAN_INFO_OFFSET),
  636. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
  637. .scan_index = 0,
  638. .scan_type = {
  639. .sign = 's',
  640. .realbits = 16,
  641. .storagebits = 16,
  642. .endianness = IIO_BE,
  643. },
  644. },
  645. MPU3050_AXIS_CHANNEL(X, 1),
  646. MPU3050_AXIS_CHANNEL(Y, 2),
  647. MPU3050_AXIS_CHANNEL(Z, 3),
  648. IIO_CHAN_SOFT_TIMESTAMP(4),
  649. };
  650. /* Four channels apart from timestamp, scan mask = 0x0f */
  651. static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
  652. /*
  653. * These are just the hardcoded factors resulting from the more elaborate
  654. * calculations done with fractions in the scale raw get/set functions.
  655. */
  656. static IIO_CONST_ATTR(anglevel_scale_available,
  657. "0.000122070 "
  658. "0.000274658 "
  659. "0.000518798 "
  660. "0.001068115");
  661. static struct attribute *mpu3050_attributes[] = {
  662. &iio_const_attr_anglevel_scale_available.dev_attr.attr,
  663. NULL,
  664. };
  665. static const struct attribute_group mpu3050_attribute_group = {
  666. .attrs = mpu3050_attributes,
  667. };
  668. static const struct iio_info mpu3050_info = {
  669. .read_raw = mpu3050_read_raw,
  670. .write_raw = mpu3050_write_raw,
  671. .attrs = &mpu3050_attribute_group,
  672. };
  673. /**
  674. * mpu3050_read_mem() - read MPU-3050 internal memory
  675. * @mpu3050: device to read from
  676. * @bank: target bank
  677. * @addr: target address
  678. * @len: number of bytes
  679. * @buf: the buffer to store the read bytes in
  680. */
  681. static int mpu3050_read_mem(struct mpu3050 *mpu3050,
  682. u8 bank,
  683. u8 addr,
  684. u8 len,
  685. u8 *buf)
  686. {
  687. int ret;
  688. ret = regmap_write(mpu3050->map,
  689. MPU3050_BANK_SEL,
  690. bank);
  691. if (ret)
  692. return ret;
  693. ret = regmap_write(mpu3050->map,
  694. MPU3050_MEM_START_ADDR,
  695. addr);
  696. if (ret)
  697. return ret;
  698. return regmap_bulk_read(mpu3050->map,
  699. MPU3050_MEM_R_W,
  700. buf,
  701. len);
  702. }
  703. static int mpu3050_hw_init(struct mpu3050 *mpu3050)
  704. {
  705. int ret;
  706. u8 otp[8];
  707. /* Reset */
  708. ret = regmap_update_bits(mpu3050->map,
  709. MPU3050_PWR_MGM,
  710. MPU3050_PWR_MGM_RESET,
  711. MPU3050_PWR_MGM_RESET);
  712. if (ret)
  713. return ret;
  714. /* Turn on the PLL */
  715. ret = regmap_update_bits(mpu3050->map,
  716. MPU3050_PWR_MGM,
  717. MPU3050_PWR_MGM_CLKSEL_MASK,
  718. MPU3050_PWR_MGM_PLL_Z);
  719. if (ret)
  720. return ret;
  721. /* Disable IRQs */
  722. ret = regmap_write(mpu3050->map,
  723. MPU3050_INT_CFG,
  724. 0);
  725. if (ret)
  726. return ret;
  727. /* Read out the 8 bytes of OTP (one-time-programmable) memory */
  728. ret = mpu3050_read_mem(mpu3050,
  729. (MPU3050_MEM_PRFTCH |
  730. MPU3050_MEM_USER_BANK |
  731. MPU3050_MEM_OTP_BANK_0),
  732. 0,
  733. sizeof(otp),
  734. otp);
  735. if (ret)
  736. return ret;
  737. /* This is device-unique data so it goes into the entropy pool */
  738. add_device_randomness(otp, sizeof(otp));
  739. dev_info(mpu3050->dev,
  740. "die ID: %04X, wafer ID: %02X, A lot ID: %04X, "
  741. "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n",
  742. /* Die ID, bits 0-12 */
  743. (otp[1] << 8 | otp[0]) & 0x1fff,
  744. /* Wafer ID, bits 13-17 */
  745. ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5,
  746. /* A lot ID, bits 18-33 */
  747. ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2,
  748. /* W lot ID, bits 34-45 */
  749. ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2,
  750. /* WP ID, bits 47-49 */
  751. ((otp[6] << 8 | otp[5]) & 0x0380) >> 7,
  752. /* rev ID, bits 50-55 */
  753. otp[6] >> 2);
  754. return 0;
  755. }
  756. static int mpu3050_power_up(struct mpu3050 *mpu3050)
  757. {
  758. int ret;
  759. ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
  760. if (ret) {
  761. dev_err(mpu3050->dev, "cannot enable regulators\n");
  762. return ret;
  763. }
  764. /*
  765. * 20-100 ms start-up time for register read/write according to
  766. * the datasheet, be on the safe side and wait 200 ms.
  767. */
  768. msleep(200);
  769. /* Take device out of sleep mode */
  770. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  771. MPU3050_PWR_MGM_SLEEP, 0);
  772. if (ret) {
  773. dev_err(mpu3050->dev, "error setting power mode\n");
  774. return ret;
  775. }
  776. msleep(10);
  777. return 0;
  778. }
  779. static int mpu3050_power_down(struct mpu3050 *mpu3050)
  780. {
  781. int ret;
  782. /*
  783. * Put MPU-3050 into sleep mode before cutting regulators.
  784. * This is important, because we may not be the sole user
  785. * of the regulator so the power may stay on after this, and
  786. * then we would be wasting power unless we go to sleep mode
  787. * first.
  788. */
  789. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  790. MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
  791. if (ret)
  792. dev_err(mpu3050->dev, "error putting to sleep\n");
  793. ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
  794. if (ret)
  795. dev_err(mpu3050->dev, "error disabling regulators\n");
  796. return 0;
  797. }
  798. static irqreturn_t mpu3050_irq_handler(int irq, void *p)
  799. {
  800. struct iio_trigger *trig = p;
  801. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  802. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  803. if (!mpu3050->hw_irq_trigger)
  804. return IRQ_NONE;
  805. /* Get the time stamp as close in time as possible */
  806. mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
  807. return IRQ_WAKE_THREAD;
  808. }
  809. static irqreturn_t mpu3050_irq_thread(int irq, void *p)
  810. {
  811. struct iio_trigger *trig = p;
  812. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  813. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  814. unsigned int val;
  815. int ret;
  816. /* ACK IRQ and check if it was from us */
  817. ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
  818. if (ret) {
  819. dev_err(mpu3050->dev, "error reading IRQ status\n");
  820. return IRQ_HANDLED;
  821. }
  822. if (!(val & MPU3050_INT_STATUS_RAW_RDY))
  823. return IRQ_NONE;
  824. iio_trigger_poll_chained(p);
  825. return IRQ_HANDLED;
  826. }
  827. /**
  828. * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
  829. * @trig: trigger instance
  830. * @enable: true if trigger should be enabled, false to disable
  831. */
  832. static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
  833. bool enable)
  834. {
  835. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  836. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  837. unsigned int val;
  838. int ret;
  839. /* Disabling trigger: disable interrupt and return */
  840. if (!enable) {
  841. /* Disable all interrupts */
  842. ret = regmap_write(mpu3050->map,
  843. MPU3050_INT_CFG,
  844. 0);
  845. if (ret)
  846. dev_err(mpu3050->dev, "error disabling IRQ\n");
  847. /* Clear IRQ flag */
  848. ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
  849. if (ret)
  850. dev_err(mpu3050->dev, "error clearing IRQ status\n");
  851. /* Disable all things in the FIFO and reset it */
  852. ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
  853. if (ret)
  854. dev_err(mpu3050->dev, "error disabling FIFO\n");
  855. ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
  856. MPU3050_USR_CTRL_FIFO_RST);
  857. if (ret)
  858. dev_err(mpu3050->dev, "error resetting FIFO\n");
  859. pm_runtime_mark_last_busy(mpu3050->dev);
  860. pm_runtime_put_autosuspend(mpu3050->dev);
  861. mpu3050->hw_irq_trigger = false;
  862. return 0;
  863. } else {
  864. /* Else we're enabling the trigger from this point */
  865. pm_runtime_get_sync(mpu3050->dev);
  866. mpu3050->hw_irq_trigger = true;
  867. /* Disable all things in the FIFO */
  868. ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
  869. if (ret)
  870. return ret;
  871. /* Reset and enable the FIFO */
  872. ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
  873. MPU3050_USR_CTRL_FIFO_EN |
  874. MPU3050_USR_CTRL_FIFO_RST,
  875. MPU3050_USR_CTRL_FIFO_EN |
  876. MPU3050_USR_CTRL_FIFO_RST);
  877. if (ret)
  878. return ret;
  879. mpu3050->pending_fifo_footer = false;
  880. /* Turn on the FIFO for temp+X+Y+Z */
  881. ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
  882. MPU3050_FIFO_EN_TEMP_OUT |
  883. MPU3050_FIFO_EN_GYRO_XOUT |
  884. MPU3050_FIFO_EN_GYRO_YOUT |
  885. MPU3050_FIFO_EN_GYRO_ZOUT |
  886. MPU3050_FIFO_EN_FOOTER);
  887. if (ret)
  888. return ret;
  889. /* Configure the sample engine */
  890. ret = mpu3050_start_sampling(mpu3050);
  891. if (ret)
  892. return ret;
  893. /* Clear IRQ flag */
  894. ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
  895. if (ret)
  896. dev_err(mpu3050->dev, "error clearing IRQ status\n");
  897. /* Give us interrupts whenever there is new data ready */
  898. val = MPU3050_INT_RAW_RDY_EN;
  899. if (mpu3050->irq_actl)
  900. val |= MPU3050_INT_ACTL;
  901. if (mpu3050->irq_latch)
  902. val |= MPU3050_INT_LATCH_EN;
  903. if (mpu3050->irq_opendrain)
  904. val |= MPU3050_INT_OPEN;
  905. ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
  906. if (ret)
  907. return ret;
  908. }
  909. return 0;
  910. }
  911. static const struct iio_trigger_ops mpu3050_trigger_ops = {
  912. .set_trigger_state = mpu3050_drdy_trigger_set_state,
  913. };
  914. static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
  915. {
  916. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  917. unsigned long irq_trig;
  918. int ret;
  919. mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
  920. "%s-dev%d",
  921. indio_dev->name,
  922. indio_dev->id);
  923. if (!mpu3050->trig)
  924. return -ENOMEM;
  925. /* Check if IRQ is open drain */
  926. if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
  927. mpu3050->irq_opendrain = true;
  928. irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
  929. /*
  930. * Configure the interrupt generator hardware to supply whatever
  931. * the interrupt is configured for, edges low/high level low/high,
  932. * we can provide it all.
  933. */
  934. switch (irq_trig) {
  935. case IRQF_TRIGGER_RISING:
  936. dev_info(&indio_dev->dev,
  937. "pulse interrupts on the rising edge\n");
  938. break;
  939. case IRQF_TRIGGER_FALLING:
  940. mpu3050->irq_actl = true;
  941. dev_info(&indio_dev->dev,
  942. "pulse interrupts on the falling edge\n");
  943. break;
  944. case IRQF_TRIGGER_HIGH:
  945. mpu3050->irq_latch = true;
  946. dev_info(&indio_dev->dev,
  947. "interrupts active high level\n");
  948. /*
  949. * With level IRQs, we mask the IRQ until it is processed,
  950. * but with edge IRQs (pulses) we can queue several interrupts
  951. * in the top half.
  952. */
  953. irq_trig |= IRQF_ONESHOT;
  954. break;
  955. case IRQF_TRIGGER_LOW:
  956. mpu3050->irq_latch = true;
  957. mpu3050->irq_actl = true;
  958. irq_trig |= IRQF_ONESHOT;
  959. dev_info(&indio_dev->dev,
  960. "interrupts active low level\n");
  961. break;
  962. default:
  963. /* This is the most preferred mode, if possible */
  964. dev_err(&indio_dev->dev,
  965. "unsupported IRQ trigger specified (%lx), enforce "
  966. "rising edge\n", irq_trig);
  967. irq_trig = IRQF_TRIGGER_RISING;
  968. break;
  969. }
  970. /* An open drain line can be shared with several devices */
  971. if (mpu3050->irq_opendrain)
  972. irq_trig |= IRQF_SHARED;
  973. ret = request_threaded_irq(irq,
  974. mpu3050_irq_handler,
  975. mpu3050_irq_thread,
  976. irq_trig,
  977. mpu3050->trig->name,
  978. mpu3050->trig);
  979. if (ret) {
  980. dev_err(mpu3050->dev,
  981. "can't get IRQ %d, error %d\n", irq, ret);
  982. return ret;
  983. }
  984. mpu3050->irq = irq;
  985. mpu3050->trig->dev.parent = mpu3050->dev;
  986. mpu3050->trig->ops = &mpu3050_trigger_ops;
  987. iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
  988. ret = iio_trigger_register(mpu3050->trig);
  989. if (ret)
  990. return ret;
  991. indio_dev->trig = iio_trigger_get(mpu3050->trig);
  992. return 0;
  993. }
  994. int mpu3050_common_probe(struct device *dev,
  995. struct regmap *map,
  996. int irq,
  997. const char *name)
  998. {
  999. struct iio_dev *indio_dev;
  1000. struct mpu3050 *mpu3050;
  1001. unsigned int val;
  1002. int ret;
  1003. indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
  1004. if (!indio_dev)
  1005. return -ENOMEM;
  1006. mpu3050 = iio_priv(indio_dev);
  1007. mpu3050->dev = dev;
  1008. mpu3050->map = map;
  1009. mutex_init(&mpu3050->lock);
  1010. /* Default fullscale: 2000 degrees per second */
  1011. mpu3050->fullscale = FS_2000_DPS;
  1012. /* 1 kHz, divide by 100, default frequency = 10 Hz */
  1013. mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
  1014. mpu3050->divisor = 99;
  1015. /* Read the mounting matrix, if present */
  1016. ret = of_iio_read_mount_matrix(dev, "mount-matrix",
  1017. &mpu3050->orientation);
  1018. if (ret)
  1019. return ret;
  1020. /* Fetch and turn on regulators */
  1021. mpu3050->regs[0].supply = mpu3050_reg_vdd;
  1022. mpu3050->regs[1].supply = mpu3050_reg_vlogic;
  1023. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
  1024. mpu3050->regs);
  1025. if (ret) {
  1026. dev_err(dev, "Cannot get regulators\n");
  1027. return ret;
  1028. }
  1029. ret = mpu3050_power_up(mpu3050);
  1030. if (ret)
  1031. return ret;
  1032. ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
  1033. if (ret) {
  1034. dev_err(dev, "could not read device ID\n");
  1035. ret = -ENODEV;
  1036. goto err_power_down;
  1037. }
  1038. if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
  1039. dev_err(dev, "unsupported chip id %02x\n",
  1040. (u8)(val & MPU3050_CHIP_ID_MASK));
  1041. ret = -ENODEV;
  1042. goto err_power_down;
  1043. }
  1044. ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
  1045. if (ret) {
  1046. dev_err(dev, "could not read device ID\n");
  1047. ret = -ENODEV;
  1048. goto err_power_down;
  1049. }
  1050. dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
  1051. ((val >> 4) & 0xf), (val & 0xf));
  1052. ret = mpu3050_hw_init(mpu3050);
  1053. if (ret)
  1054. goto err_power_down;
  1055. indio_dev->dev.parent = dev;
  1056. indio_dev->channels = mpu3050_channels;
  1057. indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
  1058. indio_dev->info = &mpu3050_info;
  1059. indio_dev->available_scan_masks = mpu3050_scan_masks;
  1060. indio_dev->modes = INDIO_DIRECT_MODE;
  1061. indio_dev->name = name;
  1062. ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
  1063. mpu3050_trigger_handler,
  1064. &mpu3050_buffer_setup_ops);
  1065. if (ret) {
  1066. dev_err(dev, "triggered buffer setup failed\n");
  1067. goto err_power_down;
  1068. }
  1069. ret = iio_device_register(indio_dev);
  1070. if (ret) {
  1071. dev_err(dev, "device register failed\n");
  1072. goto err_cleanup_buffer;
  1073. }
  1074. dev_set_drvdata(dev, indio_dev);
  1075. /* Check if we have an assigned IRQ to use as trigger */
  1076. if (irq) {
  1077. ret = mpu3050_trigger_probe(indio_dev, irq);
  1078. if (ret)
  1079. dev_err(dev, "failed to register trigger\n");
  1080. }
  1081. /* Enable runtime PM */
  1082. pm_runtime_get_noresume(dev);
  1083. pm_runtime_set_active(dev);
  1084. pm_runtime_enable(dev);
  1085. /*
  1086. * Set autosuspend to two orders of magnitude larger than the
  1087. * start-up time. 100ms start-up time means 10000ms autosuspend,
  1088. * i.e. 10 seconds.
  1089. */
  1090. pm_runtime_set_autosuspend_delay(dev, 10000);
  1091. pm_runtime_use_autosuspend(dev);
  1092. pm_runtime_put(dev);
  1093. return 0;
  1094. err_cleanup_buffer:
  1095. iio_triggered_buffer_cleanup(indio_dev);
  1096. err_power_down:
  1097. mpu3050_power_down(mpu3050);
  1098. return ret;
  1099. }
  1100. EXPORT_SYMBOL(mpu3050_common_probe);
  1101. int mpu3050_common_remove(struct device *dev)
  1102. {
  1103. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1104. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  1105. pm_runtime_get_sync(dev);
  1106. pm_runtime_put_noidle(dev);
  1107. pm_runtime_disable(dev);
  1108. iio_triggered_buffer_cleanup(indio_dev);
  1109. if (mpu3050->irq)
  1110. free_irq(mpu3050->irq, mpu3050);
  1111. iio_device_unregister(indio_dev);
  1112. mpu3050_power_down(mpu3050);
  1113. return 0;
  1114. }
  1115. EXPORT_SYMBOL(mpu3050_common_remove);
  1116. #ifdef CONFIG_PM
  1117. static int mpu3050_runtime_suspend(struct device *dev)
  1118. {
  1119. return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
  1120. }
  1121. static int mpu3050_runtime_resume(struct device *dev)
  1122. {
  1123. return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
  1124. }
  1125. #endif /* CONFIG_PM */
  1126. const struct dev_pm_ops mpu3050_dev_pm_ops = {
  1127. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1128. pm_runtime_force_resume)
  1129. SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
  1130. mpu3050_runtime_resume, NULL)
  1131. };
  1132. EXPORT_SYMBOL(mpu3050_dev_pm_ops);
  1133. MODULE_AUTHOR("Linus Walleij");
  1134. MODULE_DESCRIPTION("MPU3050 gyroscope driver");
  1135. MODULE_LICENSE("GPL");