adv7180.c 40 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504
  1. /*
  2. * adv7180.c Analog Devices ADV7180 video decoder driver
  3. * Copyright (c) 2009 Intel Corporation
  4. * Copyright (C) 2013 Cogent Embedded, Inc.
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/i2c.h>
  22. #include <linux/slab.h>
  23. #include <linux/of.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include <media/v4l2-event.h>
  28. #include <media/v4l2-device.h>
  29. #include <media/v4l2-ctrls.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
  33. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
  34. #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
  35. #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
  36. #define ADV7180_STD_NTSC_J 0x4
  37. #define ADV7180_STD_NTSC_M 0x5
  38. #define ADV7180_STD_PAL60 0x6
  39. #define ADV7180_STD_NTSC_443 0x7
  40. #define ADV7180_STD_PAL_BG 0x8
  41. #define ADV7180_STD_PAL_N 0x9
  42. #define ADV7180_STD_PAL_M 0xa
  43. #define ADV7180_STD_PAL_M_PED 0xb
  44. #define ADV7180_STD_PAL_COMB_N 0xc
  45. #define ADV7180_STD_PAL_COMB_N_PED 0xd
  46. #define ADV7180_STD_PAL_SECAM 0xe
  47. #define ADV7180_STD_PAL_SECAM_PED 0xf
  48. #define ADV7180_REG_INPUT_CONTROL 0x0000
  49. #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
  50. #define ADV7182_REG_INPUT_VIDSEL 0x0002
  51. #define ADV7180_REG_OUTPUT_CONTROL 0x0003
  52. #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
  53. #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
  54. #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
  55. #define ADV7180_AUTODETECT_DEFAULT 0x7f
  56. /* Contrast */
  57. #define ADV7180_REG_CON 0x0008 /*Unsigned */
  58. #define ADV7180_CON_MIN 0
  59. #define ADV7180_CON_DEF 128
  60. #define ADV7180_CON_MAX 255
  61. /* Brightness*/
  62. #define ADV7180_REG_BRI 0x000a /*Signed */
  63. #define ADV7180_BRI_MIN -128
  64. #define ADV7180_BRI_DEF 0
  65. #define ADV7180_BRI_MAX 127
  66. /* Hue */
  67. #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
  68. #define ADV7180_HUE_MIN -127
  69. #define ADV7180_HUE_DEF 0
  70. #define ADV7180_HUE_MAX 128
  71. #define ADV7180_REG_CTRL 0x000e
  72. #define ADV7180_CTRL_IRQ_SPACE 0x20
  73. #define ADV7180_REG_PWR_MAN 0x0f
  74. #define ADV7180_PWR_MAN_ON 0x04
  75. #define ADV7180_PWR_MAN_OFF 0x24
  76. #define ADV7180_PWR_MAN_RES 0x80
  77. #define ADV7180_REG_STATUS1 0x0010
  78. #define ADV7180_STATUS1_IN_LOCK 0x01
  79. #define ADV7180_STATUS1_AUTOD_MASK 0x70
  80. #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
  81. #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  82. #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
  83. #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
  84. #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
  85. #define ADV7180_STATUS1_AUTOD_SECAM 0x50
  86. #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
  87. #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
  88. #define ADV7180_REG_IDENT 0x0011
  89. #define ADV7180_ID_7180 0x18
  90. #define ADV7180_REG_STATUS3 0x0013
  91. #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
  92. #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
  93. #define ADV7180_REG_CTRL_2 0x001d
  94. #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
  95. #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
  96. #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
  97. #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
  98. #define ADV7180_REG_LOCK_CNT 0x0051
  99. #define ADV7180_REG_CVBS_TRIM 0x0052
  100. #define ADV7180_REG_CLAMP_ADJ 0x005a
  101. #define ADV7180_REG_RES_CIR 0x005f
  102. #define ADV7180_REG_DIFF_MODE 0x0060
  103. #define ADV7180_REG_ICONF1 0x2040
  104. #define ADV7180_ICONF1_ACTIVE_LOW 0x01
  105. #define ADV7180_ICONF1_PSYNC_ONLY 0x10
  106. #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
  107. /* Saturation */
  108. #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
  109. #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
  110. #define ADV7180_SAT_MIN 0
  111. #define ADV7180_SAT_DEF 128
  112. #define ADV7180_SAT_MAX 255
  113. #define ADV7180_IRQ1_LOCK 0x01
  114. #define ADV7180_IRQ1_UNLOCK 0x02
  115. #define ADV7180_REG_ISR1 0x2042
  116. #define ADV7180_REG_ICR1 0x2043
  117. #define ADV7180_REG_IMR1 0x2044
  118. #define ADV7180_REG_IMR2 0x2048
  119. #define ADV7180_IRQ3_AD_CHANGE 0x08
  120. #define ADV7180_REG_ISR3 0x204A
  121. #define ADV7180_REG_ICR3 0x204B
  122. #define ADV7180_REG_IMR3 0x204C
  123. #define ADV7180_REG_IMR4 0x2050
  124. #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
  125. #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
  126. #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
  127. #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
  128. #define ADV7180_REG_ACE_CTRL1 0x4080
  129. #define ADV7180_REG_ACE_CTRL5 0x4084
  130. #define ADV7180_REG_FLCONTROL 0x40e0
  131. #define ADV7180_FLCONTROL_FL_ENABLE 0x1
  132. #define ADV7180_REG_RST_CLAMP 0x809c
  133. #define ADV7180_REG_AGC_ADJ1 0x80b6
  134. #define ADV7180_REG_AGC_ADJ2 0x80c0
  135. #define ADV7180_CSI_REG_PWRDN 0x00
  136. #define ADV7180_CSI_PWRDN 0x80
  137. #define ADV7180_INPUT_CVBS_AIN1 0x00
  138. #define ADV7180_INPUT_CVBS_AIN2 0x01
  139. #define ADV7180_INPUT_CVBS_AIN3 0x02
  140. #define ADV7180_INPUT_CVBS_AIN4 0x03
  141. #define ADV7180_INPUT_CVBS_AIN5 0x04
  142. #define ADV7180_INPUT_CVBS_AIN6 0x05
  143. #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
  144. #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
  145. #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
  146. #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
  147. #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
  148. #define ADV7182_INPUT_CVBS_AIN1 0x00
  149. #define ADV7182_INPUT_CVBS_AIN2 0x01
  150. #define ADV7182_INPUT_CVBS_AIN3 0x02
  151. #define ADV7182_INPUT_CVBS_AIN4 0x03
  152. #define ADV7182_INPUT_CVBS_AIN5 0x04
  153. #define ADV7182_INPUT_CVBS_AIN6 0x05
  154. #define ADV7182_INPUT_CVBS_AIN7 0x06
  155. #define ADV7182_INPUT_CVBS_AIN8 0x07
  156. #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
  157. #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
  158. #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
  159. #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
  160. #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
  161. #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
  162. #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
  163. #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
  164. #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
  165. #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
  166. #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
  167. #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
  168. #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
  169. struct adv7180_state;
  170. #define ADV7180_FLAG_RESET_POWERED BIT(0)
  171. #define ADV7180_FLAG_V2 BIT(1)
  172. #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
  173. #define ADV7180_FLAG_I2P BIT(3)
  174. struct adv7180_chip_info {
  175. unsigned int flags;
  176. unsigned int valid_input_mask;
  177. int (*set_std)(struct adv7180_state *st, unsigned int std);
  178. int (*select_input)(struct adv7180_state *st, unsigned int input);
  179. int (*init)(struct adv7180_state *state);
  180. };
  181. struct adv7180_state {
  182. struct v4l2_ctrl_handler ctrl_hdl;
  183. struct v4l2_subdev sd;
  184. struct media_pad pad;
  185. struct mutex mutex; /* mutual excl. when accessing chip */
  186. int irq;
  187. struct gpio_desc *pwdn_gpio;
  188. v4l2_std_id curr_norm;
  189. bool powered;
  190. bool streaming;
  191. u8 input;
  192. struct i2c_client *client;
  193. unsigned int register_page;
  194. struct i2c_client *csi_client;
  195. struct i2c_client *vpp_client;
  196. const struct adv7180_chip_info *chip_info;
  197. enum v4l2_field field;
  198. };
  199. #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
  200. struct adv7180_state, \
  201. ctrl_hdl)->sd)
  202. static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
  203. {
  204. if (state->register_page != page) {
  205. i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
  206. page);
  207. state->register_page = page;
  208. }
  209. return 0;
  210. }
  211. static int adv7180_write(struct adv7180_state *state, unsigned int reg,
  212. unsigned int value)
  213. {
  214. lockdep_assert_held(&state->mutex);
  215. adv7180_select_page(state, reg >> 8);
  216. return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
  217. }
  218. static int adv7180_read(struct adv7180_state *state, unsigned int reg)
  219. {
  220. lockdep_assert_held(&state->mutex);
  221. adv7180_select_page(state, reg >> 8);
  222. return i2c_smbus_read_byte_data(state->client, reg & 0xff);
  223. }
  224. static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
  225. unsigned int value)
  226. {
  227. return i2c_smbus_write_byte_data(state->csi_client, reg, value);
  228. }
  229. static int adv7180_set_video_standard(struct adv7180_state *state,
  230. unsigned int std)
  231. {
  232. return state->chip_info->set_std(state, std);
  233. }
  234. static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
  235. unsigned int value)
  236. {
  237. return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
  238. }
  239. static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
  240. {
  241. /* in case V4L2_IN_ST_NO_SIGNAL */
  242. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  243. return V4L2_STD_UNKNOWN;
  244. switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
  245. case ADV7180_STATUS1_AUTOD_NTSM_M_J:
  246. return V4L2_STD_NTSC;
  247. case ADV7180_STATUS1_AUTOD_NTSC_4_43:
  248. return V4L2_STD_NTSC_443;
  249. case ADV7180_STATUS1_AUTOD_PAL_M:
  250. return V4L2_STD_PAL_M;
  251. case ADV7180_STATUS1_AUTOD_PAL_60:
  252. return V4L2_STD_PAL_60;
  253. case ADV7180_STATUS1_AUTOD_PAL_B_G:
  254. return V4L2_STD_PAL;
  255. case ADV7180_STATUS1_AUTOD_SECAM:
  256. return V4L2_STD_SECAM;
  257. case ADV7180_STATUS1_AUTOD_PAL_COMB:
  258. return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
  259. case ADV7180_STATUS1_AUTOD_SECAM_525:
  260. return V4L2_STD_SECAM;
  261. default:
  262. return V4L2_STD_UNKNOWN;
  263. }
  264. }
  265. static int v4l2_std_to_adv7180(v4l2_std_id std)
  266. {
  267. if (std == V4L2_STD_PAL_60)
  268. return ADV7180_STD_PAL60;
  269. if (std == V4L2_STD_NTSC_443)
  270. return ADV7180_STD_NTSC_443;
  271. if (std == V4L2_STD_PAL_N)
  272. return ADV7180_STD_PAL_N;
  273. if (std == V4L2_STD_PAL_M)
  274. return ADV7180_STD_PAL_M;
  275. if (std == V4L2_STD_PAL_Nc)
  276. return ADV7180_STD_PAL_COMB_N;
  277. if (std & V4L2_STD_PAL)
  278. return ADV7180_STD_PAL_BG;
  279. if (std & V4L2_STD_NTSC)
  280. return ADV7180_STD_NTSC_M;
  281. if (std & V4L2_STD_SECAM)
  282. return ADV7180_STD_PAL_SECAM;
  283. return -EINVAL;
  284. }
  285. static u32 adv7180_status_to_v4l2(u8 status1)
  286. {
  287. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  288. return V4L2_IN_ST_NO_SIGNAL;
  289. return 0;
  290. }
  291. static int __adv7180_status(struct adv7180_state *state, u32 *status,
  292. v4l2_std_id *std)
  293. {
  294. int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
  295. if (status1 < 0)
  296. return status1;
  297. if (status)
  298. *status = adv7180_status_to_v4l2(status1);
  299. if (std)
  300. *std = adv7180_std_to_v4l2(status1);
  301. return 0;
  302. }
  303. static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
  304. {
  305. return container_of(sd, struct adv7180_state, sd);
  306. }
  307. static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  308. {
  309. struct adv7180_state *state = to_state(sd);
  310. int err = mutex_lock_interruptible(&state->mutex);
  311. if (err)
  312. return err;
  313. if (state->streaming) {
  314. err = -EBUSY;
  315. goto unlock;
  316. }
  317. err = adv7180_set_video_standard(state,
  318. ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
  319. if (err)
  320. goto unlock;
  321. msleep(100);
  322. __adv7180_status(state, NULL, std);
  323. err = v4l2_std_to_adv7180(state->curr_norm);
  324. if (err < 0)
  325. goto unlock;
  326. err = adv7180_set_video_standard(state, err);
  327. unlock:
  328. mutex_unlock(&state->mutex);
  329. return err;
  330. }
  331. static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
  332. u32 output, u32 config)
  333. {
  334. struct adv7180_state *state = to_state(sd);
  335. int ret = mutex_lock_interruptible(&state->mutex);
  336. if (ret)
  337. return ret;
  338. if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
  339. ret = -EINVAL;
  340. goto out;
  341. }
  342. ret = state->chip_info->select_input(state, input);
  343. if (ret == 0)
  344. state->input = input;
  345. out:
  346. mutex_unlock(&state->mutex);
  347. return ret;
  348. }
  349. static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
  350. {
  351. struct adv7180_state *state = to_state(sd);
  352. int ret = mutex_lock_interruptible(&state->mutex);
  353. if (ret)
  354. return ret;
  355. ret = __adv7180_status(state, status, NULL);
  356. mutex_unlock(&state->mutex);
  357. return ret;
  358. }
  359. static int adv7180_program_std(struct adv7180_state *state)
  360. {
  361. int ret;
  362. ret = v4l2_std_to_adv7180(state->curr_norm);
  363. if (ret < 0)
  364. return ret;
  365. ret = adv7180_set_video_standard(state, ret);
  366. if (ret < 0)
  367. return ret;
  368. return 0;
  369. }
  370. static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  371. {
  372. struct adv7180_state *state = to_state(sd);
  373. int ret = mutex_lock_interruptible(&state->mutex);
  374. if (ret)
  375. return ret;
  376. /* Make sure we can support this std */
  377. ret = v4l2_std_to_adv7180(std);
  378. if (ret < 0)
  379. goto out;
  380. state->curr_norm = std;
  381. ret = adv7180_program_std(state);
  382. out:
  383. mutex_unlock(&state->mutex);
  384. return ret;
  385. }
  386. static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  387. {
  388. struct adv7180_state *state = to_state(sd);
  389. *norm = state->curr_norm;
  390. return 0;
  391. }
  392. static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
  393. struct v4l2_subdev_frame_interval *fi)
  394. {
  395. struct adv7180_state *state = to_state(sd);
  396. if (state->curr_norm & V4L2_STD_525_60) {
  397. fi->interval.numerator = 1001;
  398. fi->interval.denominator = 30000;
  399. } else {
  400. fi->interval.numerator = 1;
  401. fi->interval.denominator = 25;
  402. }
  403. return 0;
  404. }
  405. static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
  406. {
  407. if (!state->pwdn_gpio)
  408. return;
  409. if (on) {
  410. gpiod_set_value_cansleep(state->pwdn_gpio, 0);
  411. usleep_range(5000, 10000);
  412. } else {
  413. gpiod_set_value_cansleep(state->pwdn_gpio, 1);
  414. }
  415. }
  416. static int adv7180_set_power(struct adv7180_state *state, bool on)
  417. {
  418. u8 val;
  419. int ret;
  420. if (on)
  421. val = ADV7180_PWR_MAN_ON;
  422. else
  423. val = ADV7180_PWR_MAN_OFF;
  424. ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
  425. if (ret)
  426. return ret;
  427. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  428. if (on) {
  429. adv7180_csi_write(state, 0xDE, 0x02);
  430. adv7180_csi_write(state, 0xD2, 0xF7);
  431. adv7180_csi_write(state, 0xD8, 0x65);
  432. adv7180_csi_write(state, 0xE0, 0x09);
  433. adv7180_csi_write(state, 0x2C, 0x00);
  434. if (state->field == V4L2_FIELD_NONE)
  435. adv7180_csi_write(state, 0x1D, 0x80);
  436. adv7180_csi_write(state, 0x00, 0x00);
  437. } else {
  438. adv7180_csi_write(state, 0x00, 0x80);
  439. }
  440. }
  441. return 0;
  442. }
  443. static int adv7180_s_power(struct v4l2_subdev *sd, int on)
  444. {
  445. struct adv7180_state *state = to_state(sd);
  446. int ret;
  447. ret = mutex_lock_interruptible(&state->mutex);
  448. if (ret)
  449. return ret;
  450. ret = adv7180_set_power(state, on);
  451. if (ret == 0)
  452. state->powered = on;
  453. mutex_unlock(&state->mutex);
  454. return ret;
  455. }
  456. static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
  457. {
  458. struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
  459. struct adv7180_state *state = to_state(sd);
  460. int ret = mutex_lock_interruptible(&state->mutex);
  461. int val;
  462. if (ret)
  463. return ret;
  464. val = ctrl->val;
  465. switch (ctrl->id) {
  466. case V4L2_CID_BRIGHTNESS:
  467. ret = adv7180_write(state, ADV7180_REG_BRI, val);
  468. break;
  469. case V4L2_CID_HUE:
  470. /*Hue is inverted according to HSL chart */
  471. ret = adv7180_write(state, ADV7180_REG_HUE, -val);
  472. break;
  473. case V4L2_CID_CONTRAST:
  474. ret = adv7180_write(state, ADV7180_REG_CON, val);
  475. break;
  476. case V4L2_CID_SATURATION:
  477. /*
  478. *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
  479. *Let's not confuse the user, everybody understands saturation
  480. */
  481. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
  482. if (ret < 0)
  483. break;
  484. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
  485. break;
  486. case V4L2_CID_ADV_FAST_SWITCH:
  487. if (ctrl->val) {
  488. /* ADI required write */
  489. adv7180_write(state, 0x80d9, 0x44);
  490. adv7180_write(state, ADV7180_REG_FLCONTROL,
  491. ADV7180_FLCONTROL_FL_ENABLE);
  492. } else {
  493. /* ADI required write */
  494. adv7180_write(state, 0x80d9, 0xc4);
  495. adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
  496. }
  497. break;
  498. default:
  499. ret = -EINVAL;
  500. }
  501. mutex_unlock(&state->mutex);
  502. return ret;
  503. }
  504. static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
  505. .s_ctrl = adv7180_s_ctrl,
  506. };
  507. static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
  508. .ops = &adv7180_ctrl_ops,
  509. .id = V4L2_CID_ADV_FAST_SWITCH,
  510. .name = "Fast Switching",
  511. .type = V4L2_CTRL_TYPE_BOOLEAN,
  512. .min = 0,
  513. .max = 1,
  514. .step = 1,
  515. };
  516. static int adv7180_init_controls(struct adv7180_state *state)
  517. {
  518. v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
  519. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  520. V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
  521. ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
  522. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  523. V4L2_CID_CONTRAST, ADV7180_CON_MIN,
  524. ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
  525. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  526. V4L2_CID_SATURATION, ADV7180_SAT_MIN,
  527. ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
  528. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  529. V4L2_CID_HUE, ADV7180_HUE_MIN,
  530. ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
  531. v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
  532. state->sd.ctrl_handler = &state->ctrl_hdl;
  533. if (state->ctrl_hdl.error) {
  534. int err = state->ctrl_hdl.error;
  535. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  536. return err;
  537. }
  538. v4l2_ctrl_handler_setup(&state->ctrl_hdl);
  539. return 0;
  540. }
  541. static void adv7180_exit_controls(struct adv7180_state *state)
  542. {
  543. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  544. }
  545. static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
  546. struct v4l2_subdev_pad_config *cfg,
  547. struct v4l2_subdev_mbus_code_enum *code)
  548. {
  549. if (code->index != 0)
  550. return -EINVAL;
  551. code->code = MEDIA_BUS_FMT_UYVY8_2X8;
  552. return 0;
  553. }
  554. static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
  555. struct v4l2_mbus_framefmt *fmt)
  556. {
  557. struct adv7180_state *state = to_state(sd);
  558. fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
  559. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  560. fmt->width = 720;
  561. fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
  562. if (state->field == V4L2_FIELD_ALTERNATE)
  563. fmt->height /= 2;
  564. return 0;
  565. }
  566. static int adv7180_set_field_mode(struct adv7180_state *state)
  567. {
  568. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  569. return 0;
  570. if (state->field == V4L2_FIELD_NONE) {
  571. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  572. adv7180_csi_write(state, 0x01, 0x20);
  573. adv7180_csi_write(state, 0x02, 0x28);
  574. adv7180_csi_write(state, 0x03, 0x38);
  575. adv7180_csi_write(state, 0x04, 0x30);
  576. adv7180_csi_write(state, 0x05, 0x30);
  577. adv7180_csi_write(state, 0x06, 0x80);
  578. adv7180_csi_write(state, 0x07, 0x70);
  579. adv7180_csi_write(state, 0x08, 0x50);
  580. }
  581. adv7180_vpp_write(state, 0xa3, 0x00);
  582. adv7180_vpp_write(state, 0x5b, 0x00);
  583. adv7180_vpp_write(state, 0x55, 0x80);
  584. } else {
  585. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  586. adv7180_csi_write(state, 0x01, 0x18);
  587. adv7180_csi_write(state, 0x02, 0x18);
  588. adv7180_csi_write(state, 0x03, 0x30);
  589. adv7180_csi_write(state, 0x04, 0x20);
  590. adv7180_csi_write(state, 0x05, 0x28);
  591. adv7180_csi_write(state, 0x06, 0x40);
  592. adv7180_csi_write(state, 0x07, 0x58);
  593. adv7180_csi_write(state, 0x08, 0x30);
  594. }
  595. adv7180_vpp_write(state, 0xa3, 0x70);
  596. adv7180_vpp_write(state, 0x5b, 0x80);
  597. adv7180_vpp_write(state, 0x55, 0x00);
  598. }
  599. return 0;
  600. }
  601. static int adv7180_get_pad_format(struct v4l2_subdev *sd,
  602. struct v4l2_subdev_pad_config *cfg,
  603. struct v4l2_subdev_format *format)
  604. {
  605. struct adv7180_state *state = to_state(sd);
  606. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  607. format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
  608. } else {
  609. adv7180_mbus_fmt(sd, &format->format);
  610. format->format.field = state->field;
  611. }
  612. return 0;
  613. }
  614. static int adv7180_set_pad_format(struct v4l2_subdev *sd,
  615. struct v4l2_subdev_pad_config *cfg,
  616. struct v4l2_subdev_format *format)
  617. {
  618. struct adv7180_state *state = to_state(sd);
  619. struct v4l2_mbus_framefmt *framefmt;
  620. int ret;
  621. switch (format->format.field) {
  622. case V4L2_FIELD_NONE:
  623. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  624. break;
  625. /* fall through */
  626. default:
  627. format->format.field = V4L2_FIELD_ALTERNATE;
  628. break;
  629. }
  630. ret = adv7180_mbus_fmt(sd, &format->format);
  631. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  632. if (state->field != format->format.field) {
  633. state->field = format->format.field;
  634. adv7180_set_power(state, false);
  635. adv7180_set_field_mode(state);
  636. adv7180_set_power(state, true);
  637. }
  638. } else {
  639. framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
  640. *framefmt = format->format;
  641. }
  642. return ret;
  643. }
  644. static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
  645. struct v4l2_mbus_config *cfg)
  646. {
  647. struct adv7180_state *state = to_state(sd);
  648. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  649. cfg->type = V4L2_MBUS_CSI2;
  650. cfg->flags = V4L2_MBUS_CSI2_1_LANE |
  651. V4L2_MBUS_CSI2_CHANNEL_0 |
  652. V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
  653. } else {
  654. /*
  655. * The ADV7180 sensor supports BT.601/656 output modes.
  656. * The BT.656 is default and not yet configurable by s/w.
  657. */
  658. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  659. V4L2_MBUS_DATA_ACTIVE_HIGH;
  660. cfg->type = V4L2_MBUS_BT656;
  661. }
  662. return 0;
  663. }
  664. static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
  665. {
  666. struct adv7180_state *state = to_state(sd);
  667. if (state->curr_norm & V4L2_STD_525_60) {
  668. aspect->numerator = 11;
  669. aspect->denominator = 10;
  670. } else {
  671. aspect->numerator = 54;
  672. aspect->denominator = 59;
  673. }
  674. return 0;
  675. }
  676. static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
  677. {
  678. *norm = V4L2_STD_ALL;
  679. return 0;
  680. }
  681. static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
  682. {
  683. struct adv7180_state *state = to_state(sd);
  684. int ret;
  685. /* It's always safe to stop streaming, no need to take the lock */
  686. if (!enable) {
  687. state->streaming = enable;
  688. return 0;
  689. }
  690. /* Must wait until querystd released the lock */
  691. ret = mutex_lock_interruptible(&state->mutex);
  692. if (ret)
  693. return ret;
  694. state->streaming = enable;
  695. mutex_unlock(&state->mutex);
  696. return 0;
  697. }
  698. static int adv7180_subscribe_event(struct v4l2_subdev *sd,
  699. struct v4l2_fh *fh,
  700. struct v4l2_event_subscription *sub)
  701. {
  702. switch (sub->type) {
  703. case V4L2_EVENT_SOURCE_CHANGE:
  704. return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
  705. case V4L2_EVENT_CTRL:
  706. return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
  707. default:
  708. return -EINVAL;
  709. }
  710. }
  711. static const struct v4l2_subdev_video_ops adv7180_video_ops = {
  712. .s_std = adv7180_s_std,
  713. .g_std = adv7180_g_std,
  714. .g_frame_interval = adv7180_g_frame_interval,
  715. .querystd = adv7180_querystd,
  716. .g_input_status = adv7180_g_input_status,
  717. .s_routing = adv7180_s_routing,
  718. .g_mbus_config = adv7180_g_mbus_config,
  719. .g_pixelaspect = adv7180_g_pixelaspect,
  720. .g_tvnorms = adv7180_g_tvnorms,
  721. .s_stream = adv7180_s_stream,
  722. };
  723. static const struct v4l2_subdev_core_ops adv7180_core_ops = {
  724. .s_power = adv7180_s_power,
  725. .subscribe_event = adv7180_subscribe_event,
  726. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  727. };
  728. static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
  729. .enum_mbus_code = adv7180_enum_mbus_code,
  730. .set_fmt = adv7180_set_pad_format,
  731. .get_fmt = adv7180_get_pad_format,
  732. };
  733. static const struct v4l2_subdev_ops adv7180_ops = {
  734. .core = &adv7180_core_ops,
  735. .video = &adv7180_video_ops,
  736. .pad = &adv7180_pad_ops,
  737. };
  738. static irqreturn_t adv7180_irq(int irq, void *devid)
  739. {
  740. struct adv7180_state *state = devid;
  741. u8 isr3;
  742. mutex_lock(&state->mutex);
  743. isr3 = adv7180_read(state, ADV7180_REG_ISR3);
  744. /* clear */
  745. adv7180_write(state, ADV7180_REG_ICR3, isr3);
  746. if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
  747. static const struct v4l2_event src_ch = {
  748. .type = V4L2_EVENT_SOURCE_CHANGE,
  749. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  750. };
  751. v4l2_subdev_notify_event(&state->sd, &src_ch);
  752. }
  753. mutex_unlock(&state->mutex);
  754. return IRQ_HANDLED;
  755. }
  756. static int adv7180_init(struct adv7180_state *state)
  757. {
  758. int ret;
  759. /* ITU-R BT.656-4 compatible */
  760. ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  761. ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
  762. if (ret < 0)
  763. return ret;
  764. /* Manually set V bit end position in NTSC mode */
  765. return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
  766. ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
  767. }
  768. static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
  769. {
  770. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
  771. (std << 4) | state->input);
  772. }
  773. static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
  774. {
  775. int ret;
  776. ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
  777. if (ret < 0)
  778. return ret;
  779. ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
  780. ret |= input;
  781. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
  782. }
  783. static int adv7182_init(struct adv7180_state *state)
  784. {
  785. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  786. adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
  787. ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
  788. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  789. adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
  790. ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
  791. if (state->chip_info->flags & ADV7180_FLAG_V2) {
  792. /* ADI recommended writes for improved video quality */
  793. adv7180_write(state, 0x0080, 0x51);
  794. adv7180_write(state, 0x0081, 0x51);
  795. adv7180_write(state, 0x0082, 0x68);
  796. }
  797. /* ADI required writes */
  798. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  799. adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
  800. adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
  801. adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
  802. } else {
  803. if (state->chip_info->flags & ADV7180_FLAG_V2)
  804. adv7180_write(state,
  805. ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  806. 0x17);
  807. else
  808. adv7180_write(state,
  809. ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  810. 0x07);
  811. adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
  812. adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
  813. }
  814. adv7180_write(state, 0x0013, 0x00);
  815. return 0;
  816. }
  817. static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
  818. {
  819. return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
  820. }
  821. enum adv7182_input_type {
  822. ADV7182_INPUT_TYPE_CVBS,
  823. ADV7182_INPUT_TYPE_DIFF_CVBS,
  824. ADV7182_INPUT_TYPE_SVIDEO,
  825. ADV7182_INPUT_TYPE_YPBPR,
  826. };
  827. static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
  828. {
  829. switch (input) {
  830. case ADV7182_INPUT_CVBS_AIN1:
  831. case ADV7182_INPUT_CVBS_AIN2:
  832. case ADV7182_INPUT_CVBS_AIN3:
  833. case ADV7182_INPUT_CVBS_AIN4:
  834. case ADV7182_INPUT_CVBS_AIN5:
  835. case ADV7182_INPUT_CVBS_AIN6:
  836. case ADV7182_INPUT_CVBS_AIN7:
  837. case ADV7182_INPUT_CVBS_AIN8:
  838. return ADV7182_INPUT_TYPE_CVBS;
  839. case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
  840. case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
  841. case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
  842. case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
  843. return ADV7182_INPUT_TYPE_SVIDEO;
  844. case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
  845. case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
  846. return ADV7182_INPUT_TYPE_YPBPR;
  847. case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
  848. case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
  849. case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
  850. case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
  851. return ADV7182_INPUT_TYPE_DIFF_CVBS;
  852. default: /* Will never happen */
  853. return 0;
  854. }
  855. }
  856. /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
  857. static unsigned int adv7182_lbias_settings[][3] = {
  858. [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
  859. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  860. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  861. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  862. };
  863. static unsigned int adv7280_lbias_settings[][3] = {
  864. [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
  865. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  866. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  867. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  868. };
  869. static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
  870. {
  871. enum adv7182_input_type input_type;
  872. unsigned int *lbias;
  873. unsigned int i;
  874. int ret;
  875. ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
  876. if (ret)
  877. return ret;
  878. /* Reset clamp circuitry - ADI recommended writes */
  879. adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
  880. adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
  881. input_type = adv7182_get_input_type(input);
  882. switch (input_type) {
  883. case ADV7182_INPUT_TYPE_CVBS:
  884. case ADV7182_INPUT_TYPE_DIFF_CVBS:
  885. /* ADI recommends to use the SH1 filter */
  886. adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
  887. break;
  888. default:
  889. adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
  890. break;
  891. }
  892. if (state->chip_info->flags & ADV7180_FLAG_V2)
  893. lbias = adv7280_lbias_settings[input_type];
  894. else
  895. lbias = adv7182_lbias_settings[input_type];
  896. for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
  897. adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
  898. if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
  899. /* ADI required writes to make differential CVBS work */
  900. adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
  901. adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
  902. adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
  903. adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
  904. adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
  905. } else {
  906. adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
  907. adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
  908. adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
  909. adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
  910. adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
  911. }
  912. return 0;
  913. }
  914. static const struct adv7180_chip_info adv7180_info = {
  915. .flags = ADV7180_FLAG_RESET_POWERED,
  916. /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
  917. * all inputs and let the card driver take care of validation
  918. */
  919. .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
  920. BIT(ADV7180_INPUT_CVBS_AIN2) |
  921. BIT(ADV7180_INPUT_CVBS_AIN3) |
  922. BIT(ADV7180_INPUT_CVBS_AIN4) |
  923. BIT(ADV7180_INPUT_CVBS_AIN5) |
  924. BIT(ADV7180_INPUT_CVBS_AIN6) |
  925. BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
  926. BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
  927. BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
  928. BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  929. BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
  930. .init = adv7180_init,
  931. .set_std = adv7180_set_std,
  932. .select_input = adv7180_select_input,
  933. };
  934. static const struct adv7180_chip_info adv7182_info = {
  935. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  936. BIT(ADV7182_INPUT_CVBS_AIN2) |
  937. BIT(ADV7182_INPUT_CVBS_AIN3) |
  938. BIT(ADV7182_INPUT_CVBS_AIN4) |
  939. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  940. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  941. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  942. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  943. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
  944. .init = adv7182_init,
  945. .set_std = adv7182_set_std,
  946. .select_input = adv7182_select_input,
  947. };
  948. static const struct adv7180_chip_info adv7280_info = {
  949. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  950. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  951. BIT(ADV7182_INPUT_CVBS_AIN2) |
  952. BIT(ADV7182_INPUT_CVBS_AIN3) |
  953. BIT(ADV7182_INPUT_CVBS_AIN4) |
  954. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  955. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  956. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
  957. .init = adv7182_init,
  958. .set_std = adv7182_set_std,
  959. .select_input = adv7182_select_input,
  960. };
  961. static const struct adv7180_chip_info adv7280_m_info = {
  962. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  963. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  964. BIT(ADV7182_INPUT_CVBS_AIN2) |
  965. BIT(ADV7182_INPUT_CVBS_AIN3) |
  966. BIT(ADV7182_INPUT_CVBS_AIN4) |
  967. BIT(ADV7182_INPUT_CVBS_AIN5) |
  968. BIT(ADV7182_INPUT_CVBS_AIN6) |
  969. BIT(ADV7182_INPUT_CVBS_AIN7) |
  970. BIT(ADV7182_INPUT_CVBS_AIN8) |
  971. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  972. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  973. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  974. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  975. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  976. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
  977. .init = adv7182_init,
  978. .set_std = adv7182_set_std,
  979. .select_input = adv7182_select_input,
  980. };
  981. static const struct adv7180_chip_info adv7281_info = {
  982. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  983. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  984. BIT(ADV7182_INPUT_CVBS_AIN2) |
  985. BIT(ADV7182_INPUT_CVBS_AIN7) |
  986. BIT(ADV7182_INPUT_CVBS_AIN8) |
  987. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  988. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  989. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  990. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  991. .init = adv7182_init,
  992. .set_std = adv7182_set_std,
  993. .select_input = adv7182_select_input,
  994. };
  995. static const struct adv7180_chip_info adv7281_m_info = {
  996. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  997. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  998. BIT(ADV7182_INPUT_CVBS_AIN2) |
  999. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1000. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1001. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1002. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1003. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1004. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1005. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1006. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  1007. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1008. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1009. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1010. .init = adv7182_init,
  1011. .set_std = adv7182_set_std,
  1012. .select_input = adv7182_select_input,
  1013. };
  1014. static const struct adv7180_chip_info adv7281_ma_info = {
  1015. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  1016. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1017. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1018. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1019. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1020. BIT(ADV7182_INPUT_CVBS_AIN5) |
  1021. BIT(ADV7182_INPUT_CVBS_AIN6) |
  1022. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1023. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1024. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1025. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1026. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  1027. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1028. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  1029. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
  1030. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1031. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1032. BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
  1033. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1034. .init = adv7182_init,
  1035. .set_std = adv7182_set_std,
  1036. .select_input = adv7182_select_input,
  1037. };
  1038. static const struct adv7180_chip_info adv7282_info = {
  1039. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  1040. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1041. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1042. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1043. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1044. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1045. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1046. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1047. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1048. .init = adv7182_init,
  1049. .set_std = adv7182_set_std,
  1050. .select_input = adv7182_select_input,
  1051. };
  1052. static const struct adv7180_chip_info adv7282_m_info = {
  1053. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  1054. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1055. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1056. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1057. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1058. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1059. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1060. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1061. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1062. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1063. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1064. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1065. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1066. .init = adv7182_init,
  1067. .set_std = adv7182_set_std,
  1068. .select_input = adv7182_select_input,
  1069. };
  1070. static int init_device(struct adv7180_state *state)
  1071. {
  1072. int ret;
  1073. mutex_lock(&state->mutex);
  1074. adv7180_set_power_pin(state, true);
  1075. adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
  1076. usleep_range(5000, 10000);
  1077. ret = state->chip_info->init(state);
  1078. if (ret)
  1079. goto out_unlock;
  1080. ret = adv7180_program_std(state);
  1081. if (ret)
  1082. goto out_unlock;
  1083. adv7180_set_field_mode(state);
  1084. /* register for interrupts */
  1085. if (state->irq > 0) {
  1086. /* config the Interrupt pin to be active low */
  1087. ret = adv7180_write(state, ADV7180_REG_ICONF1,
  1088. ADV7180_ICONF1_ACTIVE_LOW |
  1089. ADV7180_ICONF1_PSYNC_ONLY);
  1090. if (ret < 0)
  1091. goto out_unlock;
  1092. ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
  1093. if (ret < 0)
  1094. goto out_unlock;
  1095. ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
  1096. if (ret < 0)
  1097. goto out_unlock;
  1098. /* enable AD change interrupts interrupts */
  1099. ret = adv7180_write(state, ADV7180_REG_IMR3,
  1100. ADV7180_IRQ3_AD_CHANGE);
  1101. if (ret < 0)
  1102. goto out_unlock;
  1103. ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
  1104. if (ret < 0)
  1105. goto out_unlock;
  1106. }
  1107. out_unlock:
  1108. mutex_unlock(&state->mutex);
  1109. return ret;
  1110. }
  1111. static int adv7180_probe(struct i2c_client *client,
  1112. const struct i2c_device_id *id)
  1113. {
  1114. struct adv7180_state *state;
  1115. struct v4l2_subdev *sd;
  1116. int ret;
  1117. /* Check if the adapter supports the needed features */
  1118. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  1119. return -EIO;
  1120. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1121. client->addr, client->adapter->name);
  1122. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  1123. if (state == NULL)
  1124. return -ENOMEM;
  1125. state->client = client;
  1126. state->field = V4L2_FIELD_ALTERNATE;
  1127. state->chip_info = (struct adv7180_chip_info *)id->driver_data;
  1128. state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
  1129. GPIOD_OUT_HIGH);
  1130. if (IS_ERR(state->pwdn_gpio)) {
  1131. ret = PTR_ERR(state->pwdn_gpio);
  1132. v4l_err(client, "request for power pin failed: %d\n", ret);
  1133. return ret;
  1134. }
  1135. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  1136. state->csi_client = i2c_new_dummy(client->adapter,
  1137. ADV7180_DEFAULT_CSI_I2C_ADDR);
  1138. if (!state->csi_client)
  1139. return -ENOMEM;
  1140. }
  1141. if (state->chip_info->flags & ADV7180_FLAG_I2P) {
  1142. state->vpp_client = i2c_new_dummy(client->adapter,
  1143. ADV7180_DEFAULT_VPP_I2C_ADDR);
  1144. if (!state->vpp_client) {
  1145. ret = -ENOMEM;
  1146. goto err_unregister_csi_client;
  1147. }
  1148. }
  1149. state->irq = client->irq;
  1150. mutex_init(&state->mutex);
  1151. state->curr_norm = V4L2_STD_NTSC;
  1152. if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
  1153. state->powered = true;
  1154. else
  1155. state->powered = false;
  1156. state->input = 0;
  1157. sd = &state->sd;
  1158. v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
  1159. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
  1160. ret = adv7180_init_controls(state);
  1161. if (ret)
  1162. goto err_unregister_vpp_client;
  1163. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  1164. sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
  1165. ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
  1166. if (ret)
  1167. goto err_free_ctrl;
  1168. ret = init_device(state);
  1169. if (ret)
  1170. goto err_media_entity_cleanup;
  1171. if (state->irq) {
  1172. ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
  1173. IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
  1174. KBUILD_MODNAME, state);
  1175. if (ret)
  1176. goto err_media_entity_cleanup;
  1177. }
  1178. ret = v4l2_async_register_subdev(sd);
  1179. if (ret)
  1180. goto err_free_irq;
  1181. return 0;
  1182. err_free_irq:
  1183. if (state->irq > 0)
  1184. free_irq(client->irq, state);
  1185. err_media_entity_cleanup:
  1186. media_entity_cleanup(&sd->entity);
  1187. err_free_ctrl:
  1188. adv7180_exit_controls(state);
  1189. err_unregister_vpp_client:
  1190. i2c_unregister_device(state->vpp_client);
  1191. err_unregister_csi_client:
  1192. i2c_unregister_device(state->csi_client);
  1193. mutex_destroy(&state->mutex);
  1194. return ret;
  1195. }
  1196. static int adv7180_remove(struct i2c_client *client)
  1197. {
  1198. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1199. struct adv7180_state *state = to_state(sd);
  1200. v4l2_async_unregister_subdev(sd);
  1201. if (state->irq > 0)
  1202. free_irq(client->irq, state);
  1203. media_entity_cleanup(&sd->entity);
  1204. adv7180_exit_controls(state);
  1205. i2c_unregister_device(state->vpp_client);
  1206. i2c_unregister_device(state->csi_client);
  1207. adv7180_set_power_pin(state, false);
  1208. mutex_destroy(&state->mutex);
  1209. return 0;
  1210. }
  1211. static const struct i2c_device_id adv7180_id[] = {
  1212. { "adv7180", (kernel_ulong_t)&adv7180_info },
  1213. { "adv7180cp", (kernel_ulong_t)&adv7180_info },
  1214. { "adv7180st", (kernel_ulong_t)&adv7180_info },
  1215. { "adv7182", (kernel_ulong_t)&adv7182_info },
  1216. { "adv7280", (kernel_ulong_t)&adv7280_info },
  1217. { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
  1218. { "adv7281", (kernel_ulong_t)&adv7281_info },
  1219. { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
  1220. { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
  1221. { "adv7282", (kernel_ulong_t)&adv7282_info },
  1222. { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
  1223. {},
  1224. };
  1225. MODULE_DEVICE_TABLE(i2c, adv7180_id);
  1226. #ifdef CONFIG_PM_SLEEP
  1227. static int adv7180_suspend(struct device *dev)
  1228. {
  1229. struct i2c_client *client = to_i2c_client(dev);
  1230. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1231. struct adv7180_state *state = to_state(sd);
  1232. return adv7180_set_power(state, false);
  1233. }
  1234. static int adv7180_resume(struct device *dev)
  1235. {
  1236. struct i2c_client *client = to_i2c_client(dev);
  1237. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1238. struct adv7180_state *state = to_state(sd);
  1239. int ret;
  1240. ret = init_device(state);
  1241. if (ret < 0)
  1242. return ret;
  1243. ret = adv7180_set_power(state, state->powered);
  1244. if (ret)
  1245. return ret;
  1246. return 0;
  1247. }
  1248. static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
  1249. #define ADV7180_PM_OPS (&adv7180_pm_ops)
  1250. #else
  1251. #define ADV7180_PM_OPS NULL
  1252. #endif
  1253. #ifdef CONFIG_OF
  1254. static const struct of_device_id adv7180_of_id[] = {
  1255. { .compatible = "adi,adv7180", },
  1256. { .compatible = "adi,adv7180cp", },
  1257. { .compatible = "adi,adv7180st", },
  1258. { .compatible = "adi,adv7182", },
  1259. { .compatible = "adi,adv7280", },
  1260. { .compatible = "adi,adv7280-m", },
  1261. { .compatible = "adi,adv7281", },
  1262. { .compatible = "adi,adv7281-m", },
  1263. { .compatible = "adi,adv7281-ma", },
  1264. { .compatible = "adi,adv7282", },
  1265. { .compatible = "adi,adv7282-m", },
  1266. { },
  1267. };
  1268. MODULE_DEVICE_TABLE(of, adv7180_of_id);
  1269. #endif
  1270. static struct i2c_driver adv7180_driver = {
  1271. .driver = {
  1272. .name = KBUILD_MODNAME,
  1273. .pm = ADV7180_PM_OPS,
  1274. .of_match_table = of_match_ptr(adv7180_of_id),
  1275. },
  1276. .probe = adv7180_probe,
  1277. .remove = adv7180_remove,
  1278. .id_table = adv7180_id,
  1279. };
  1280. module_i2c_driver(adv7180_driver);
  1281. MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
  1282. MODULE_AUTHOR("Mocean Laboratories");
  1283. MODULE_LICENSE("GPL v2");