adv7183.c 17 KB

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  1. /*
  2. * adv7183.c Analog Devices ADV7183 video decoder driver
  3. *
  4. * Copyright (c) 2011 Analog Devices Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/gpio.h>
  18. #include <linux/i2c.h>
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/slab.h>
  22. #include <linux/types.h>
  23. #include <linux/videodev2.h>
  24. #include <media/i2c/adv7183.h>
  25. #include <media/v4l2-ctrls.h>
  26. #include <media/v4l2-device.h>
  27. #include "adv7183_regs.h"
  28. struct adv7183 {
  29. struct v4l2_subdev sd;
  30. struct v4l2_ctrl_handler hdl;
  31. v4l2_std_id std; /* Current set standard */
  32. u32 input;
  33. u32 output;
  34. unsigned reset_pin;
  35. unsigned oe_pin;
  36. struct v4l2_mbus_framefmt fmt;
  37. };
  38. /* EXAMPLES USING 27 MHz CLOCK
  39. * Mode 1 CVBS Input (Composite Video on AIN5)
  40. * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
  41. */
  42. static const unsigned char adv7183_init_regs[] = {
  43. ADV7183_IN_CTRL, 0x04, /* CVBS input on AIN5 */
  44. ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
  45. ADV7183_SHAP_FILT_CTRL, 0x41, /* Set CSFM to SH1 */
  46. ADV7183_ADC_CTRL, 0x16, /* Power down ADC 1 and ADC 2 */
  47. ADV7183_CTI_DNR_CTRL_4, 0x04, /* Set DNR threshold to 4 for flat response */
  48. /* ADI recommended programming sequence */
  49. ADV7183_ADI_CTRL, 0x80,
  50. ADV7183_CTI_DNR_CTRL_4, 0x20,
  51. 0x52, 0x18,
  52. 0x58, 0xED,
  53. 0x77, 0xC5,
  54. 0x7C, 0x93,
  55. 0x7D, 0x00,
  56. 0xD0, 0x48,
  57. 0xD5, 0xA0,
  58. 0xD7, 0xEA,
  59. ADV7183_SD_SATURATION_CR, 0x3E,
  60. ADV7183_PAL_V_END, 0x3E,
  61. ADV7183_PAL_F_TOGGLE, 0x0F,
  62. ADV7183_ADI_CTRL, 0x00,
  63. };
  64. static inline struct adv7183 *to_adv7183(struct v4l2_subdev *sd)
  65. {
  66. return container_of(sd, struct adv7183, sd);
  67. }
  68. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  69. {
  70. return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
  71. }
  72. static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
  73. {
  74. struct i2c_client *client = v4l2_get_subdevdata(sd);
  75. return i2c_smbus_read_byte_data(client, reg);
  76. }
  77. static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
  78. unsigned char value)
  79. {
  80. struct i2c_client *client = v4l2_get_subdevdata(sd);
  81. return i2c_smbus_write_byte_data(client, reg, value);
  82. }
  83. static int adv7183_writeregs(struct v4l2_subdev *sd,
  84. const unsigned char *regs, unsigned int num)
  85. {
  86. unsigned char reg, data;
  87. unsigned int cnt = 0;
  88. if (num & 0x1) {
  89. v4l2_err(sd, "invalid regs array\n");
  90. return -1;
  91. }
  92. while (cnt < num) {
  93. reg = *regs++;
  94. data = *regs++;
  95. cnt += 2;
  96. adv7183_write(sd, reg, data);
  97. }
  98. return 0;
  99. }
  100. static int adv7183_log_status(struct v4l2_subdev *sd)
  101. {
  102. struct adv7183 *decoder = to_adv7183(sd);
  103. v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
  104. adv7183_read(sd, ADV7183_IN_CTRL));
  105. v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
  106. adv7183_read(sd, ADV7183_VD_SEL));
  107. v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
  108. adv7183_read(sd, ADV7183_OUT_CTRL));
  109. v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
  110. adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
  111. v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
  112. adv7183_read(sd, ADV7183_AUTO_DET_EN));
  113. v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
  114. adv7183_read(sd, ADV7183_CONTRAST));
  115. v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
  116. adv7183_read(sd, ADV7183_BRIGHTNESS));
  117. v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
  118. adv7183_read(sd, ADV7183_HUE));
  119. v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
  120. adv7183_read(sd, ADV7183_DEF_Y));
  121. v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
  122. adv7183_read(sd, ADV7183_DEF_C));
  123. v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
  124. adv7183_read(sd, ADV7183_ADI_CTRL));
  125. v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
  126. adv7183_read(sd, ADV7183_POW_MANAGE));
  127. v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
  128. adv7183_read(sd, ADV7183_STATUS_1),
  129. adv7183_read(sd, ADV7183_STATUS_2),
  130. adv7183_read(sd, ADV7183_STATUS_3));
  131. v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
  132. adv7183_read(sd, ADV7183_IDENT));
  133. v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
  134. adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
  135. v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
  136. adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
  137. v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
  138. adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
  139. adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
  140. v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
  141. adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
  142. v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
  143. adv7183_read(sd, ADV7183_ADI_CTRL_2));
  144. v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
  145. adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
  146. v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
  147. adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
  148. v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
  149. adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
  150. v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
  151. adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
  152. adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
  153. v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
  154. adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
  155. adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
  156. v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
  157. adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
  158. adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
  159. adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
  160. v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
  161. adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
  162. adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
  163. adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
  164. v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
  165. adv7183_read(sd, ADV7183_POLARITY));
  166. v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
  167. adv7183_read(sd, ADV7183_ADC_CTRL));
  168. v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
  169. adv7183_read(sd, ADV7183_SD_OFFSET_CB),
  170. adv7183_read(sd, ADV7183_SD_OFFSET_CR));
  171. v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
  172. adv7183_read(sd, ADV7183_SD_SATURATION_CB),
  173. adv7183_read(sd, ADV7183_SD_SATURATION_CR));
  174. v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
  175. adv7183_read(sd, ADV7183_DRIVE_STR));
  176. v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
  177. return 0;
  178. }
  179. static int adv7183_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
  180. {
  181. struct adv7183 *decoder = to_adv7183(sd);
  182. *std = decoder->std;
  183. return 0;
  184. }
  185. static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  186. {
  187. struct adv7183 *decoder = to_adv7183(sd);
  188. int reg;
  189. reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
  190. if (std == V4L2_STD_PAL_60)
  191. reg |= 0x60;
  192. else if (std == V4L2_STD_NTSC_443)
  193. reg |= 0x70;
  194. else if (std == V4L2_STD_PAL_N)
  195. reg |= 0x90;
  196. else if (std == V4L2_STD_PAL_M)
  197. reg |= 0xA0;
  198. else if (std == V4L2_STD_PAL_Nc)
  199. reg |= 0xC0;
  200. else if (std & V4L2_STD_PAL)
  201. reg |= 0x80;
  202. else if (std & V4L2_STD_NTSC)
  203. reg |= 0x50;
  204. else if (std & V4L2_STD_SECAM)
  205. reg |= 0xE0;
  206. else
  207. return -EINVAL;
  208. adv7183_write(sd, ADV7183_IN_CTRL, reg);
  209. decoder->std = std;
  210. return 0;
  211. }
  212. static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
  213. {
  214. int reg;
  215. reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80;
  216. adv7183_write(sd, ADV7183_POW_MANAGE, reg);
  217. /* wait 5ms before any further i2c writes are performed */
  218. usleep_range(5000, 10000);
  219. return 0;
  220. }
  221. static int adv7183_s_routing(struct v4l2_subdev *sd,
  222. u32 input, u32 output, u32 config)
  223. {
  224. struct adv7183 *decoder = to_adv7183(sd);
  225. int reg;
  226. if ((input > ADV7183_COMPONENT1) || (output > ADV7183_16BIT_OUT))
  227. return -EINVAL;
  228. if (input != decoder->input) {
  229. decoder->input = input;
  230. reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
  231. switch (input) {
  232. case ADV7183_COMPOSITE1:
  233. reg |= 0x1;
  234. break;
  235. case ADV7183_COMPOSITE2:
  236. reg |= 0x2;
  237. break;
  238. case ADV7183_COMPOSITE3:
  239. reg |= 0x3;
  240. break;
  241. case ADV7183_COMPOSITE4:
  242. reg |= 0x4;
  243. break;
  244. case ADV7183_COMPOSITE5:
  245. reg |= 0x5;
  246. break;
  247. case ADV7183_COMPOSITE6:
  248. reg |= 0xB;
  249. break;
  250. case ADV7183_COMPOSITE7:
  251. reg |= 0xC;
  252. break;
  253. case ADV7183_COMPOSITE8:
  254. reg |= 0xD;
  255. break;
  256. case ADV7183_COMPOSITE9:
  257. reg |= 0xE;
  258. break;
  259. case ADV7183_COMPOSITE10:
  260. reg |= 0xF;
  261. break;
  262. case ADV7183_SVIDEO0:
  263. reg |= 0x6;
  264. break;
  265. case ADV7183_SVIDEO1:
  266. reg |= 0x7;
  267. break;
  268. case ADV7183_SVIDEO2:
  269. reg |= 0x8;
  270. break;
  271. case ADV7183_COMPONENT0:
  272. reg |= 0x9;
  273. break;
  274. case ADV7183_COMPONENT1:
  275. reg |= 0xA;
  276. break;
  277. default:
  278. break;
  279. }
  280. adv7183_write(sd, ADV7183_IN_CTRL, reg);
  281. }
  282. if (output != decoder->output) {
  283. decoder->output = output;
  284. reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
  285. switch (output) {
  286. case ADV7183_16BIT_OUT:
  287. reg |= 0x9;
  288. break;
  289. default:
  290. reg |= 0xC;
  291. break;
  292. }
  293. adv7183_write(sd, ADV7183_OUT_CTRL, reg);
  294. }
  295. return 0;
  296. }
  297. static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
  298. {
  299. struct v4l2_subdev *sd = to_sd(ctrl);
  300. int val = ctrl->val;
  301. switch (ctrl->id) {
  302. case V4L2_CID_BRIGHTNESS:
  303. if (val < 0)
  304. val = 127 - val;
  305. adv7183_write(sd, ADV7183_BRIGHTNESS, val);
  306. break;
  307. case V4L2_CID_CONTRAST:
  308. adv7183_write(sd, ADV7183_CONTRAST, val);
  309. break;
  310. case V4L2_CID_SATURATION:
  311. adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
  312. adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
  313. break;
  314. case V4L2_CID_HUE:
  315. adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
  316. adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
  317. break;
  318. default:
  319. return -EINVAL;
  320. }
  321. return 0;
  322. }
  323. static int adv7183_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  324. {
  325. struct adv7183 *decoder = to_adv7183(sd);
  326. int reg;
  327. /* enable autodetection block */
  328. reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
  329. adv7183_write(sd, ADV7183_IN_CTRL, reg);
  330. /* wait autodetection switch */
  331. mdelay(10);
  332. /* get autodetection result */
  333. reg = adv7183_read(sd, ADV7183_STATUS_1);
  334. switch ((reg >> 0x4) & 0x7) {
  335. case 0:
  336. *std &= V4L2_STD_NTSC;
  337. break;
  338. case 1:
  339. *std &= V4L2_STD_NTSC_443;
  340. break;
  341. case 2:
  342. *std &= V4L2_STD_PAL_M;
  343. break;
  344. case 3:
  345. *std &= V4L2_STD_PAL_60;
  346. break;
  347. case 4:
  348. *std &= V4L2_STD_PAL;
  349. break;
  350. case 5:
  351. *std &= V4L2_STD_SECAM;
  352. break;
  353. case 6:
  354. *std &= V4L2_STD_PAL_Nc;
  355. break;
  356. case 7:
  357. *std &= V4L2_STD_SECAM;
  358. break;
  359. default:
  360. *std = V4L2_STD_UNKNOWN;
  361. break;
  362. }
  363. /* after std detection, write back user set std */
  364. adv7183_s_std(sd, decoder->std);
  365. return 0;
  366. }
  367. static int adv7183_g_input_status(struct v4l2_subdev *sd, u32 *status)
  368. {
  369. int reg;
  370. *status = V4L2_IN_ST_NO_SIGNAL;
  371. reg = adv7183_read(sd, ADV7183_STATUS_1);
  372. if (reg < 0)
  373. return reg;
  374. if (reg & 0x1)
  375. *status = 0;
  376. return 0;
  377. }
  378. static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
  379. struct v4l2_subdev_pad_config *cfg,
  380. struct v4l2_subdev_mbus_code_enum *code)
  381. {
  382. if (code->pad || code->index > 0)
  383. return -EINVAL;
  384. code->code = MEDIA_BUS_FMT_UYVY8_2X8;
  385. return 0;
  386. }
  387. static int adv7183_set_fmt(struct v4l2_subdev *sd,
  388. struct v4l2_subdev_pad_config *cfg,
  389. struct v4l2_subdev_format *format)
  390. {
  391. struct adv7183 *decoder = to_adv7183(sd);
  392. struct v4l2_mbus_framefmt *fmt = &format->format;
  393. if (format->pad)
  394. return -EINVAL;
  395. fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
  396. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  397. if (decoder->std & V4L2_STD_525_60) {
  398. fmt->field = V4L2_FIELD_SEQ_TB;
  399. fmt->width = 720;
  400. fmt->height = 480;
  401. } else {
  402. fmt->field = V4L2_FIELD_SEQ_BT;
  403. fmt->width = 720;
  404. fmt->height = 576;
  405. }
  406. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  407. decoder->fmt = *fmt;
  408. else
  409. cfg->try_fmt = *fmt;
  410. return 0;
  411. }
  412. static int adv7183_get_fmt(struct v4l2_subdev *sd,
  413. struct v4l2_subdev_pad_config *cfg,
  414. struct v4l2_subdev_format *format)
  415. {
  416. struct adv7183 *decoder = to_adv7183(sd);
  417. if (format->pad)
  418. return -EINVAL;
  419. format->format = decoder->fmt;
  420. return 0;
  421. }
  422. static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
  423. {
  424. struct adv7183 *decoder = to_adv7183(sd);
  425. if (enable)
  426. gpio_set_value(decoder->oe_pin, 0);
  427. else
  428. gpio_set_value(decoder->oe_pin, 1);
  429. udelay(1);
  430. return 0;
  431. }
  432. #ifdef CONFIG_VIDEO_ADV_DEBUG
  433. static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
  434. {
  435. reg->val = adv7183_read(sd, reg->reg & 0xff);
  436. reg->size = 1;
  437. return 0;
  438. }
  439. static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
  440. {
  441. adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
  442. return 0;
  443. }
  444. #endif
  445. static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
  446. .s_ctrl = adv7183_s_ctrl,
  447. };
  448. static const struct v4l2_subdev_core_ops adv7183_core_ops = {
  449. .log_status = adv7183_log_status,
  450. .reset = adv7183_reset,
  451. #ifdef CONFIG_VIDEO_ADV_DEBUG
  452. .g_register = adv7183_g_register,
  453. .s_register = adv7183_s_register,
  454. #endif
  455. };
  456. static const struct v4l2_subdev_video_ops adv7183_video_ops = {
  457. .g_std = adv7183_g_std,
  458. .s_std = adv7183_s_std,
  459. .s_routing = adv7183_s_routing,
  460. .querystd = adv7183_querystd,
  461. .g_input_status = adv7183_g_input_status,
  462. .s_stream = adv7183_s_stream,
  463. };
  464. static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
  465. .enum_mbus_code = adv7183_enum_mbus_code,
  466. .get_fmt = adv7183_get_fmt,
  467. .set_fmt = adv7183_set_fmt,
  468. };
  469. static const struct v4l2_subdev_ops adv7183_ops = {
  470. .core = &adv7183_core_ops,
  471. .video = &adv7183_video_ops,
  472. .pad = &adv7183_pad_ops,
  473. };
  474. static int adv7183_probe(struct i2c_client *client,
  475. const struct i2c_device_id *id)
  476. {
  477. struct adv7183 *decoder;
  478. struct v4l2_subdev *sd;
  479. struct v4l2_ctrl_handler *hdl;
  480. int ret;
  481. struct v4l2_subdev_format fmt = {
  482. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  483. };
  484. const unsigned *pin_array;
  485. /* Check if the adapter supports the needed features */
  486. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  487. return -EIO;
  488. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  489. client->addr << 1, client->adapter->name);
  490. pin_array = client->dev.platform_data;
  491. if (pin_array == NULL)
  492. return -EINVAL;
  493. decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
  494. if (decoder == NULL)
  495. return -ENOMEM;
  496. decoder->reset_pin = pin_array[0];
  497. decoder->oe_pin = pin_array[1];
  498. if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
  499. GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
  500. v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
  501. return -EBUSY;
  502. }
  503. if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
  504. GPIOF_OUT_INIT_HIGH,
  505. "ADV7183 Output Enable")) {
  506. v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
  507. return -EBUSY;
  508. }
  509. sd = &decoder->sd;
  510. v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
  511. hdl = &decoder->hdl;
  512. v4l2_ctrl_handler_init(hdl, 4);
  513. v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
  514. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  515. v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
  516. V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
  517. v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
  518. V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
  519. v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
  520. V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
  521. /* hook the control handler into the driver */
  522. sd->ctrl_handler = hdl;
  523. if (hdl->error) {
  524. ret = hdl->error;
  525. v4l2_ctrl_handler_free(hdl);
  526. return ret;
  527. }
  528. /* v4l2 doesn't support an autodetect standard, pick PAL as default */
  529. decoder->std = V4L2_STD_PAL;
  530. decoder->input = ADV7183_COMPOSITE4;
  531. decoder->output = ADV7183_8BIT_OUT;
  532. /* reset chip */
  533. /* reset pulse width at least 5ms */
  534. mdelay(10);
  535. gpio_set_value(decoder->reset_pin, 1);
  536. /* wait 5ms before any further i2c writes are performed */
  537. mdelay(5);
  538. adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
  539. adv7183_s_std(sd, decoder->std);
  540. fmt.format.width = 720;
  541. fmt.format.height = 576;
  542. adv7183_set_fmt(sd, NULL, &fmt);
  543. /* initialize the hardware to the default control values */
  544. ret = v4l2_ctrl_handler_setup(hdl);
  545. if (ret) {
  546. v4l2_ctrl_handler_free(hdl);
  547. return ret;
  548. }
  549. return 0;
  550. }
  551. static int adv7183_remove(struct i2c_client *client)
  552. {
  553. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  554. v4l2_device_unregister_subdev(sd);
  555. v4l2_ctrl_handler_free(sd->ctrl_handler);
  556. return 0;
  557. }
  558. static const struct i2c_device_id adv7183_id[] = {
  559. {"adv7183", 0},
  560. {},
  561. };
  562. MODULE_DEVICE_TABLE(i2c, adv7183_id);
  563. static struct i2c_driver adv7183_driver = {
  564. .driver = {
  565. .name = "adv7183",
  566. },
  567. .probe = adv7183_probe,
  568. .remove = adv7183_remove,
  569. .id_table = adv7183_id,
  570. };
  571. module_i2c_driver(adv7183_driver);
  572. MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
  573. MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
  574. MODULE_LICENSE("GPL v2");