ks0127.c 20 KB

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  1. /*
  2. * Video Capture Driver (Video for Linux 1/2)
  3. * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
  4. *
  5. * This module is an interface to the KS0127 video decoder chip.
  6. *
  7. * Copyright (C) 1999 Ryan Drake <stiletto@mediaone.net>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. *****************************************************************************
  20. *
  21. * Modified and extended by
  22. * Mike Bernson <mike@mlb.org>
  23. * Gerard v.d. Horst
  24. * Leon van Stuivenberg <l.vanstuivenberg@chello.nl>
  25. * Gernot Ziegler <gz@lysator.liu.se>
  26. *
  27. * Version History:
  28. * V1.0 Ryan Drake Initial version by Ryan Drake
  29. * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
  30. */
  31. #include <linux/init.h>
  32. #include <linux/module.h>
  33. #include <linux/delay.h>
  34. #include <linux/errno.h>
  35. #include <linux/kernel.h>
  36. #include <linux/i2c.h>
  37. #include <linux/videodev2.h>
  38. #include <linux/slab.h>
  39. #include <media/v4l2-device.h>
  40. #include "ks0127.h"
  41. MODULE_DESCRIPTION("KS0127 video decoder driver");
  42. MODULE_AUTHOR("Ryan Drake");
  43. MODULE_LICENSE("GPL");
  44. /* Addresses */
  45. #define I2C_KS0127_ADDON 0xD8
  46. #define I2C_KS0127_ONBOARD 0xDA
  47. /* ks0127 control registers */
  48. #define KS_STAT 0x00
  49. #define KS_CMDA 0x01
  50. #define KS_CMDB 0x02
  51. #define KS_CMDC 0x03
  52. #define KS_CMDD 0x04
  53. #define KS_HAVB 0x05
  54. #define KS_HAVE 0x06
  55. #define KS_HS1B 0x07
  56. #define KS_HS1E 0x08
  57. #define KS_HS2B 0x09
  58. #define KS_HS2E 0x0a
  59. #define KS_AGC 0x0b
  60. #define KS_HXTRA 0x0c
  61. #define KS_CDEM 0x0d
  62. #define KS_PORTAB 0x0e
  63. #define KS_LUMA 0x0f
  64. #define KS_CON 0x10
  65. #define KS_BRT 0x11
  66. #define KS_CHROMA 0x12
  67. #define KS_CHROMB 0x13
  68. #define KS_DEMOD 0x14
  69. #define KS_SAT 0x15
  70. #define KS_HUE 0x16
  71. #define KS_VERTIA 0x17
  72. #define KS_VERTIB 0x18
  73. #define KS_VERTIC 0x19
  74. #define KS_HSCLL 0x1a
  75. #define KS_HSCLH 0x1b
  76. #define KS_VSCLL 0x1c
  77. #define KS_VSCLH 0x1d
  78. #define KS_OFMTA 0x1e
  79. #define KS_OFMTB 0x1f
  80. #define KS_VBICTL 0x20
  81. #define KS_CCDAT2 0x21
  82. #define KS_CCDAT1 0x22
  83. #define KS_VBIL30 0x23
  84. #define KS_VBIL74 0x24
  85. #define KS_VBIL118 0x25
  86. #define KS_VBIL1512 0x26
  87. #define KS_TTFRAM 0x27
  88. #define KS_TESTA 0x28
  89. #define KS_UVOFFH 0x29
  90. #define KS_UVOFFL 0x2a
  91. #define KS_UGAIN 0x2b
  92. #define KS_VGAIN 0x2c
  93. #define KS_VAVB 0x2d
  94. #define KS_VAVE 0x2e
  95. #define KS_CTRACK 0x2f
  96. #define KS_POLCTL 0x30
  97. #define KS_REFCOD 0x31
  98. #define KS_INVALY 0x32
  99. #define KS_INVALU 0x33
  100. #define KS_INVALV 0x34
  101. #define KS_UNUSEY 0x35
  102. #define KS_UNUSEU 0x36
  103. #define KS_UNUSEV 0x37
  104. #define KS_USRSAV 0x38
  105. #define KS_USREAV 0x39
  106. #define KS_SHS1A 0x3a
  107. #define KS_SHS1B 0x3b
  108. #define KS_SHS1C 0x3c
  109. #define KS_CMDE 0x3d
  110. #define KS_VSDEL 0x3e
  111. #define KS_CMDF 0x3f
  112. #define KS_GAMMA0 0x40
  113. #define KS_GAMMA1 0x41
  114. #define KS_GAMMA2 0x42
  115. #define KS_GAMMA3 0x43
  116. #define KS_GAMMA4 0x44
  117. #define KS_GAMMA5 0x45
  118. #define KS_GAMMA6 0x46
  119. #define KS_GAMMA7 0x47
  120. #define KS_GAMMA8 0x48
  121. #define KS_GAMMA9 0x49
  122. #define KS_GAMMA10 0x4a
  123. #define KS_GAMMA11 0x4b
  124. #define KS_GAMMA12 0x4c
  125. #define KS_GAMMA13 0x4d
  126. #define KS_GAMMA14 0x4e
  127. #define KS_GAMMA15 0x4f
  128. #define KS_GAMMA16 0x50
  129. #define KS_GAMMA17 0x51
  130. #define KS_GAMMA18 0x52
  131. #define KS_GAMMA19 0x53
  132. #define KS_GAMMA20 0x54
  133. #define KS_GAMMA21 0x55
  134. #define KS_GAMMA22 0x56
  135. #define KS_GAMMA23 0x57
  136. #define KS_GAMMA24 0x58
  137. #define KS_GAMMA25 0x59
  138. #define KS_GAMMA26 0x5a
  139. #define KS_GAMMA27 0x5b
  140. #define KS_GAMMA28 0x5c
  141. #define KS_GAMMA29 0x5d
  142. #define KS_GAMMA30 0x5e
  143. #define KS_GAMMA31 0x5f
  144. #define KS_GAMMAD0 0x60
  145. #define KS_GAMMAD1 0x61
  146. #define KS_GAMMAD2 0x62
  147. #define KS_GAMMAD3 0x63
  148. #define KS_GAMMAD4 0x64
  149. #define KS_GAMMAD5 0x65
  150. #define KS_GAMMAD6 0x66
  151. #define KS_GAMMAD7 0x67
  152. #define KS_GAMMAD8 0x68
  153. #define KS_GAMMAD9 0x69
  154. #define KS_GAMMAD10 0x6a
  155. #define KS_GAMMAD11 0x6b
  156. #define KS_GAMMAD12 0x6c
  157. #define KS_GAMMAD13 0x6d
  158. #define KS_GAMMAD14 0x6e
  159. #define KS_GAMMAD15 0x6f
  160. #define KS_GAMMAD16 0x70
  161. #define KS_GAMMAD17 0x71
  162. #define KS_GAMMAD18 0x72
  163. #define KS_GAMMAD19 0x73
  164. #define KS_GAMMAD20 0x74
  165. #define KS_GAMMAD21 0x75
  166. #define KS_GAMMAD22 0x76
  167. #define KS_GAMMAD23 0x77
  168. #define KS_GAMMAD24 0x78
  169. #define KS_GAMMAD25 0x79
  170. #define KS_GAMMAD26 0x7a
  171. #define KS_GAMMAD27 0x7b
  172. #define KS_GAMMAD28 0x7c
  173. #define KS_GAMMAD29 0x7d
  174. #define KS_GAMMAD30 0x7e
  175. #define KS_GAMMAD31 0x7f
  176. /****************************************************************************
  177. * mga_dev : represents one ks0127 chip.
  178. ****************************************************************************/
  179. struct adjust {
  180. int contrast;
  181. int bright;
  182. int hue;
  183. int ugain;
  184. int vgain;
  185. };
  186. struct ks0127 {
  187. struct v4l2_subdev sd;
  188. v4l2_std_id norm;
  189. u8 regs[256];
  190. };
  191. static inline struct ks0127 *to_ks0127(struct v4l2_subdev *sd)
  192. {
  193. return container_of(sd, struct ks0127, sd);
  194. }
  195. static int debug; /* insmod parameter */
  196. module_param(debug, int, 0);
  197. MODULE_PARM_DESC(debug, "Debug output");
  198. static u8 reg_defaults[64];
  199. static void init_reg_defaults(void)
  200. {
  201. static int initialized;
  202. u8 *table = reg_defaults;
  203. if (initialized)
  204. return;
  205. initialized = 1;
  206. table[KS_CMDA] = 0x2c; /* VSE=0, CCIR 601, autodetect standard */
  207. table[KS_CMDB] = 0x12; /* VALIGN=0, AGC control and input */
  208. table[KS_CMDC] = 0x00; /* Test options */
  209. /* clock & input select, write 1 to PORTA */
  210. table[KS_CMDD] = 0x01;
  211. table[KS_HAVB] = 0x00; /* HAV Start Control */
  212. table[KS_HAVE] = 0x00; /* HAV End Control */
  213. table[KS_HS1B] = 0x10; /* HS1 Start Control */
  214. table[KS_HS1E] = 0x00; /* HS1 End Control */
  215. table[KS_HS2B] = 0x00; /* HS2 Start Control */
  216. table[KS_HS2E] = 0x00; /* HS2 End Control */
  217. table[KS_AGC] = 0x53; /* Manual setting for AGC */
  218. table[KS_HXTRA] = 0x00; /* Extra Bits for HAV and HS1/2 */
  219. table[KS_CDEM] = 0x00; /* Chroma Demodulation Control */
  220. table[KS_PORTAB] = 0x0f; /* port B is input, port A output GPPORT */
  221. table[KS_LUMA] = 0x01; /* Luma control */
  222. table[KS_CON] = 0x00; /* Contrast Control */
  223. table[KS_BRT] = 0x00; /* Brightness Control */
  224. table[KS_CHROMA] = 0x2a; /* Chroma control A */
  225. table[KS_CHROMB] = 0x90; /* Chroma control B */
  226. table[KS_DEMOD] = 0x00; /* Chroma Demodulation Control & Status */
  227. table[KS_SAT] = 0x00; /* Color Saturation Control*/
  228. table[KS_HUE] = 0x00; /* Hue Control */
  229. table[KS_VERTIA] = 0x00; /* Vertical Processing Control A */
  230. /* Vertical Processing Control B, luma 1 line delayed */
  231. table[KS_VERTIB] = 0x12;
  232. table[KS_VERTIC] = 0x0b; /* Vertical Processing Control C */
  233. table[KS_HSCLL] = 0x00; /* Horizontal Scaling Ratio Low */
  234. table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */
  235. table[KS_VSCLL] = 0x00; /* Vertical Scaling Ratio Low */
  236. table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */
  237. /* 16 bit YCbCr 4:2:2 output; I can't make the bt866 like 8 bit /Sam */
  238. table[KS_OFMTA] = 0x30;
  239. table[KS_OFMTB] = 0x00; /* Output Control B */
  240. /* VBI Decoder Control; 4bit fmt: avoid Y overflow */
  241. table[KS_VBICTL] = 0x5d;
  242. table[KS_CCDAT2] = 0x00; /* Read Only register */
  243. table[KS_CCDAT1] = 0x00; /* Read Only register */
  244. table[KS_VBIL30] = 0xa8; /* VBI data decoding options */
  245. table[KS_VBIL74] = 0xaa; /* VBI data decoding options */
  246. table[KS_VBIL118] = 0x2a; /* VBI data decoding options */
  247. table[KS_VBIL1512] = 0x00; /* VBI data decoding options */
  248. table[KS_TTFRAM] = 0x00; /* Teletext frame alignment pattern */
  249. table[KS_TESTA] = 0x00; /* test register, shouldn't be written */
  250. table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */
  251. table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */
  252. table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */
  253. table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */
  254. table[KS_VAVB] = 0x07; /* VAV Begin */
  255. table[KS_VAVE] = 0x00; /* VAV End */
  256. table[KS_CTRACK] = 0x00; /* Chroma Tracking Control */
  257. table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */
  258. table[KS_REFCOD] = 0x80; /* Reference Code Insertion Control */
  259. table[KS_INVALY] = 0x10; /* Invalid Y Code */
  260. table[KS_INVALU] = 0x80; /* Invalid U Code */
  261. table[KS_INVALV] = 0x80; /* Invalid V Code */
  262. table[KS_UNUSEY] = 0x10; /* Unused Y Code */
  263. table[KS_UNUSEU] = 0x80; /* Unused U Code */
  264. table[KS_UNUSEV] = 0x80; /* Unused V Code */
  265. table[KS_USRSAV] = 0x00; /* reserved */
  266. table[KS_USREAV] = 0x00; /* reserved */
  267. table[KS_SHS1A] = 0x00; /* User Defined SHS1 A */
  268. /* User Defined SHS1 B, ALT656=1 on 0127B */
  269. table[KS_SHS1B] = 0x80;
  270. table[KS_SHS1C] = 0x00; /* User Defined SHS1 C */
  271. table[KS_CMDE] = 0x00; /* Command Register E */
  272. table[KS_VSDEL] = 0x00; /* VS Delay Control */
  273. /* Command Register F, update -immediately- */
  274. /* (there might come no vsync)*/
  275. table[KS_CMDF] = 0x02;
  276. }
  277. /* We need to manually read because of a bug in the KS0127 chip.
  278. *
  279. * An explanation from kayork@mail.utexas.edu:
  280. *
  281. * During I2C reads, the KS0127 only samples for a stop condition
  282. * during the place where the acknowledge bit should be. Any standard
  283. * I2C implementation (correctly) throws in another clock transition
  284. * at the 9th bit, and the KS0127 will not recognize the stop condition
  285. * and will continue to clock out data.
  286. *
  287. * So we have to do the read ourself. Big deal.
  288. * workaround in i2c-algo-bit
  289. */
  290. static u8 ks0127_read(struct v4l2_subdev *sd, u8 reg)
  291. {
  292. struct i2c_client *client = v4l2_get_subdevdata(sd);
  293. char val = 0;
  294. struct i2c_msg msgs[] = {
  295. {
  296. .addr = client->addr,
  297. .len = sizeof(reg),
  298. .buf = &reg
  299. },
  300. {
  301. .addr = client->addr,
  302. .flags = I2C_M_RD | I2C_M_NO_RD_ACK,
  303. .len = sizeof(val),
  304. .buf = &val
  305. }
  306. };
  307. int ret;
  308. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  309. if (ret != ARRAY_SIZE(msgs))
  310. v4l2_dbg(1, debug, sd, "read error\n");
  311. return val;
  312. }
  313. static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  314. {
  315. struct i2c_client *client = v4l2_get_subdevdata(sd);
  316. struct ks0127 *ks = to_ks0127(sd);
  317. char msg[] = { reg, val };
  318. if (i2c_master_send(client, msg, sizeof(msg)) != sizeof(msg))
  319. v4l2_dbg(1, debug, sd, "write error\n");
  320. ks->regs[reg] = val;
  321. }
  322. /* generic bit-twiddling */
  323. static void ks0127_and_or(struct v4l2_subdev *sd, u8 reg, u8 and_v, u8 or_v)
  324. {
  325. struct ks0127 *ks = to_ks0127(sd);
  326. u8 val = ks->regs[reg];
  327. val = (val & and_v) | or_v;
  328. ks0127_write(sd, reg, val);
  329. }
  330. /****************************************************************************
  331. * ks0127 private api
  332. ****************************************************************************/
  333. static void ks0127_init(struct v4l2_subdev *sd)
  334. {
  335. u8 *table = reg_defaults;
  336. int i;
  337. v4l2_dbg(1, debug, sd, "reset\n");
  338. msleep(1);
  339. /* initialize all registers to known values */
  340. /* (except STAT, 0x21, 0x22, TEST and 0x38,0x39) */
  341. for (i = 1; i < 33; i++)
  342. ks0127_write(sd, i, table[i]);
  343. for (i = 35; i < 40; i++)
  344. ks0127_write(sd, i, table[i]);
  345. for (i = 41; i < 56; i++)
  346. ks0127_write(sd, i, table[i]);
  347. for (i = 58; i < 64; i++)
  348. ks0127_write(sd, i, table[i]);
  349. if ((ks0127_read(sd, KS_STAT) & 0x80) == 0) {
  350. v4l2_dbg(1, debug, sd, "ks0122s found\n");
  351. return;
  352. }
  353. switch (ks0127_read(sd, KS_CMDE) & 0x0f) {
  354. case 0:
  355. v4l2_dbg(1, debug, sd, "ks0127 found\n");
  356. break;
  357. case 9:
  358. v4l2_dbg(1, debug, sd, "ks0127B Revision A found\n");
  359. break;
  360. default:
  361. v4l2_dbg(1, debug, sd, "unknown revision\n");
  362. break;
  363. }
  364. }
  365. static int ks0127_s_routing(struct v4l2_subdev *sd,
  366. u32 input, u32 output, u32 config)
  367. {
  368. struct ks0127 *ks = to_ks0127(sd);
  369. switch (input) {
  370. case KS_INPUT_COMPOSITE_1:
  371. case KS_INPUT_COMPOSITE_2:
  372. case KS_INPUT_COMPOSITE_3:
  373. case KS_INPUT_COMPOSITE_4:
  374. case KS_INPUT_COMPOSITE_5:
  375. case KS_INPUT_COMPOSITE_6:
  376. v4l2_dbg(1, debug, sd,
  377. "s_routing %d: Composite\n", input);
  378. /* autodetect 50/60 Hz */
  379. ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);
  380. /* VSE=0 */
  381. ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);
  382. /* set input line */
  383. ks0127_and_or(sd, KS_CMDB, 0xb0, input);
  384. /* non-freerunning mode */
  385. ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);
  386. /* analog input */
  387. ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);
  388. /* enable chroma demodulation */
  389. ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);
  390. /* chroma trap, HYBWR=1 */
  391. ks0127_and_or(sd, KS_LUMA, 0x00,
  392. (reg_defaults[KS_LUMA])|0x0c);
  393. /* scaler fullbw, luma comb off */
  394. ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);
  395. /* manual chroma comb .25 .5 .25 */
  396. ks0127_and_or(sd, KS_VERTIC, 0x0f, 0x90);
  397. /* chroma path delay */
  398. ks0127_and_or(sd, KS_CHROMB, 0x0f, 0x90);
  399. ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);
  400. ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);
  401. ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);
  402. ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);
  403. break;
  404. case KS_INPUT_SVIDEO_1:
  405. case KS_INPUT_SVIDEO_2:
  406. case KS_INPUT_SVIDEO_3:
  407. v4l2_dbg(1, debug, sd,
  408. "s_routing %d: S-Video\n", input);
  409. /* autodetect 50/60 Hz */
  410. ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);
  411. /* VSE=0 */
  412. ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);
  413. /* set input line */
  414. ks0127_and_or(sd, KS_CMDB, 0xb0, input);
  415. /* non-freerunning mode */
  416. ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);
  417. /* analog input */
  418. ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);
  419. /* enable chroma demodulation */
  420. ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);
  421. ks0127_and_or(sd, KS_LUMA, 0x00,
  422. reg_defaults[KS_LUMA]);
  423. /* disable luma comb */
  424. ks0127_and_or(sd, KS_VERTIA, 0x08,
  425. (reg_defaults[KS_VERTIA]&0xf0)|0x01);
  426. ks0127_and_or(sd, KS_VERTIC, 0x0f,
  427. reg_defaults[KS_VERTIC]&0xf0);
  428. ks0127_and_or(sd, KS_CHROMB, 0x0f,
  429. reg_defaults[KS_CHROMB]&0xf0);
  430. ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);
  431. ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);
  432. ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);
  433. ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);
  434. break;
  435. case KS_INPUT_YUV656:
  436. v4l2_dbg(1, debug, sd, "s_routing 15: YUV656\n");
  437. if (ks->norm & V4L2_STD_525_60)
  438. /* force 60 Hz */
  439. ks0127_and_or(sd, KS_CMDA, 0xfc, 0x03);
  440. else
  441. /* force 50 Hz */
  442. ks0127_and_or(sd, KS_CMDA, 0xfc, 0x02);
  443. ks0127_and_or(sd, KS_CMDA, 0xff, 0x40); /* VSE=1 */
  444. /* set input line and VALIGN */
  445. ks0127_and_or(sd, KS_CMDB, 0xb0, (input | 0x40));
  446. /* freerunning mode, */
  447. /* TSTGEN = 1 TSTGFR=11 TSTGPH=0 TSTGPK=0 VMEM=1*/
  448. ks0127_and_or(sd, KS_CMDC, 0x70, 0x87);
  449. /* digital input, SYNDIR = 0 INPSL=01 CLKDIR=0 EAV=0 */
  450. ks0127_and_or(sd, KS_CMDD, 0x03, 0x08);
  451. /* disable chroma demodulation */
  452. ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x30);
  453. /* HYPK =01 CTRAP = 0 HYBWR=0 PED=1 RGBH=1 UNIT=1 */
  454. ks0127_and_or(sd, KS_LUMA, 0x00, 0x71);
  455. ks0127_and_or(sd, KS_VERTIC, 0x0f,
  456. reg_defaults[KS_VERTIC]&0xf0);
  457. /* scaler fullbw, luma comb off */
  458. ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);
  459. ks0127_and_or(sd, KS_CHROMB, 0x0f,
  460. reg_defaults[KS_CHROMB]&0xf0);
  461. ks0127_and_or(sd, KS_CON, 0x00, 0x00);
  462. ks0127_and_or(sd, KS_BRT, 0x00, 32); /* spec: 34 */
  463. /* spec: 229 (e5) */
  464. ks0127_and_or(sd, KS_SAT, 0x00, 0xe8);
  465. ks0127_and_or(sd, KS_HUE, 0x00, 0);
  466. ks0127_and_or(sd, KS_UGAIN, 0x00, 238);
  467. ks0127_and_or(sd, KS_VGAIN, 0x00, 0x00);
  468. /*UOFF:0x30, VOFF:0x30, TSTCGN=1 */
  469. ks0127_and_or(sd, KS_UVOFFH, 0x00, 0x4f);
  470. ks0127_and_or(sd, KS_UVOFFL, 0x00, 0x00);
  471. break;
  472. default:
  473. v4l2_dbg(1, debug, sd,
  474. "s_routing: Unknown input %d\n", input);
  475. break;
  476. }
  477. /* hack: CDMLPF sometimes spontaneously switches on; */
  478. /* force back off */
  479. ks0127_write(sd, KS_DEMOD, reg_defaults[KS_DEMOD]);
  480. return 0;
  481. }
  482. static int ks0127_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  483. {
  484. struct ks0127 *ks = to_ks0127(sd);
  485. /* Set to automatic SECAM/Fsc mode */
  486. ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);
  487. ks->norm = std;
  488. if (std & V4L2_STD_NTSC) {
  489. v4l2_dbg(1, debug, sd,
  490. "s_std: NTSC_M\n");
  491. ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);
  492. } else if (std & V4L2_STD_PAL_N) {
  493. v4l2_dbg(1, debug, sd,
  494. "s_std: NTSC_N (fixme)\n");
  495. ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);
  496. } else if (std & V4L2_STD_PAL) {
  497. v4l2_dbg(1, debug, sd,
  498. "s_std: PAL_N\n");
  499. ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);
  500. } else if (std & V4L2_STD_PAL_M) {
  501. v4l2_dbg(1, debug, sd,
  502. "s_std: PAL_M (fixme)\n");
  503. ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);
  504. } else if (std & V4L2_STD_SECAM) {
  505. v4l2_dbg(1, debug, sd,
  506. "s_std: SECAM\n");
  507. /* set to secam autodetection */
  508. ks0127_and_or(sd, KS_CHROMA, 0xdf, 0x20);
  509. ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);
  510. schedule_timeout_interruptible(HZ/10+1);
  511. /* did it autodetect? */
  512. if (!(ks0127_read(sd, KS_DEMOD) & 0x40))
  513. /* force to secam mode */
  514. ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x0f);
  515. } else {
  516. v4l2_dbg(1, debug, sd, "s_std: Unknown norm %llx\n",
  517. (unsigned long long)std);
  518. }
  519. return 0;
  520. }
  521. static int ks0127_s_stream(struct v4l2_subdev *sd, int enable)
  522. {
  523. v4l2_dbg(1, debug, sd, "s_stream(%d)\n", enable);
  524. if (enable) {
  525. /* All output pins on */
  526. ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x30);
  527. /* Obey the OEN pin */
  528. ks0127_and_or(sd, KS_CDEM, 0x7f, 0x00);
  529. } else {
  530. /* Video output pins off */
  531. ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x00);
  532. /* Ignore the OEN pin */
  533. ks0127_and_or(sd, KS_CDEM, 0x7f, 0x80);
  534. }
  535. return 0;
  536. }
  537. static int ks0127_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
  538. {
  539. int stat = V4L2_IN_ST_NO_SIGNAL;
  540. u8 status;
  541. v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;
  542. status = ks0127_read(sd, KS_STAT);
  543. if (!(status & 0x20)) /* NOVID not set */
  544. stat = 0;
  545. if (!(status & 0x01)) { /* CLOCK set */
  546. stat |= V4L2_IN_ST_NO_COLOR;
  547. std = V4L2_STD_UNKNOWN;
  548. } else {
  549. if ((status & 0x08)) /* PALDET set */
  550. std &= V4L2_STD_PAL;
  551. else
  552. std &= V4L2_STD_NTSC;
  553. }
  554. if ((status & 0x10)) /* PALDET set */
  555. std &= V4L2_STD_525_60;
  556. else
  557. std &= V4L2_STD_625_50;
  558. if (pstd)
  559. *pstd = std;
  560. if (pstatus)
  561. *pstatus = stat;
  562. return 0;
  563. }
  564. static int ks0127_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  565. {
  566. v4l2_dbg(1, debug, sd, "querystd\n");
  567. return ks0127_status(sd, NULL, std);
  568. }
  569. static int ks0127_g_input_status(struct v4l2_subdev *sd, u32 *status)
  570. {
  571. v4l2_dbg(1, debug, sd, "g_input_status\n");
  572. return ks0127_status(sd, status, NULL);
  573. }
  574. /* ----------------------------------------------------------------------- */
  575. static const struct v4l2_subdev_video_ops ks0127_video_ops = {
  576. .s_std = ks0127_s_std,
  577. .s_routing = ks0127_s_routing,
  578. .s_stream = ks0127_s_stream,
  579. .querystd = ks0127_querystd,
  580. .g_input_status = ks0127_g_input_status,
  581. };
  582. static const struct v4l2_subdev_ops ks0127_ops = {
  583. .video = &ks0127_video_ops,
  584. };
  585. /* ----------------------------------------------------------------------- */
  586. static int ks0127_probe(struct i2c_client *client, const struct i2c_device_id *id)
  587. {
  588. struct ks0127 *ks;
  589. struct v4l2_subdev *sd;
  590. v4l_info(client, "%s chip found @ 0x%x (%s)\n",
  591. client->addr == (I2C_KS0127_ADDON >> 1) ? "addon" : "on-board",
  592. client->addr << 1, client->adapter->name);
  593. ks = devm_kzalloc(&client->dev, sizeof(*ks), GFP_KERNEL);
  594. if (ks == NULL)
  595. return -ENOMEM;
  596. sd = &ks->sd;
  597. v4l2_i2c_subdev_init(sd, client, &ks0127_ops);
  598. /* power up */
  599. init_reg_defaults();
  600. ks0127_write(sd, KS_CMDA, 0x2c);
  601. mdelay(10);
  602. /* reset the device */
  603. ks0127_init(sd);
  604. return 0;
  605. }
  606. static int ks0127_remove(struct i2c_client *client)
  607. {
  608. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  609. v4l2_device_unregister_subdev(sd);
  610. ks0127_write(sd, KS_OFMTA, 0x20); /* tristate */
  611. ks0127_write(sd, KS_CMDA, 0x2c | 0x80); /* power down */
  612. return 0;
  613. }
  614. static const struct i2c_device_id ks0127_id[] = {
  615. { "ks0127", 0 },
  616. { "ks0127b", 0 },
  617. { "ks0122s", 0 },
  618. { }
  619. };
  620. MODULE_DEVICE_TABLE(i2c, ks0127_id);
  621. static struct i2c_driver ks0127_driver = {
  622. .driver = {
  623. .name = "ks0127",
  624. },
  625. .probe = ks0127_probe,
  626. .remove = ks0127_remove,
  627. .id_table = ks0127_id,
  628. };
  629. module_i2c_driver(ks0127_driver);