ov772x.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ov772x Camera Driver
  4. *
  5. * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
  6. *
  7. * Copyright (C) 2008 Renesas Solutions Corp.
  8. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  9. *
  10. * Based on ov7670 and soc_camera_platform driver,
  11. *
  12. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  13. * Copyright (C) 2008 Magnus Damm
  14. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/delay.h>
  18. #include <linux/gpio/consumer.h>
  19. #include <linux/i2c.h>
  20. #include <linux/init.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/slab.h>
  24. #include <linux/v4l2-mediabus.h>
  25. #include <linux/videodev2.h>
  26. #include <media/i2c/ov772x.h>
  27. #include <media/v4l2-ctrls.h>
  28. #include <media/v4l2-device.h>
  29. #include <media/v4l2-image-sizes.h>
  30. #include <media/v4l2-subdev.h>
  31. /*
  32. * register offset
  33. */
  34. #define GAIN 0x00 /* AGC - Gain control gain setting */
  35. #define BLUE 0x01 /* AWB - Blue channel gain setting */
  36. #define RED 0x02 /* AWB - Red channel gain setting */
  37. #define GREEN 0x03 /* AWB - Green channel gain setting */
  38. #define COM1 0x04 /* Common control 1 */
  39. #define BAVG 0x05 /* U/B Average Level */
  40. #define GAVG 0x06 /* Y/Gb Average Level */
  41. #define RAVG 0x07 /* V/R Average Level */
  42. #define AECH 0x08 /* Exposure Value - AEC MSBs */
  43. #define COM2 0x09 /* Common control 2 */
  44. #define PID 0x0A /* Product ID Number MSB */
  45. #define VER 0x0B /* Product ID Number LSB */
  46. #define COM3 0x0C /* Common control 3 */
  47. #define COM4 0x0D /* Common control 4 */
  48. #define COM5 0x0E /* Common control 5 */
  49. #define COM6 0x0F /* Common control 6 */
  50. #define AEC 0x10 /* Exposure Value */
  51. #define CLKRC 0x11 /* Internal clock */
  52. #define COM7 0x12 /* Common control 7 */
  53. #define COM8 0x13 /* Common control 8 */
  54. #define COM9 0x14 /* Common control 9 */
  55. #define COM10 0x15 /* Common control 10 */
  56. #define REG16 0x16 /* Register 16 */
  57. #define HSTART 0x17 /* Horizontal sensor size */
  58. #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
  59. #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
  60. #define VSIZE 0x1A /* Vertical sensor size */
  61. #define PSHFT 0x1B /* Data format - pixel delay select */
  62. #define MIDH 0x1C /* Manufacturer ID byte - high */
  63. #define MIDL 0x1D /* Manufacturer ID byte - low */
  64. #define LAEC 0x1F /* Fine AEC value */
  65. #define COM11 0x20 /* Common control 11 */
  66. #define BDBASE 0x22 /* Banding filter Minimum AEC value */
  67. #define DBSTEP 0x23 /* Banding filter Maximum Setp */
  68. #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
  69. #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
  70. #define VPT 0x26 /* AGC/AEC Fast mode operating region */
  71. #define REG28 0x28 /* Register 28 */
  72. #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
  73. #define EXHCH 0x2A /* Dummy pixel insert MSB */
  74. #define EXHCL 0x2B /* Dummy pixel insert LSB */
  75. #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
  76. #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
  77. #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
  78. #define YAVE 0x2F /* Y/G Channel Average value */
  79. #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
  80. #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
  81. #define HREF 0x32 /* Image start and size control */
  82. #define DM_LNL 0x33 /* Dummy line low 8 bits */
  83. #define DM_LNH 0x34 /* Dummy line high 8 bits */
  84. #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
  85. #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
  86. #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
  87. #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
  88. #define OFF_B 0x39 /* Analog process B channel offset value */
  89. #define OFF_R 0x3A /* Analog process R channel offset value */
  90. #define OFF_GB 0x3B /* Analog process Gb channel offset value */
  91. #define OFF_GR 0x3C /* Analog process Gr channel offset value */
  92. #define COM12 0x3D /* Common control 12 */
  93. #define COM13 0x3E /* Common control 13 */
  94. #define COM14 0x3F /* Common control 14 */
  95. #define COM15 0x40 /* Common control 15*/
  96. #define COM16 0x41 /* Common control 16 */
  97. #define TGT_B 0x42 /* BLC blue channel target value */
  98. #define TGT_R 0x43 /* BLC red channel target value */
  99. #define TGT_GB 0x44 /* BLC Gb channel target value */
  100. #define TGT_GR 0x45 /* BLC Gr channel target value */
  101. /* for ov7720 */
  102. #define LCC0 0x46 /* Lens correction control 0 */
  103. #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
  104. #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
  105. #define LCC3 0x49 /* Lens correction option 3 */
  106. #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
  107. #define LCC5 0x4B /* Lens correction option 5 */
  108. #define LCC6 0x4C /* Lens correction option 6 */
  109. /* for ov7725 */
  110. #define LC_CTR 0x46 /* Lens correction control */
  111. #define LC_XC 0x47 /* X coordinate of lens correction center relative */
  112. #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
  113. #define LC_COEF 0x49 /* Lens correction coefficient */
  114. #define LC_RADI 0x4A /* Lens correction radius */
  115. #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
  116. #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
  117. #define FIXGAIN 0x4D /* Analog fix gain amplifer */
  118. #define AREF0 0x4E /* Sensor reference control */
  119. #define AREF1 0x4F /* Sensor reference current control */
  120. #define AREF2 0x50 /* Analog reference control */
  121. #define AREF3 0x51 /* ADC reference control */
  122. #define AREF4 0x52 /* ADC reference control */
  123. #define AREF5 0x53 /* ADC reference control */
  124. #define AREF6 0x54 /* Analog reference control */
  125. #define AREF7 0x55 /* Analog reference control */
  126. #define UFIX 0x60 /* U channel fixed value output */
  127. #define VFIX 0x61 /* V channel fixed value output */
  128. #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
  129. #define AWB_CTRL0 0x63 /* AWB control byte 0 */
  130. #define DSP_CTRL1 0x64 /* DSP control byte 1 */
  131. #define DSP_CTRL2 0x65 /* DSP control byte 2 */
  132. #define DSP_CTRL3 0x66 /* DSP control byte 3 */
  133. #define DSP_CTRL4 0x67 /* DSP control byte 4 */
  134. #define AWB_BIAS 0x68 /* AWB BLC level clip */
  135. #define AWB_CTRL1 0x69 /* AWB control 1 */
  136. #define AWB_CTRL2 0x6A /* AWB control 2 */
  137. #define AWB_CTRL3 0x6B /* AWB control 3 */
  138. #define AWB_CTRL4 0x6C /* AWB control 4 */
  139. #define AWB_CTRL5 0x6D /* AWB control 5 */
  140. #define AWB_CTRL6 0x6E /* AWB control 6 */
  141. #define AWB_CTRL7 0x6F /* AWB control 7 */
  142. #define AWB_CTRL8 0x70 /* AWB control 8 */
  143. #define AWB_CTRL9 0x71 /* AWB control 9 */
  144. #define AWB_CTRL10 0x72 /* AWB control 10 */
  145. #define AWB_CTRL11 0x73 /* AWB control 11 */
  146. #define AWB_CTRL12 0x74 /* AWB control 12 */
  147. #define AWB_CTRL13 0x75 /* AWB control 13 */
  148. #define AWB_CTRL14 0x76 /* AWB control 14 */
  149. #define AWB_CTRL15 0x77 /* AWB control 15 */
  150. #define AWB_CTRL16 0x78 /* AWB control 16 */
  151. #define AWB_CTRL17 0x79 /* AWB control 17 */
  152. #define AWB_CTRL18 0x7A /* AWB control 18 */
  153. #define AWB_CTRL19 0x7B /* AWB control 19 */
  154. #define AWB_CTRL20 0x7C /* AWB control 20 */
  155. #define AWB_CTRL21 0x7D /* AWB control 21 */
  156. #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
  157. #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
  158. #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
  159. #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
  160. #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
  161. #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
  162. #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
  163. #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
  164. #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
  165. #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
  166. #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
  167. #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
  168. #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
  169. #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
  170. #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
  171. #define SLOP 0x8D /* Gamma curve highest segment slope */
  172. #define DNSTH 0x8E /* De-noise threshold */
  173. #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
  174. #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
  175. #define DNSOFF 0x91 /* Auto De-noise threshold control */
  176. #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
  177. #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
  178. #define MTX1 0x94 /* Matrix coefficient 1 */
  179. #define MTX2 0x95 /* Matrix coefficient 2 */
  180. #define MTX3 0x96 /* Matrix coefficient 3 */
  181. #define MTX4 0x97 /* Matrix coefficient 4 */
  182. #define MTX5 0x98 /* Matrix coefficient 5 */
  183. #define MTX6 0x99 /* Matrix coefficient 6 */
  184. #define MTX_CTRL 0x9A /* Matrix control */
  185. #define BRIGHT 0x9B /* Brightness control */
  186. #define CNTRST 0x9C /* Contrast contrast */
  187. #define CNTRST_CTRL 0x9D /* Contrast contrast center */
  188. #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
  189. #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
  190. #define SCAL0 0xA0 /* Scaling control 0 */
  191. #define SCAL1 0xA1 /* Scaling control 1 */
  192. #define SCAL2 0xA2 /* Scaling control 2 */
  193. #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
  194. #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
  195. #define SDE 0xA6 /* Special digital effect control */
  196. #define USAT 0xA7 /* U component saturation control */
  197. #define VSAT 0xA8 /* V component saturation control */
  198. /* for ov7720 */
  199. #define HUE0 0xA9 /* Hue control 0 */
  200. #define HUE1 0xAA /* Hue control 1 */
  201. /* for ov7725 */
  202. #define HUECOS 0xA9 /* Cosine value */
  203. #define HUESIN 0xAA /* Sine value */
  204. #define SIGN 0xAB /* Sign bit for Hue and contrast */
  205. #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
  206. /*
  207. * register detail
  208. */
  209. /* COM2 */
  210. #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
  211. /* Output drive capability */
  212. #define OCAP_1x 0x00 /* 1x */
  213. #define OCAP_2x 0x01 /* 2x */
  214. #define OCAP_3x 0x02 /* 3x */
  215. #define OCAP_4x 0x03 /* 4x */
  216. /* COM3 */
  217. #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
  218. #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
  219. #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
  220. #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
  221. #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
  222. #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
  223. #define SWAP_ML 0x08 /* Swap output MSB/LSB */
  224. /* Tri-state option for output clock */
  225. #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
  226. /* 1: No tri-state at this period */
  227. /* Tri-state option for output data */
  228. #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
  229. /* 1: No tri-state at this period */
  230. #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
  231. /* COM4 */
  232. /* PLL frequency control */
  233. #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
  234. #define PLL_4x 0x40 /* 01: PLL 4x */
  235. #define PLL_6x 0x80 /* 10: PLL 6x */
  236. #define PLL_8x 0xc0 /* 11: PLL 8x */
  237. /* AEC evaluate window */
  238. #define AEC_FULL 0x00 /* 00: Full window */
  239. #define AEC_1p2 0x10 /* 01: 1/2 window */
  240. #define AEC_1p4 0x20 /* 10: 1/4 window */
  241. #define AEC_2p3 0x30 /* 11: Low 2/3 window */
  242. #define COM4_RESERVED 0x01 /* Reserved bit */
  243. /* COM5 */
  244. #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
  245. #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
  246. /* Auto frame rate max rate control */
  247. #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
  248. #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
  249. #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
  250. #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
  251. /* Auto frame rate active point control */
  252. #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
  253. #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
  254. #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
  255. #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
  256. /* AEC max step control */
  257. #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
  258. /* 1 : No limit to AEC increase step */
  259. /* CLKRC */
  260. /* Input clock divider register */
  261. #define CLKRC_RESERVED 0x80 /* Reserved bit */
  262. #define CLKRC_DIV(n) ((n) - 1)
  263. /* COM7 */
  264. /* SCCB Register Reset */
  265. #define SCCB_RESET 0x80 /* 0 : No change */
  266. /* 1 : Resets all registers to default */
  267. /* Resolution selection */
  268. #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
  269. #define SLCT_VGA 0x00 /* 0 : VGA */
  270. #define SLCT_QVGA 0x40 /* 1 : QVGA */
  271. #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
  272. #define SENSOR_RAW 0x10 /* Sensor RAW */
  273. /* RGB output format control */
  274. #define FMT_MASK 0x0c /* Mask of color format */
  275. #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
  276. #define FMT_RGB565 0x04 /* 01 : RGB 565 */
  277. #define FMT_RGB555 0x08 /* 10 : RGB 555 */
  278. #define FMT_RGB444 0x0c /* 11 : RGB 444 */
  279. /* Output format control */
  280. #define OFMT_MASK 0x03 /* Mask of output format */
  281. #define OFMT_YUV 0x00 /* 00 : YUV */
  282. #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
  283. #define OFMT_RGB 0x02 /* 10 : RGB */
  284. #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
  285. /* COM8 */
  286. #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
  287. /* AEC Setp size limit */
  288. #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
  289. /* 1 : Unlimited step size */
  290. #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
  291. #define AEC_BND 0x10 /* Enable AEC below banding value */
  292. #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
  293. #define AGC_ON 0x04 /* AGC Enable */
  294. #define AWB_ON 0x02 /* AWB Enable */
  295. #define AEC_ON 0x01 /* AEC Enable */
  296. /* COM9 */
  297. #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
  298. /* Automatic gain ceiling - maximum AGC value */
  299. #define GAIN_2x 0x00 /* 000 : 2x */
  300. #define GAIN_4x 0x10 /* 001 : 4x */
  301. #define GAIN_8x 0x20 /* 010 : 8x */
  302. #define GAIN_16x 0x30 /* 011 : 16x */
  303. #define GAIN_32x 0x40 /* 100 : 32x */
  304. #define GAIN_64x 0x50 /* 101 : 64x */
  305. #define GAIN_128x 0x60 /* 110 : 128x */
  306. #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
  307. #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
  308. /* COM11 */
  309. #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
  310. #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
  311. /* HREF */
  312. #define HREF_VSTART_SHIFT 6 /* VSTART LSB */
  313. #define HREF_HSTART_SHIFT 4 /* HSTART 2 LSBs */
  314. #define HREF_VSIZE_SHIFT 2 /* VSIZE LSB */
  315. #define HREF_HSIZE_SHIFT 0 /* HSIZE 2 LSBs */
  316. /* EXHCH */
  317. #define EXHCH_VSIZE_SHIFT 2 /* VOUTSIZE LSB */
  318. #define EXHCH_HSIZE_SHIFT 0 /* HOUTSIZE 2 LSBs */
  319. /* DSP_CTRL1 */
  320. #define FIFO_ON 0x80 /* FIFO enable/disable selection */
  321. #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
  322. #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
  323. #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
  324. #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
  325. #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
  326. #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
  327. #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
  328. /* DSP_CTRL3 */
  329. #define UV_MASK 0x80 /* UV output sequence option */
  330. #define UV_ON 0x80 /* ON */
  331. #define UV_OFF 0x00 /* OFF */
  332. #define CBAR_MASK 0x20 /* DSP Color bar mask */
  333. #define CBAR_ON 0x20 /* ON */
  334. #define CBAR_OFF 0x00 /* OFF */
  335. /* DSP_CTRL4 */
  336. #define DSP_OFMT_YUV 0x00
  337. #define DSP_OFMT_RGB 0x00
  338. #define DSP_OFMT_RAW8 0x02
  339. #define DSP_OFMT_RAW10 0x03
  340. /* DSPAUTO (DSP Auto Function ON/OFF Control) */
  341. #define AWB_ACTRL 0x80 /* AWB auto threshold control */
  342. #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
  343. #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
  344. #define UV_ACTRL 0x10 /* UV adjust auto slope control */
  345. #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
  346. #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
  347. #define OV772X_MAX_WIDTH VGA_WIDTH
  348. #define OV772X_MAX_HEIGHT VGA_HEIGHT
  349. /*
  350. * ID
  351. */
  352. #define OV7720 0x7720
  353. #define OV7725 0x7721
  354. #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
  355. /*
  356. * PLL multipliers
  357. */
  358. static struct {
  359. unsigned int mult;
  360. u8 com4;
  361. } ov772x_pll[] = {
  362. { 1, PLL_BYPASS, },
  363. { 4, PLL_4x, },
  364. { 6, PLL_6x, },
  365. { 8, PLL_8x, },
  366. };
  367. /*
  368. * struct
  369. */
  370. struct ov772x_color_format {
  371. u32 code;
  372. enum v4l2_colorspace colorspace;
  373. u8 dsp3;
  374. u8 dsp4;
  375. u8 com3;
  376. u8 com7;
  377. };
  378. struct ov772x_win_size {
  379. char *name;
  380. unsigned char com7_bit;
  381. unsigned int sizeimage;
  382. struct v4l2_rect rect;
  383. };
  384. struct ov772x_priv {
  385. struct v4l2_subdev subdev;
  386. struct v4l2_ctrl_handler hdl;
  387. struct clk *clk;
  388. struct ov772x_camera_info *info;
  389. struct gpio_desc *pwdn_gpio;
  390. struct gpio_desc *rstb_gpio;
  391. const struct ov772x_color_format *cfmt;
  392. const struct ov772x_win_size *win;
  393. struct v4l2_ctrl *vflip_ctrl;
  394. struct v4l2_ctrl *hflip_ctrl;
  395. /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
  396. struct v4l2_ctrl *band_filter_ctrl;
  397. unsigned int fps;
  398. /* lock to protect power_count and streaming */
  399. struct mutex lock;
  400. int power_count;
  401. int streaming;
  402. #ifdef CONFIG_MEDIA_CONTROLLER
  403. struct media_pad pad;
  404. #endif
  405. };
  406. /*
  407. * supported color format list
  408. */
  409. static const struct ov772x_color_format ov772x_cfmts[] = {
  410. {
  411. .code = MEDIA_BUS_FMT_YUYV8_2X8,
  412. .colorspace = V4L2_COLORSPACE_SRGB,
  413. .dsp3 = 0x0,
  414. .dsp4 = DSP_OFMT_YUV,
  415. .com3 = SWAP_YUV,
  416. .com7 = OFMT_YUV,
  417. },
  418. {
  419. .code = MEDIA_BUS_FMT_YVYU8_2X8,
  420. .colorspace = V4L2_COLORSPACE_SRGB,
  421. .dsp3 = UV_ON,
  422. .dsp4 = DSP_OFMT_YUV,
  423. .com3 = SWAP_YUV,
  424. .com7 = OFMT_YUV,
  425. },
  426. {
  427. .code = MEDIA_BUS_FMT_UYVY8_2X8,
  428. .colorspace = V4L2_COLORSPACE_SRGB,
  429. .dsp3 = 0x0,
  430. .dsp4 = DSP_OFMT_YUV,
  431. .com3 = 0x0,
  432. .com7 = OFMT_YUV,
  433. },
  434. {
  435. .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
  436. .colorspace = V4L2_COLORSPACE_SRGB,
  437. .dsp3 = 0x0,
  438. .dsp4 = DSP_OFMT_YUV,
  439. .com3 = SWAP_RGB,
  440. .com7 = FMT_RGB555 | OFMT_RGB,
  441. },
  442. {
  443. .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
  444. .colorspace = V4L2_COLORSPACE_SRGB,
  445. .dsp3 = 0x0,
  446. .dsp4 = DSP_OFMT_YUV,
  447. .com3 = 0x0,
  448. .com7 = FMT_RGB555 | OFMT_RGB,
  449. },
  450. {
  451. .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
  452. .colorspace = V4L2_COLORSPACE_SRGB,
  453. .dsp3 = 0x0,
  454. .dsp4 = DSP_OFMT_YUV,
  455. .com3 = SWAP_RGB,
  456. .com7 = FMT_RGB565 | OFMT_RGB,
  457. },
  458. {
  459. .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
  460. .colorspace = V4L2_COLORSPACE_SRGB,
  461. .dsp3 = 0x0,
  462. .dsp4 = DSP_OFMT_YUV,
  463. .com3 = 0x0,
  464. .com7 = FMT_RGB565 | OFMT_RGB,
  465. },
  466. {
  467. /* Setting DSP4 to DSP_OFMT_RAW8 still gives 10-bit output,
  468. * regardless of the COM7 value. We can thus only support 10-bit
  469. * Bayer until someone figures it out.
  470. */
  471. .code = MEDIA_BUS_FMT_SBGGR10_1X10,
  472. .colorspace = V4L2_COLORSPACE_SRGB,
  473. .dsp3 = 0x0,
  474. .dsp4 = DSP_OFMT_RAW10,
  475. .com3 = 0x0,
  476. .com7 = SENSOR_RAW | OFMT_BRAW,
  477. },
  478. };
  479. /*
  480. * window size list
  481. */
  482. static const struct ov772x_win_size ov772x_win_sizes[] = {
  483. {
  484. .name = "VGA",
  485. .com7_bit = SLCT_VGA,
  486. .sizeimage = 510 * 748,
  487. .rect = {
  488. .left = 140,
  489. .top = 14,
  490. .width = VGA_WIDTH,
  491. .height = VGA_HEIGHT,
  492. },
  493. }, {
  494. .name = "QVGA",
  495. .com7_bit = SLCT_QVGA,
  496. .sizeimage = 278 * 576,
  497. .rect = {
  498. .left = 252,
  499. .top = 6,
  500. .width = QVGA_WIDTH,
  501. .height = QVGA_HEIGHT,
  502. },
  503. },
  504. };
  505. /*
  506. * frame rate settings lists
  507. */
  508. static const unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 };
  509. /*
  510. * general function
  511. */
  512. static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd)
  513. {
  514. return container_of(sd, struct ov772x_priv, subdev);
  515. }
  516. static int ov772x_read(struct i2c_client *client, u8 addr)
  517. {
  518. int ret;
  519. u8 val;
  520. ret = i2c_master_send(client, &addr, 1);
  521. if (ret < 0)
  522. return ret;
  523. ret = i2c_master_recv(client, &val, 1);
  524. if (ret < 0)
  525. return ret;
  526. return val;
  527. }
  528. static inline int ov772x_write(struct i2c_client *client, u8 addr, u8 value)
  529. {
  530. return i2c_smbus_write_byte_data(client, addr, value);
  531. }
  532. static int ov772x_mask_set(struct i2c_client *client, u8 command, u8 mask,
  533. u8 set)
  534. {
  535. s32 val = ov772x_read(client, command);
  536. if (val < 0)
  537. return val;
  538. val &= ~mask;
  539. val |= set & mask;
  540. return ov772x_write(client, command, val);
  541. }
  542. static int ov772x_reset(struct i2c_client *client)
  543. {
  544. int ret;
  545. ret = ov772x_write(client, COM7, SCCB_RESET);
  546. if (ret < 0)
  547. return ret;
  548. usleep_range(1000, 5000);
  549. return ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
  550. }
  551. /*
  552. * subdev ops
  553. */
  554. static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
  555. {
  556. struct i2c_client *client = v4l2_get_subdevdata(sd);
  557. struct ov772x_priv *priv = to_ov772x(sd);
  558. int ret = 0;
  559. mutex_lock(&priv->lock);
  560. if (priv->streaming == enable)
  561. goto done;
  562. ret = ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE,
  563. enable ? 0 : SOFT_SLEEP_MODE);
  564. if (ret)
  565. goto done;
  566. if (enable) {
  567. dev_dbg(&client->dev, "format %d, win %s\n",
  568. priv->cfmt->code, priv->win->name);
  569. }
  570. priv->streaming = enable;
  571. done:
  572. mutex_unlock(&priv->lock);
  573. return ret;
  574. }
  575. static unsigned int ov772x_select_fps(struct ov772x_priv *priv,
  576. struct v4l2_fract *tpf)
  577. {
  578. unsigned int fps = tpf->numerator ?
  579. tpf->denominator / tpf->numerator :
  580. tpf->denominator;
  581. unsigned int best_diff;
  582. unsigned int diff;
  583. unsigned int idx;
  584. unsigned int i;
  585. /* Approximate to the closest supported frame interval. */
  586. best_diff = ~0L;
  587. for (i = 0, idx = 0; i < ARRAY_SIZE(ov772x_frame_intervals); i++) {
  588. diff = abs(fps - ov772x_frame_intervals[i]);
  589. if (diff < best_diff) {
  590. idx = i;
  591. best_diff = diff;
  592. }
  593. }
  594. return ov772x_frame_intervals[idx];
  595. }
  596. static int ov772x_set_frame_rate(struct ov772x_priv *priv,
  597. unsigned int fps,
  598. const struct ov772x_color_format *cfmt,
  599. const struct ov772x_win_size *win)
  600. {
  601. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  602. unsigned long fin = clk_get_rate(priv->clk);
  603. unsigned int best_diff;
  604. unsigned int fsize;
  605. unsigned int pclk;
  606. unsigned int diff;
  607. unsigned int i;
  608. u8 clkrc = 0;
  609. u8 com4 = 0;
  610. int ret;
  611. /* Use image size (with blankings) to calculate desired pixel clock. */
  612. switch (cfmt->com7 & OFMT_MASK) {
  613. case OFMT_BRAW:
  614. fsize = win->sizeimage;
  615. break;
  616. case OFMT_RGB:
  617. case OFMT_YUV:
  618. default:
  619. fsize = win->sizeimage * 2;
  620. break;
  621. }
  622. pclk = fps * fsize;
  623. /*
  624. * Pixel clock generation circuit is pretty simple:
  625. *
  626. * Fin -> [ / CLKRC_div] -> [ * PLL_mult] -> pclk
  627. *
  628. * Try to approximate the desired pixel clock testing all available
  629. * PLL multipliers (1x, 4x, 6x, 8x) and calculate corresponding
  630. * divisor with:
  631. *
  632. * div = PLL_mult * Fin / pclk
  633. *
  634. * and re-calculate the pixel clock using it:
  635. *
  636. * pclk = Fin * PLL_mult / CLKRC_div
  637. *
  638. * Choose the PLL_mult and CLKRC_div pair that gives a pixel clock
  639. * closer to the desired one.
  640. *
  641. * The desired pixel clock is calculated using a known frame size
  642. * (blanking included) and FPS.
  643. */
  644. best_diff = ~0L;
  645. for (i = 0; i < ARRAY_SIZE(ov772x_pll); i++) {
  646. unsigned int pll_mult = ov772x_pll[i].mult;
  647. unsigned int pll_out = pll_mult * fin;
  648. unsigned int t_pclk;
  649. unsigned int div;
  650. if (pll_out < pclk)
  651. continue;
  652. div = DIV_ROUND_CLOSEST(pll_out, pclk);
  653. t_pclk = DIV_ROUND_CLOSEST(fin * pll_mult, div);
  654. diff = abs(pclk - t_pclk);
  655. if (diff < best_diff) {
  656. best_diff = diff;
  657. clkrc = CLKRC_DIV(div);
  658. com4 = ov772x_pll[i].com4;
  659. }
  660. }
  661. ret = ov772x_write(client, COM4, com4 | COM4_RESERVED);
  662. if (ret < 0)
  663. return ret;
  664. ret = ov772x_write(client, CLKRC, clkrc | CLKRC_RESERVED);
  665. if (ret < 0)
  666. return ret;
  667. return 0;
  668. }
  669. static int ov772x_g_frame_interval(struct v4l2_subdev *sd,
  670. struct v4l2_subdev_frame_interval *ival)
  671. {
  672. struct ov772x_priv *priv = to_ov772x(sd);
  673. struct v4l2_fract *tpf = &ival->interval;
  674. tpf->numerator = 1;
  675. tpf->denominator = priv->fps;
  676. return 0;
  677. }
  678. static int ov772x_s_frame_interval(struct v4l2_subdev *sd,
  679. struct v4l2_subdev_frame_interval *ival)
  680. {
  681. struct ov772x_priv *priv = to_ov772x(sd);
  682. struct v4l2_fract *tpf = &ival->interval;
  683. unsigned int fps;
  684. int ret = 0;
  685. mutex_lock(&priv->lock);
  686. if (priv->streaming) {
  687. ret = -EBUSY;
  688. goto error;
  689. }
  690. fps = ov772x_select_fps(priv, tpf);
  691. /*
  692. * If the device is not powered up by the host driver do
  693. * not apply any changes to H/W at this time. Instead
  694. * the frame rate will be restored right after power-up.
  695. */
  696. if (priv->power_count > 0) {
  697. ret = ov772x_set_frame_rate(priv, fps, priv->cfmt, priv->win);
  698. if (ret)
  699. goto error;
  700. }
  701. tpf->numerator = 1;
  702. tpf->denominator = fps;
  703. priv->fps = fps;
  704. error:
  705. mutex_unlock(&priv->lock);
  706. return ret;
  707. }
  708. static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
  709. {
  710. struct ov772x_priv *priv = container_of(ctrl->handler,
  711. struct ov772x_priv, hdl);
  712. struct v4l2_subdev *sd = &priv->subdev;
  713. struct i2c_client *client = v4l2_get_subdevdata(sd);
  714. int ret = 0;
  715. u8 val;
  716. /* v4l2_ctrl_lock() locks our own mutex */
  717. /*
  718. * If the device is not powered up by the host driver do
  719. * not apply any controls to H/W at this time. Instead
  720. * the controls will be restored right after power-up.
  721. */
  722. if (priv->power_count == 0)
  723. return 0;
  724. switch (ctrl->id) {
  725. case V4L2_CID_VFLIP:
  726. val = ctrl->val ? VFLIP_IMG : 0x00;
  727. if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
  728. val ^= VFLIP_IMG;
  729. return ov772x_mask_set(client, COM3, VFLIP_IMG, val);
  730. case V4L2_CID_HFLIP:
  731. val = ctrl->val ? HFLIP_IMG : 0x00;
  732. if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
  733. val ^= HFLIP_IMG;
  734. return ov772x_mask_set(client, COM3, HFLIP_IMG, val);
  735. case V4L2_CID_BAND_STOP_FILTER:
  736. if (!ctrl->val) {
  737. /* Switch the filter off, it is on now */
  738. ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
  739. if (!ret)
  740. ret = ov772x_mask_set(client, COM8,
  741. BNDF_ON_OFF, 0);
  742. } else {
  743. /* Switch the filter on, set AEC low limit */
  744. val = 256 - ctrl->val;
  745. ret = ov772x_mask_set(client, COM8,
  746. BNDF_ON_OFF, BNDF_ON_OFF);
  747. if (!ret)
  748. ret = ov772x_mask_set(client, BDBASE,
  749. 0xff, val);
  750. }
  751. return ret;
  752. }
  753. return -EINVAL;
  754. }
  755. #ifdef CONFIG_VIDEO_ADV_DEBUG
  756. static int ov772x_g_register(struct v4l2_subdev *sd,
  757. struct v4l2_dbg_register *reg)
  758. {
  759. struct i2c_client *client = v4l2_get_subdevdata(sd);
  760. int ret;
  761. reg->size = 1;
  762. if (reg->reg > 0xff)
  763. return -EINVAL;
  764. ret = ov772x_read(client, reg->reg);
  765. if (ret < 0)
  766. return ret;
  767. reg->val = (__u64)ret;
  768. return 0;
  769. }
  770. static int ov772x_s_register(struct v4l2_subdev *sd,
  771. const struct v4l2_dbg_register *reg)
  772. {
  773. struct i2c_client *client = v4l2_get_subdevdata(sd);
  774. if (reg->reg > 0xff ||
  775. reg->val > 0xff)
  776. return -EINVAL;
  777. return ov772x_write(client, reg->reg, reg->val);
  778. }
  779. #endif
  780. static int ov772x_power_on(struct ov772x_priv *priv)
  781. {
  782. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  783. int ret;
  784. if (priv->clk) {
  785. ret = clk_prepare_enable(priv->clk);
  786. if (ret)
  787. return ret;
  788. }
  789. if (priv->pwdn_gpio) {
  790. gpiod_set_value(priv->pwdn_gpio, 1);
  791. usleep_range(500, 1000);
  792. }
  793. /*
  794. * FIXME: The reset signal is connected to a shared GPIO on some
  795. * platforms (namely the SuperH Migo-R). Until a framework becomes
  796. * available to handle this cleanly, request the GPIO temporarily
  797. * to avoid conflicts.
  798. */
  799. priv->rstb_gpio = gpiod_get_optional(&client->dev, "reset",
  800. GPIOD_OUT_LOW);
  801. if (IS_ERR(priv->rstb_gpio)) {
  802. dev_info(&client->dev, "Unable to get GPIO \"reset\"");
  803. clk_disable_unprepare(priv->clk);
  804. return PTR_ERR(priv->rstb_gpio);
  805. }
  806. if (priv->rstb_gpio) {
  807. gpiod_set_value(priv->rstb_gpio, 1);
  808. usleep_range(500, 1000);
  809. gpiod_set_value(priv->rstb_gpio, 0);
  810. usleep_range(500, 1000);
  811. gpiod_put(priv->rstb_gpio);
  812. }
  813. return 0;
  814. }
  815. static int ov772x_power_off(struct ov772x_priv *priv)
  816. {
  817. clk_disable_unprepare(priv->clk);
  818. if (priv->pwdn_gpio) {
  819. gpiod_set_value(priv->pwdn_gpio, 0);
  820. usleep_range(500, 1000);
  821. }
  822. return 0;
  823. }
  824. static int ov772x_set_params(struct ov772x_priv *priv,
  825. const struct ov772x_color_format *cfmt,
  826. const struct ov772x_win_size *win);
  827. static int ov772x_s_power(struct v4l2_subdev *sd, int on)
  828. {
  829. struct ov772x_priv *priv = to_ov772x(sd);
  830. int ret = 0;
  831. mutex_lock(&priv->lock);
  832. /* If the power count is modified from 0 to != 0 or from != 0 to 0,
  833. * update the power state.
  834. */
  835. if (priv->power_count == !on) {
  836. if (on) {
  837. ret = ov772x_power_on(priv);
  838. /*
  839. * Restore the format, the frame rate, and
  840. * the controls
  841. */
  842. if (!ret)
  843. ret = ov772x_set_params(priv, priv->cfmt,
  844. priv->win);
  845. } else {
  846. ret = ov772x_power_off(priv);
  847. }
  848. }
  849. if (!ret) {
  850. /* Update the power count. */
  851. priv->power_count += on ? 1 : -1;
  852. WARN(priv->power_count < 0, "Unbalanced power count\n");
  853. WARN(priv->power_count > 1, "Duplicated s_power call\n");
  854. }
  855. mutex_unlock(&priv->lock);
  856. return ret;
  857. }
  858. static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
  859. {
  860. const struct ov772x_win_size *win = &ov772x_win_sizes[0];
  861. u32 best_diff = UINT_MAX;
  862. unsigned int i;
  863. for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) {
  864. u32 diff = abs(width - ov772x_win_sizes[i].rect.width)
  865. + abs(height - ov772x_win_sizes[i].rect.height);
  866. if (diff < best_diff) {
  867. best_diff = diff;
  868. win = &ov772x_win_sizes[i];
  869. }
  870. }
  871. return win;
  872. }
  873. static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf,
  874. const struct ov772x_color_format **cfmt,
  875. const struct ov772x_win_size **win)
  876. {
  877. unsigned int i;
  878. /* Select a format. */
  879. *cfmt = &ov772x_cfmts[0];
  880. for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
  881. if (mf->code == ov772x_cfmts[i].code) {
  882. *cfmt = &ov772x_cfmts[i];
  883. break;
  884. }
  885. }
  886. /* Select a window size. */
  887. *win = ov772x_select_win(mf->width, mf->height);
  888. }
  889. static int ov772x_edgectrl(struct ov772x_priv *priv)
  890. {
  891. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  892. int ret;
  893. if (!priv->info)
  894. return 0;
  895. if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
  896. /*
  897. * Manual Edge Control Mode.
  898. *
  899. * Edge auto strength bit is set by default.
  900. * Remove it when manual mode.
  901. */
  902. ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
  903. if (ret < 0)
  904. return ret;
  905. ret = ov772x_mask_set(client,
  906. EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK,
  907. priv->info->edgectrl.threshold);
  908. if (ret < 0)
  909. return ret;
  910. ret = ov772x_mask_set(client,
  911. EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK,
  912. priv->info->edgectrl.strength);
  913. if (ret < 0)
  914. return ret;
  915. } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
  916. /*
  917. * Auto Edge Control Mode.
  918. *
  919. * Set upper and lower limit.
  920. */
  921. ret = ov772x_mask_set(client,
  922. EDGE_UPPER, OV772X_EDGE_UPPER_MASK,
  923. priv->info->edgectrl.upper);
  924. if (ret < 0)
  925. return ret;
  926. ret = ov772x_mask_set(client,
  927. EDGE_LOWER, OV772X_EDGE_LOWER_MASK,
  928. priv->info->edgectrl.lower);
  929. if (ret < 0)
  930. return ret;
  931. }
  932. return 0;
  933. }
  934. static int ov772x_set_params(struct ov772x_priv *priv,
  935. const struct ov772x_color_format *cfmt,
  936. const struct ov772x_win_size *win)
  937. {
  938. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  939. int ret;
  940. u8 val;
  941. /* Reset hardware. */
  942. ov772x_reset(client);
  943. /* Edge Ctrl. */
  944. ret = ov772x_edgectrl(priv);
  945. if (ret < 0)
  946. return ret;
  947. /* Format and window size. */
  948. ret = ov772x_write(client, HSTART, win->rect.left >> 2);
  949. if (ret < 0)
  950. goto ov772x_set_fmt_error;
  951. ret = ov772x_write(client, HSIZE, win->rect.width >> 2);
  952. if (ret < 0)
  953. goto ov772x_set_fmt_error;
  954. ret = ov772x_write(client, VSTART, win->rect.top >> 1);
  955. if (ret < 0)
  956. goto ov772x_set_fmt_error;
  957. ret = ov772x_write(client, VSIZE, win->rect.height >> 1);
  958. if (ret < 0)
  959. goto ov772x_set_fmt_error;
  960. ret = ov772x_write(client, HOUTSIZE, win->rect.width >> 2);
  961. if (ret < 0)
  962. goto ov772x_set_fmt_error;
  963. ret = ov772x_write(client, VOUTSIZE, win->rect.height >> 1);
  964. if (ret < 0)
  965. goto ov772x_set_fmt_error;
  966. ret = ov772x_write(client, HREF,
  967. ((win->rect.top & 1) << HREF_VSTART_SHIFT) |
  968. ((win->rect.left & 3) << HREF_HSTART_SHIFT) |
  969. ((win->rect.height & 1) << HREF_VSIZE_SHIFT) |
  970. ((win->rect.width & 3) << HREF_HSIZE_SHIFT));
  971. if (ret < 0)
  972. goto ov772x_set_fmt_error;
  973. ret = ov772x_write(client, EXHCH,
  974. ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) |
  975. ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT));
  976. if (ret < 0)
  977. goto ov772x_set_fmt_error;
  978. /* Set DSP_CTRL3. */
  979. val = cfmt->dsp3;
  980. if (val) {
  981. ret = ov772x_mask_set(client,
  982. DSP_CTRL3, UV_MASK, val);
  983. if (ret < 0)
  984. goto ov772x_set_fmt_error;
  985. }
  986. /* DSP_CTRL4: AEC reference point and DSP output format. */
  987. if (cfmt->dsp4) {
  988. ret = ov772x_write(client, DSP_CTRL4, cfmt->dsp4);
  989. if (ret < 0)
  990. goto ov772x_set_fmt_error;
  991. }
  992. /* Set COM3. */
  993. val = cfmt->com3;
  994. if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
  995. val |= VFLIP_IMG;
  996. if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
  997. val |= HFLIP_IMG;
  998. if (priv->vflip_ctrl->val)
  999. val ^= VFLIP_IMG;
  1000. if (priv->hflip_ctrl->val)
  1001. val ^= HFLIP_IMG;
  1002. ret = ov772x_mask_set(client,
  1003. COM3, SWAP_MASK | IMG_MASK, val);
  1004. if (ret < 0)
  1005. goto ov772x_set_fmt_error;
  1006. /* COM7: Sensor resolution and output format control. */
  1007. ret = ov772x_write(client, COM7, win->com7_bit | cfmt->com7);
  1008. if (ret < 0)
  1009. goto ov772x_set_fmt_error;
  1010. /* COM4, CLKRC: Set pixel clock and framerate. */
  1011. ret = ov772x_set_frame_rate(priv, priv->fps, cfmt, win);
  1012. if (ret < 0)
  1013. goto ov772x_set_fmt_error;
  1014. /* Set COM8. */
  1015. if (priv->band_filter_ctrl->val) {
  1016. unsigned short band_filter = priv->band_filter_ctrl->val;
  1017. ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, BNDF_ON_OFF);
  1018. if (!ret)
  1019. ret = ov772x_mask_set(client, BDBASE,
  1020. 0xff, 256 - band_filter);
  1021. if (ret < 0)
  1022. goto ov772x_set_fmt_error;
  1023. }
  1024. return ret;
  1025. ov772x_set_fmt_error:
  1026. ov772x_reset(client);
  1027. return ret;
  1028. }
  1029. static int ov772x_get_selection(struct v4l2_subdev *sd,
  1030. struct v4l2_subdev_pad_config *cfg,
  1031. struct v4l2_subdev_selection *sel)
  1032. {
  1033. struct ov772x_priv *priv = to_ov772x(sd);
  1034. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  1035. return -EINVAL;
  1036. sel->r.left = 0;
  1037. sel->r.top = 0;
  1038. switch (sel->target) {
  1039. case V4L2_SEL_TGT_CROP_BOUNDS:
  1040. case V4L2_SEL_TGT_CROP_DEFAULT:
  1041. case V4L2_SEL_TGT_CROP:
  1042. sel->r.width = priv->win->rect.width;
  1043. sel->r.height = priv->win->rect.height;
  1044. return 0;
  1045. default:
  1046. return -EINVAL;
  1047. }
  1048. }
  1049. static int ov772x_get_fmt(struct v4l2_subdev *sd,
  1050. struct v4l2_subdev_pad_config *cfg,
  1051. struct v4l2_subdev_format *format)
  1052. {
  1053. struct v4l2_mbus_framefmt *mf = &format->format;
  1054. struct ov772x_priv *priv = to_ov772x(sd);
  1055. if (format->pad)
  1056. return -EINVAL;
  1057. mf->width = priv->win->rect.width;
  1058. mf->height = priv->win->rect.height;
  1059. mf->code = priv->cfmt->code;
  1060. mf->colorspace = priv->cfmt->colorspace;
  1061. mf->field = V4L2_FIELD_NONE;
  1062. return 0;
  1063. }
  1064. static int ov772x_set_fmt(struct v4l2_subdev *sd,
  1065. struct v4l2_subdev_pad_config *cfg,
  1066. struct v4l2_subdev_format *format)
  1067. {
  1068. struct ov772x_priv *priv = to_ov772x(sd);
  1069. struct v4l2_mbus_framefmt *mf = &format->format;
  1070. const struct ov772x_color_format *cfmt;
  1071. const struct ov772x_win_size *win;
  1072. int ret = 0;
  1073. if (format->pad)
  1074. return -EINVAL;
  1075. ov772x_select_params(mf, &cfmt, &win);
  1076. mf->code = cfmt->code;
  1077. mf->width = win->rect.width;
  1078. mf->height = win->rect.height;
  1079. mf->field = V4L2_FIELD_NONE;
  1080. mf->colorspace = cfmt->colorspace;
  1081. mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
  1082. mf->quantization = V4L2_QUANTIZATION_DEFAULT;
  1083. mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
  1084. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1085. cfg->try_fmt = *mf;
  1086. return 0;
  1087. }
  1088. mutex_lock(&priv->lock);
  1089. if (priv->streaming) {
  1090. ret = -EBUSY;
  1091. goto error;
  1092. }
  1093. /*
  1094. * If the device is not powered up by the host driver do
  1095. * not apply any changes to H/W at this time. Instead
  1096. * the format will be restored right after power-up.
  1097. */
  1098. if (priv->power_count > 0) {
  1099. ret = ov772x_set_params(priv, cfmt, win);
  1100. if (ret < 0)
  1101. goto error;
  1102. }
  1103. priv->win = win;
  1104. priv->cfmt = cfmt;
  1105. error:
  1106. mutex_unlock(&priv->lock);
  1107. return ret;
  1108. }
  1109. static int ov772x_video_probe(struct ov772x_priv *priv)
  1110. {
  1111. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  1112. int pid, ver, midh, midl;
  1113. const char *devname;
  1114. int ret;
  1115. ret = ov772x_power_on(priv);
  1116. if (ret < 0)
  1117. return ret;
  1118. /* Check and show product ID and manufacturer ID. */
  1119. pid = ov772x_read(client, PID);
  1120. if (pid < 0)
  1121. return pid;
  1122. ver = ov772x_read(client, VER);
  1123. if (ver < 0)
  1124. return ver;
  1125. switch (VERSION(pid, ver)) {
  1126. case OV7720:
  1127. devname = "ov7720";
  1128. break;
  1129. case OV7725:
  1130. devname = "ov7725";
  1131. break;
  1132. default:
  1133. dev_err(&client->dev,
  1134. "Product ID error %x:%x\n", pid, ver);
  1135. ret = -ENODEV;
  1136. goto done;
  1137. }
  1138. midh = ov772x_read(client, MIDH);
  1139. if (midh < 0)
  1140. return midh;
  1141. midl = ov772x_read(client, MIDL);
  1142. if (midl < 0)
  1143. return midl;
  1144. dev_info(&client->dev,
  1145. "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
  1146. devname, pid, ver, midh, midl);
  1147. ret = v4l2_ctrl_handler_setup(&priv->hdl);
  1148. done:
  1149. ov772x_power_off(priv);
  1150. return ret;
  1151. }
  1152. static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
  1153. .s_ctrl = ov772x_s_ctrl,
  1154. };
  1155. static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
  1156. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1157. .g_register = ov772x_g_register,
  1158. .s_register = ov772x_s_register,
  1159. #endif
  1160. .s_power = ov772x_s_power,
  1161. };
  1162. static int ov772x_enum_frame_interval(struct v4l2_subdev *sd,
  1163. struct v4l2_subdev_pad_config *cfg,
  1164. struct v4l2_subdev_frame_interval_enum *fie)
  1165. {
  1166. if (fie->pad || fie->index >= ARRAY_SIZE(ov772x_frame_intervals))
  1167. return -EINVAL;
  1168. if (fie->width != VGA_WIDTH && fie->width != QVGA_WIDTH)
  1169. return -EINVAL;
  1170. if (fie->height != VGA_HEIGHT && fie->height != QVGA_HEIGHT)
  1171. return -EINVAL;
  1172. fie->interval.numerator = 1;
  1173. fie->interval.denominator = ov772x_frame_intervals[fie->index];
  1174. return 0;
  1175. }
  1176. static int ov772x_enum_mbus_code(struct v4l2_subdev *sd,
  1177. struct v4l2_subdev_pad_config *cfg,
  1178. struct v4l2_subdev_mbus_code_enum *code)
  1179. {
  1180. if (code->pad || code->index >= ARRAY_SIZE(ov772x_cfmts))
  1181. return -EINVAL;
  1182. code->code = ov772x_cfmts[code->index].code;
  1183. return 0;
  1184. }
  1185. static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
  1186. .s_stream = ov772x_s_stream,
  1187. .s_frame_interval = ov772x_s_frame_interval,
  1188. .g_frame_interval = ov772x_g_frame_interval,
  1189. };
  1190. static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = {
  1191. .enum_frame_interval = ov772x_enum_frame_interval,
  1192. .enum_mbus_code = ov772x_enum_mbus_code,
  1193. .get_selection = ov772x_get_selection,
  1194. .get_fmt = ov772x_get_fmt,
  1195. .set_fmt = ov772x_set_fmt,
  1196. };
  1197. static const struct v4l2_subdev_ops ov772x_subdev_ops = {
  1198. .core = &ov772x_subdev_core_ops,
  1199. .video = &ov772x_subdev_video_ops,
  1200. .pad = &ov772x_subdev_pad_ops,
  1201. };
  1202. /*
  1203. * i2c_driver function
  1204. */
  1205. static int ov772x_probe(struct i2c_client *client,
  1206. const struct i2c_device_id *did)
  1207. {
  1208. struct ov772x_priv *priv;
  1209. struct i2c_adapter *adapter = client->adapter;
  1210. int ret;
  1211. if (!client->dev.of_node && !client->dev.platform_data) {
  1212. dev_err(&client->dev,
  1213. "Missing ov772x platform data for non-DT device\n");
  1214. return -EINVAL;
  1215. }
  1216. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
  1217. dev_err(&adapter->dev,
  1218. "I2C-Adapter doesn't support SMBUS_BYTE_DATA\n");
  1219. return -EIO;
  1220. }
  1221. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  1222. if (!priv)
  1223. return -ENOMEM;
  1224. priv->info = client->dev.platform_data;
  1225. mutex_init(&priv->lock);
  1226. v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
  1227. priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1228. v4l2_ctrl_handler_init(&priv->hdl, 3);
  1229. /* Use our mutex for the controls */
  1230. priv->hdl.lock = &priv->lock;
  1231. priv->vflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
  1232. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1233. priv->hflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
  1234. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1235. priv->band_filter_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
  1236. V4L2_CID_BAND_STOP_FILTER,
  1237. 0, 256, 1, 0);
  1238. priv->subdev.ctrl_handler = &priv->hdl;
  1239. if (priv->hdl.error) {
  1240. ret = priv->hdl.error;
  1241. goto error_mutex_destroy;
  1242. }
  1243. priv->clk = clk_get(&client->dev, NULL);
  1244. if (IS_ERR(priv->clk)) {
  1245. dev_err(&client->dev, "Unable to get xclk clock\n");
  1246. ret = PTR_ERR(priv->clk);
  1247. goto error_ctrl_free;
  1248. }
  1249. priv->pwdn_gpio = gpiod_get_optional(&client->dev, "powerdown",
  1250. GPIOD_OUT_LOW);
  1251. if (IS_ERR(priv->pwdn_gpio)) {
  1252. dev_info(&client->dev, "Unable to get GPIO \"powerdown\"");
  1253. ret = PTR_ERR(priv->pwdn_gpio);
  1254. goto error_clk_put;
  1255. }
  1256. ret = ov772x_video_probe(priv);
  1257. if (ret < 0)
  1258. goto error_gpio_put;
  1259. #ifdef CONFIG_MEDIA_CONTROLLER
  1260. priv->pad.flags = MEDIA_PAD_FL_SOURCE;
  1261. priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1262. ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
  1263. if (ret < 0)
  1264. goto error_gpio_put;
  1265. #endif
  1266. priv->cfmt = &ov772x_cfmts[0];
  1267. priv->win = &ov772x_win_sizes[0];
  1268. priv->fps = 15;
  1269. ret = v4l2_async_register_subdev(&priv->subdev);
  1270. if (ret)
  1271. goto error_entity_cleanup;
  1272. return 0;
  1273. error_entity_cleanup:
  1274. media_entity_cleanup(&priv->subdev.entity);
  1275. error_gpio_put:
  1276. if (priv->pwdn_gpio)
  1277. gpiod_put(priv->pwdn_gpio);
  1278. error_clk_put:
  1279. clk_put(priv->clk);
  1280. error_ctrl_free:
  1281. v4l2_ctrl_handler_free(&priv->hdl);
  1282. error_mutex_destroy:
  1283. mutex_destroy(&priv->lock);
  1284. return ret;
  1285. }
  1286. static int ov772x_remove(struct i2c_client *client)
  1287. {
  1288. struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client));
  1289. media_entity_cleanup(&priv->subdev.entity);
  1290. clk_put(priv->clk);
  1291. if (priv->pwdn_gpio)
  1292. gpiod_put(priv->pwdn_gpio);
  1293. v4l2_async_unregister_subdev(&priv->subdev);
  1294. v4l2_ctrl_handler_free(&priv->hdl);
  1295. mutex_destroy(&priv->lock);
  1296. return 0;
  1297. }
  1298. static const struct i2c_device_id ov772x_id[] = {
  1299. { "ov772x", 0 },
  1300. { }
  1301. };
  1302. MODULE_DEVICE_TABLE(i2c, ov772x_id);
  1303. static const struct of_device_id ov772x_of_match[] = {
  1304. { .compatible = "ovti,ov7725", },
  1305. { .compatible = "ovti,ov7720", },
  1306. { /* sentinel */ },
  1307. };
  1308. MODULE_DEVICE_TABLE(of, ov772x_of_match);
  1309. static struct i2c_driver ov772x_i2c_driver = {
  1310. .driver = {
  1311. .name = "ov772x",
  1312. .of_match_table = ov772x_of_match,
  1313. },
  1314. .probe = ov772x_probe,
  1315. .remove = ov772x_remove,
  1316. .id_table = ov772x_id,
  1317. };
  1318. module_i2c_driver(ov772x_i2c_driver);
  1319. MODULE_DESCRIPTION("V4L2 driver for OV772x image sensor");
  1320. MODULE_AUTHOR("Kuninori Morimoto");
  1321. MODULE_LICENSE("GPL v2");