isif.c 29 KB

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  1. /*
  2. * Copyright (C) 2008-2009 Texas Instruments Inc
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * Image Sensor Interface (ISIF) driver
  15. *
  16. * This driver is for configuring the ISIF IP available on DM365 or any other
  17. * TI SoCs. This is used for capturing yuv or bayer video or image data
  18. * from a decoder or sensor. This IP is similar to the CCDC IP on DM355
  19. * and DM6446, but with enhanced or additional ip blocks. The driver
  20. * configures the ISIF upon commands from the vpfe bridge driver through
  21. * ccdc_hw_device interface.
  22. *
  23. * TODO: 1) Raw bayer parameter settings and bayer capture
  24. * 2) Add support for control ioctl
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/io.h>
  30. #include <linux/videodev2.h>
  31. #include <linux/err.h>
  32. #include <linux/module.h>
  33. #include <media/davinci/isif.h>
  34. #include <media/davinci/vpss.h>
  35. #include "isif_regs.h"
  36. #include "ccdc_hw_device.h"
  37. /* Defaults for module configuration parameters */
  38. static struct isif_config_params_raw isif_config_defaults = {
  39. .linearize = {
  40. .en = 0,
  41. .corr_shft = ISIF_NO_SHIFT,
  42. .scale_fact = {1, 0},
  43. },
  44. .df_csc = {
  45. .df_or_csc = 0,
  46. .csc = {
  47. .en = 0,
  48. },
  49. },
  50. .dfc = {
  51. .en = 0,
  52. },
  53. .bclamp = {
  54. .en = 0,
  55. },
  56. .gain_offset = {
  57. .gain = {
  58. .r_ye = {1, 0},
  59. .gr_cy = {1, 0},
  60. .gb_g = {1, 0},
  61. .b_mg = {1, 0},
  62. },
  63. },
  64. .culling = {
  65. .hcpat_odd = 0xff,
  66. .hcpat_even = 0xff,
  67. .vcpat = 0xff,
  68. },
  69. .compress = {
  70. .alg = ISIF_ALAW,
  71. },
  72. };
  73. /* ISIF operation configuration */
  74. static struct isif_oper_config {
  75. struct device *dev;
  76. enum vpfe_hw_if_type if_type;
  77. struct isif_ycbcr_config ycbcr;
  78. struct isif_params_raw bayer;
  79. enum isif_data_pack data_pack;
  80. /* ISIF base address */
  81. void __iomem *base_addr;
  82. /* ISIF Linear Table 0 */
  83. void __iomem *linear_tbl0_addr;
  84. /* ISIF Linear Table 1 */
  85. void __iomem *linear_tbl1_addr;
  86. } isif_cfg = {
  87. .ycbcr = {
  88. .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
  89. .frm_fmt = CCDC_FRMFMT_INTERLACED,
  90. .win = ISIF_WIN_NTSC,
  91. .fid_pol = VPFE_PINPOL_POSITIVE,
  92. .vd_pol = VPFE_PINPOL_POSITIVE,
  93. .hd_pol = VPFE_PINPOL_POSITIVE,
  94. .pix_order = CCDC_PIXORDER_CBYCRY,
  95. .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED,
  96. },
  97. .bayer = {
  98. .pix_fmt = CCDC_PIXFMT_RAW,
  99. .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
  100. .win = ISIF_WIN_VGA,
  101. .fid_pol = VPFE_PINPOL_POSITIVE,
  102. .vd_pol = VPFE_PINPOL_POSITIVE,
  103. .hd_pol = VPFE_PINPOL_POSITIVE,
  104. .gain = {
  105. .r_ye = {1, 0},
  106. .gr_cy = {1, 0},
  107. .gb_g = {1, 0},
  108. .b_mg = {1, 0},
  109. },
  110. .cfa_pat = ISIF_CFA_PAT_MOSAIC,
  111. .data_msb = ISIF_BIT_MSB_11,
  112. .config_params = {
  113. .data_shift = ISIF_NO_SHIFT,
  114. .col_pat_field0 = {
  115. .olop = ISIF_GREEN_BLUE,
  116. .olep = ISIF_BLUE,
  117. .elop = ISIF_RED,
  118. .elep = ISIF_GREEN_RED,
  119. },
  120. .col_pat_field1 = {
  121. .olop = ISIF_GREEN_BLUE,
  122. .olep = ISIF_BLUE,
  123. .elop = ISIF_RED,
  124. .elep = ISIF_GREEN_RED,
  125. },
  126. .test_pat_gen = 0,
  127. },
  128. },
  129. .data_pack = ISIF_DATA_PACK8,
  130. };
  131. /* Raw Bayer formats */
  132. static const u32 isif_raw_bayer_pix_formats[] = {
  133. V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
  134. /* Raw YUV formats */
  135. static const u32 isif_raw_yuv_pix_formats[] = {
  136. V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
  137. /* register access routines */
  138. static inline u32 regr(u32 offset)
  139. {
  140. return __raw_readl(isif_cfg.base_addr + offset);
  141. }
  142. static inline void regw(u32 val, u32 offset)
  143. {
  144. __raw_writel(val, isif_cfg.base_addr + offset);
  145. }
  146. /* reg_modify() - read, modify and write register */
  147. static inline u32 reg_modify(u32 mask, u32 val, u32 offset)
  148. {
  149. u32 new_val = (regr(offset) & ~mask) | (val & mask);
  150. regw(new_val, offset);
  151. return new_val;
  152. }
  153. static inline void regw_lin_tbl(u32 val, u32 offset, int i)
  154. {
  155. if (!i)
  156. __raw_writel(val, isif_cfg.linear_tbl0_addr + offset);
  157. else
  158. __raw_writel(val, isif_cfg.linear_tbl1_addr + offset);
  159. }
  160. static void isif_disable_all_modules(void)
  161. {
  162. /* disable BC */
  163. regw(0, CLAMPCFG);
  164. /* disable vdfc */
  165. regw(0, DFCCTL);
  166. /* disable CSC */
  167. regw(0, CSCCTL);
  168. /* disable linearization */
  169. regw(0, LINCFG0);
  170. /* disable other modules here as they are supported */
  171. }
  172. static void isif_enable(int en)
  173. {
  174. if (!en) {
  175. /* Before disable isif, disable all ISIF modules */
  176. isif_disable_all_modules();
  177. /*
  178. * wait for next VD. Assume lowest scan rate is 12 Hz. So
  179. * 100 msec delay is good enough
  180. */
  181. msleep(100);
  182. }
  183. reg_modify(ISIF_SYNCEN_VDHDEN_MASK, en, SYNCEN);
  184. }
  185. static void isif_enable_output_to_sdram(int en)
  186. {
  187. reg_modify(ISIF_SYNCEN_WEN_MASK, en << ISIF_SYNCEN_WEN_SHIFT, SYNCEN);
  188. }
  189. static void isif_config_culling(struct isif_cul *cul)
  190. {
  191. u32 val;
  192. /* Horizontal pattern */
  193. val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd;
  194. regw(val, CULH);
  195. /* vertical pattern */
  196. regw(cul->vcpat, CULV);
  197. /* LPF */
  198. reg_modify(ISIF_LPF_MASK << ISIF_LPF_SHIFT,
  199. cul->en_lpf << ISIF_LPF_SHIFT, MODESET);
  200. }
  201. static void isif_config_gain_offset(void)
  202. {
  203. struct isif_gain_offsets_adj *gain_off_p =
  204. &isif_cfg.bayer.config_params.gain_offset;
  205. u32 val;
  206. val = (!!gain_off_p->gain_sdram_en << GAIN_SDRAM_EN_SHIFT) |
  207. (!!gain_off_p->gain_ipipe_en << GAIN_IPIPE_EN_SHIFT) |
  208. (!!gain_off_p->gain_h3a_en << GAIN_H3A_EN_SHIFT) |
  209. (!!gain_off_p->offset_sdram_en << OFST_SDRAM_EN_SHIFT) |
  210. (!!gain_off_p->offset_ipipe_en << OFST_IPIPE_EN_SHIFT) |
  211. (!!gain_off_p->offset_h3a_en << OFST_H3A_EN_SHIFT);
  212. reg_modify(GAIN_OFFSET_EN_MASK, val, CGAMMAWD);
  213. val = (gain_off_p->gain.r_ye.integer << GAIN_INTEGER_SHIFT) |
  214. gain_off_p->gain.r_ye.decimal;
  215. regw(val, CRGAIN);
  216. val = (gain_off_p->gain.gr_cy.integer << GAIN_INTEGER_SHIFT) |
  217. gain_off_p->gain.gr_cy.decimal;
  218. regw(val, CGRGAIN);
  219. val = (gain_off_p->gain.gb_g.integer << GAIN_INTEGER_SHIFT) |
  220. gain_off_p->gain.gb_g.decimal;
  221. regw(val, CGBGAIN);
  222. val = (gain_off_p->gain.b_mg.integer << GAIN_INTEGER_SHIFT) |
  223. gain_off_p->gain.b_mg.decimal;
  224. regw(val, CBGAIN);
  225. regw(gain_off_p->offset, COFSTA);
  226. }
  227. static void isif_restore_defaults(void)
  228. {
  229. enum vpss_ccdc_source_sel source = VPSS_CCDCIN;
  230. dev_dbg(isif_cfg.dev, "\nstarting isif_restore_defaults...");
  231. isif_cfg.bayer.config_params = isif_config_defaults;
  232. /* Enable clock to ISIF, IPIPEIF and BL */
  233. vpss_enable_clock(VPSS_CCDC_CLOCK, 1);
  234. vpss_enable_clock(VPSS_IPIPEIF_CLOCK, 1);
  235. vpss_enable_clock(VPSS_BL_CLOCK, 1);
  236. /* Set default offset and gain */
  237. isif_config_gain_offset();
  238. vpss_select_ccdc_source(source);
  239. dev_dbg(isif_cfg.dev, "\nEnd of isif_restore_defaults...");
  240. }
  241. static int isif_open(struct device *device)
  242. {
  243. isif_restore_defaults();
  244. return 0;
  245. }
  246. /* This function will configure the window size to be capture in ISIF reg */
  247. static void isif_setwin(struct v4l2_rect *image_win,
  248. enum ccdc_frmfmt frm_fmt, int ppc)
  249. {
  250. int horz_start, horz_nr_pixels;
  251. int vert_start, vert_nr_lines;
  252. int mid_img = 0;
  253. dev_dbg(isif_cfg.dev, "\nStarting isif_setwin...");
  254. /*
  255. * ppc - per pixel count. indicates how many pixels per cell
  256. * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
  257. * raw capture this is 1
  258. */
  259. horz_start = image_win->left << (ppc - 1);
  260. horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
  261. /* Writing the horizontal info into the registers */
  262. regw(horz_start & START_PX_HOR_MASK, SPH);
  263. regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH);
  264. vert_start = image_win->top;
  265. if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
  266. vert_nr_lines = (image_win->height >> 1) - 1;
  267. vert_start >>= 1;
  268. /* To account for VD since line 0 doesn't have any data */
  269. vert_start += 1;
  270. } else {
  271. /* To account for VD since line 0 doesn't have any data */
  272. vert_start += 1;
  273. vert_nr_lines = image_win->height - 1;
  274. /* configure VDINT0 and VDINT1 */
  275. mid_img = vert_start + (image_win->height / 2);
  276. regw(mid_img, VDINT1);
  277. }
  278. regw(0, VDINT0);
  279. regw(vert_start & START_VER_ONE_MASK, SLV0);
  280. regw(vert_start & START_VER_TWO_MASK, SLV1);
  281. regw(vert_nr_lines & NUM_LINES_VER, LNV);
  282. }
  283. static void isif_config_bclamp(struct isif_black_clamp *bc)
  284. {
  285. u32 val;
  286. /*
  287. * DC Offset is always added to image data irrespective of bc enable
  288. * status
  289. */
  290. regw(bc->dc_offset, CLDCOFST);
  291. if (bc->en) {
  292. val = bc->bc_mode_color << ISIF_BC_MODE_COLOR_SHIFT;
  293. /* Enable BC and horizontal clamp caculation paramaters */
  294. val = val | 1 | (bc->horz.mode << ISIF_HORZ_BC_MODE_SHIFT);
  295. regw(val, CLAMPCFG);
  296. if (bc->horz.mode != ISIF_HORZ_BC_DISABLE) {
  297. /*
  298. * Window count for calculation
  299. * Base window selection
  300. * pixel limit
  301. * Horizontal size of window
  302. * vertical size of the window
  303. * Horizontal start position of the window
  304. * Vertical start position of the window
  305. */
  306. val = bc->horz.win_count_calc |
  307. ((!!bc->horz.base_win_sel_calc) <<
  308. ISIF_HORZ_BC_WIN_SEL_SHIFT) |
  309. ((!!bc->horz.clamp_pix_limit) <<
  310. ISIF_HORZ_BC_PIX_LIMIT_SHIFT) |
  311. (bc->horz.win_h_sz_calc <<
  312. ISIF_HORZ_BC_WIN_H_SIZE_SHIFT) |
  313. (bc->horz.win_v_sz_calc <<
  314. ISIF_HORZ_BC_WIN_V_SIZE_SHIFT);
  315. regw(val, CLHWIN0);
  316. regw(bc->horz.win_start_h_calc, CLHWIN1);
  317. regw(bc->horz.win_start_v_calc, CLHWIN2);
  318. }
  319. /* vertical clamp caculation paramaters */
  320. /* Reset clamp value sel for previous line */
  321. val |=
  322. (bc->vert.reset_val_sel << ISIF_VERT_BC_RST_VAL_SEL_SHIFT) |
  323. (bc->vert.line_ave_coef << ISIF_VERT_BC_LINE_AVE_COEF_SHIFT);
  324. regw(val, CLVWIN0);
  325. /* Optical Black horizontal start position */
  326. regw(bc->vert.ob_start_h, CLVWIN1);
  327. /* Optical Black vertical start position */
  328. regw(bc->vert.ob_start_v, CLVWIN2);
  329. /* Optical Black vertical size for calculation */
  330. regw(bc->vert.ob_v_sz_calc, CLVWIN3);
  331. /* Vertical start position for BC subtraction */
  332. regw(bc->vert_start_sub, CLSV);
  333. }
  334. }
  335. static void isif_config_linearization(struct isif_linearize *linearize)
  336. {
  337. u32 val, i;
  338. if (!linearize->en) {
  339. regw(0, LINCFG0);
  340. return;
  341. }
  342. /* shift value for correction & enable linearization (set lsb) */
  343. val = (linearize->corr_shft << ISIF_LIN_CORRSFT_SHIFT) | 1;
  344. regw(val, LINCFG0);
  345. /* Scale factor */
  346. val = ((!!linearize->scale_fact.integer) <<
  347. ISIF_LIN_SCALE_FACT_INTEG_SHIFT) |
  348. linearize->scale_fact.decimal;
  349. regw(val, LINCFG1);
  350. for (i = 0; i < ISIF_LINEAR_TAB_SIZE; i++) {
  351. if (i % 2)
  352. regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 1);
  353. else
  354. regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 0);
  355. }
  356. }
  357. static int isif_config_dfc(struct isif_dfc *vdfc)
  358. {
  359. /* initialize retries to loop for max ~ 250 usec */
  360. u32 val, count, retries = loops_per_jiffy / (4000/HZ);
  361. int i;
  362. if (!vdfc->en)
  363. return 0;
  364. /* Correction mode */
  365. val = (vdfc->corr_mode << ISIF_VDFC_CORR_MOD_SHIFT);
  366. /* Correct whole line or partial */
  367. if (vdfc->corr_whole_line)
  368. val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT;
  369. /* level shift value */
  370. val |= vdfc->def_level_shift << ISIF_VDFC_LEVEL_SHFT_SHIFT;
  371. regw(val, DFCCTL);
  372. /* Defect saturation level */
  373. regw(vdfc->def_sat_level, VDFSATLV);
  374. regw(vdfc->table[0].pos_vert, DFCMEM0);
  375. regw(vdfc->table[0].pos_horz, DFCMEM1);
  376. if (vdfc->corr_mode == ISIF_VDFC_NORMAL ||
  377. vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) {
  378. regw(vdfc->table[0].level_at_pos, DFCMEM2);
  379. regw(vdfc->table[0].level_up_pixels, DFCMEM3);
  380. regw(vdfc->table[0].level_low_pixels, DFCMEM4);
  381. }
  382. /* set DFCMARST and set DFCMWR */
  383. val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1;
  384. regw(val, DFCMEMCTL);
  385. count = retries;
  386. while (count && (regr(DFCMEMCTL) & 0x1))
  387. count--;
  388. if (!count) {
  389. dev_dbg(isif_cfg.dev, "defect table write timeout !!!\n");
  390. return -1;
  391. }
  392. for (i = 1; i < vdfc->num_vdefects; i++) {
  393. regw(vdfc->table[i].pos_vert, DFCMEM0);
  394. regw(vdfc->table[i].pos_horz, DFCMEM1);
  395. if (vdfc->corr_mode == ISIF_VDFC_NORMAL ||
  396. vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) {
  397. regw(vdfc->table[i].level_at_pos, DFCMEM2);
  398. regw(vdfc->table[i].level_up_pixels, DFCMEM3);
  399. regw(vdfc->table[i].level_low_pixels, DFCMEM4);
  400. }
  401. val = regr(DFCMEMCTL);
  402. /* clear DFCMARST and set DFCMWR */
  403. val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT);
  404. val |= 1;
  405. regw(val, DFCMEMCTL);
  406. count = retries;
  407. while (count && (regr(DFCMEMCTL) & 0x1))
  408. count--;
  409. if (!count) {
  410. dev_err(isif_cfg.dev,
  411. "defect table write timeout !!!\n");
  412. return -1;
  413. }
  414. }
  415. if (vdfc->num_vdefects < ISIF_VDFC_TABLE_SIZE) {
  416. /* Extra cycle needed */
  417. regw(0, DFCMEM0);
  418. regw(0x1FFF, DFCMEM1);
  419. regw(1, DFCMEMCTL);
  420. }
  421. /* enable VDFC */
  422. reg_modify((1 << ISIF_VDFC_EN_SHIFT), (1 << ISIF_VDFC_EN_SHIFT),
  423. DFCCTL);
  424. return 0;
  425. }
  426. static void isif_config_csc(struct isif_df_csc *df_csc)
  427. {
  428. u32 val1 = 0, val2 = 0, i;
  429. if (!df_csc->csc.en) {
  430. regw(0, CSCCTL);
  431. return;
  432. }
  433. for (i = 0; i < ISIF_CSC_NUM_COEFF; i++) {
  434. if ((i % 2) == 0) {
  435. /* CSCM - LSB */
  436. val1 = (df_csc->csc.coeff[i].integer <<
  437. ISIF_CSC_COEF_INTEG_SHIFT) |
  438. df_csc->csc.coeff[i].decimal;
  439. } else {
  440. /* CSCM - MSB */
  441. val2 = (df_csc->csc.coeff[i].integer <<
  442. ISIF_CSC_COEF_INTEG_SHIFT) |
  443. df_csc->csc.coeff[i].decimal;
  444. val2 <<= ISIF_CSCM_MSB_SHIFT;
  445. val2 |= val1;
  446. regw(val2, (CSCM0 + ((i - 1) << 1)));
  447. }
  448. }
  449. /* program the active area */
  450. regw(df_csc->start_pix, FMTSPH);
  451. /*
  452. * one extra pixel as required for CSC. Actually number of
  453. * pixel - 1 should be configured in this register. So we
  454. * need to subtract 1 before writing to FMTSPH, but we will
  455. * not do this since csc requires one extra pixel
  456. */
  457. regw(df_csc->num_pixels, FMTLNH);
  458. regw(df_csc->start_line, FMTSLV);
  459. /*
  460. * one extra line as required for CSC. See reason documented for
  461. * num_pixels
  462. */
  463. regw(df_csc->num_lines, FMTLNV);
  464. /* Enable CSC */
  465. regw(1, CSCCTL);
  466. }
  467. static int isif_config_raw(void)
  468. {
  469. struct isif_params_raw *params = &isif_cfg.bayer;
  470. struct isif_config_params_raw *module_params =
  471. &isif_cfg.bayer.config_params;
  472. struct vpss_pg_frame_size frame_size;
  473. struct vpss_sync_pol sync;
  474. u32 val;
  475. dev_dbg(isif_cfg.dev, "\nStarting isif_config_raw..\n");
  476. /*
  477. * Configure CCDCFG register:-
  478. * Set CCD Not to swap input since input is RAW data
  479. * Set FID detection function to Latch at V-Sync
  480. * Set WENLOG - isif valid area
  481. * Set TRGSEL
  482. * Set EXTRG
  483. * Packed to 8 or 16 bits
  484. */
  485. val = ISIF_YCINSWP_RAW | ISIF_CCDCFG_FIDMD_LATCH_VSYNC |
  486. ISIF_CCDCFG_WENLOG_AND | ISIF_CCDCFG_TRGSEL_WEN |
  487. ISIF_CCDCFG_EXTRG_DISABLE | isif_cfg.data_pack;
  488. dev_dbg(isif_cfg.dev, "Writing 0x%x to ...CCDCFG \n", val);
  489. regw(val, CCDCFG);
  490. /*
  491. * Configure the vertical sync polarity(MODESET.VDPOL)
  492. * Configure the horizontal sync polarity (MODESET.HDPOL)
  493. * Configure frame id polarity (MODESET.FLDPOL)
  494. * Configure data polarity
  495. * Configure External WEN Selection
  496. * Configure frame format(progressive or interlace)
  497. * Configure pixel format (Input mode)
  498. * Configure the data shift
  499. */
  500. val = ISIF_VDHDOUT_INPUT | (params->vd_pol << ISIF_VD_POL_SHIFT) |
  501. (params->hd_pol << ISIF_HD_POL_SHIFT) |
  502. (params->fid_pol << ISIF_FID_POL_SHIFT) |
  503. (ISIF_DATAPOL_NORMAL << ISIF_DATAPOL_SHIFT) |
  504. (ISIF_EXWEN_DISABLE << ISIF_EXWEN_SHIFT) |
  505. (params->frm_fmt << ISIF_FRM_FMT_SHIFT) |
  506. (params->pix_fmt << ISIF_INPUT_SHIFT) |
  507. (params->config_params.data_shift << ISIF_DATASFT_SHIFT);
  508. regw(val, MODESET);
  509. dev_dbg(isif_cfg.dev, "Writing 0x%x to MODESET...\n", val);
  510. /*
  511. * Configure GAMMAWD register
  512. * CFA pattern setting
  513. */
  514. val = params->cfa_pat << ISIF_GAMMAWD_CFA_SHIFT;
  515. /* Gamma msb */
  516. if (module_params->compress.alg == ISIF_ALAW)
  517. val |= ISIF_ALAW_ENABLE;
  518. val |= (params->data_msb << ISIF_ALAW_GAMMA_WD_SHIFT);
  519. regw(val, CGAMMAWD);
  520. /* Configure DPCM compression settings */
  521. if (module_params->compress.alg == ISIF_DPCM) {
  522. val = BIT(ISIF_DPCM_EN_SHIFT) |
  523. (module_params->compress.pred <<
  524. ISIF_DPCM_PREDICTOR_SHIFT);
  525. }
  526. regw(val, MISC);
  527. /* Configure Gain & Offset */
  528. isif_config_gain_offset();
  529. /* Configure Color pattern */
  530. val = (params->config_params.col_pat_field0.olop) |
  531. (params->config_params.col_pat_field0.olep << 2) |
  532. (params->config_params.col_pat_field0.elop << 4) |
  533. (params->config_params.col_pat_field0.elep << 6) |
  534. (params->config_params.col_pat_field1.olop << 8) |
  535. (params->config_params.col_pat_field1.olep << 10) |
  536. (params->config_params.col_pat_field1.elop << 12) |
  537. (params->config_params.col_pat_field1.elep << 14);
  538. regw(val, CCOLP);
  539. dev_dbg(isif_cfg.dev, "Writing %x to CCOLP ...\n", val);
  540. /* Configure HSIZE register */
  541. val = (!!params->horz_flip_en) << ISIF_HSIZE_FLIP_SHIFT;
  542. /* calculate line offset in 32 bytes based on pack value */
  543. if (isif_cfg.data_pack == ISIF_PACK_8BIT)
  544. val |= ((params->win.width + 31) >> 5);
  545. else if (isif_cfg.data_pack == ISIF_PACK_12BIT)
  546. val |= (((params->win.width +
  547. (params->win.width >> 2)) + 31) >> 5);
  548. else
  549. val |= (((params->win.width * 2) + 31) >> 5);
  550. regw(val, HSIZE);
  551. /* Configure SDOFST register */
  552. if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
  553. if (params->image_invert_en) {
  554. /* For interlace inverse mode */
  555. regw(0x4B6D, SDOFST);
  556. dev_dbg(isif_cfg.dev, "Writing 0x4B6D to SDOFST...\n");
  557. } else {
  558. /* For interlace non inverse mode */
  559. regw(0x0B6D, SDOFST);
  560. dev_dbg(isif_cfg.dev, "Writing 0x0B6D to SDOFST...\n");
  561. }
  562. } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
  563. if (params->image_invert_en) {
  564. /* For progressive inverse mode */
  565. regw(0x4000, SDOFST);
  566. dev_dbg(isif_cfg.dev, "Writing 0x4000 to SDOFST...\n");
  567. } else {
  568. /* For progressive non inverse mode */
  569. regw(0x0000, SDOFST);
  570. dev_dbg(isif_cfg.dev, "Writing 0x0000 to SDOFST...\n");
  571. }
  572. }
  573. /* Configure video window */
  574. isif_setwin(&params->win, params->frm_fmt, 1);
  575. /* Configure Black Clamp */
  576. isif_config_bclamp(&module_params->bclamp);
  577. /* Configure Vertical Defection Pixel Correction */
  578. if (isif_config_dfc(&module_params->dfc) < 0)
  579. return -EFAULT;
  580. if (!module_params->df_csc.df_or_csc)
  581. /* Configure Color Space Conversion */
  582. isif_config_csc(&module_params->df_csc);
  583. isif_config_linearization(&module_params->linearize);
  584. /* Configure Culling */
  585. isif_config_culling(&module_params->culling);
  586. /* Configure horizontal and vertical offsets(DFC,LSC,Gain) */
  587. regw(module_params->horz_offset, DATAHOFST);
  588. regw(module_params->vert_offset, DATAVOFST);
  589. /* Setup test pattern if enabled */
  590. if (params->config_params.test_pat_gen) {
  591. /* Use the HD/VD pol settings from user */
  592. sync.ccdpg_hdpol = params->hd_pol;
  593. sync.ccdpg_vdpol = params->vd_pol;
  594. dm365_vpss_set_sync_pol(sync);
  595. frame_size.hlpfr = isif_cfg.bayer.win.width;
  596. frame_size.pplen = isif_cfg.bayer.win.height;
  597. dm365_vpss_set_pg_frame_size(frame_size);
  598. vpss_select_ccdc_source(VPSS_PGLPBK);
  599. }
  600. dev_dbg(isif_cfg.dev, "\nEnd of isif_config_ycbcr...\n");
  601. return 0;
  602. }
  603. static int isif_set_buftype(enum ccdc_buftype buf_type)
  604. {
  605. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  606. isif_cfg.bayer.buf_type = buf_type;
  607. else
  608. isif_cfg.ycbcr.buf_type = buf_type;
  609. return 0;
  610. }
  611. static enum ccdc_buftype isif_get_buftype(void)
  612. {
  613. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  614. return isif_cfg.bayer.buf_type;
  615. return isif_cfg.ycbcr.buf_type;
  616. }
  617. static int isif_enum_pix(u32 *pix, int i)
  618. {
  619. int ret = -EINVAL;
  620. if (isif_cfg.if_type == VPFE_RAW_BAYER) {
  621. if (i < ARRAY_SIZE(isif_raw_bayer_pix_formats)) {
  622. *pix = isif_raw_bayer_pix_formats[i];
  623. ret = 0;
  624. }
  625. } else {
  626. if (i < ARRAY_SIZE(isif_raw_yuv_pix_formats)) {
  627. *pix = isif_raw_yuv_pix_formats[i];
  628. ret = 0;
  629. }
  630. }
  631. return ret;
  632. }
  633. static int isif_set_pixel_format(unsigned int pixfmt)
  634. {
  635. if (isif_cfg.if_type == VPFE_RAW_BAYER) {
  636. if (pixfmt == V4L2_PIX_FMT_SBGGR8) {
  637. if ((isif_cfg.bayer.config_params.compress.alg !=
  638. ISIF_ALAW) &&
  639. (isif_cfg.bayer.config_params.compress.alg !=
  640. ISIF_DPCM)) {
  641. dev_dbg(isif_cfg.dev,
  642. "Either configure A-Law or DPCM\n");
  643. return -EINVAL;
  644. }
  645. isif_cfg.data_pack = ISIF_PACK_8BIT;
  646. } else if (pixfmt == V4L2_PIX_FMT_SBGGR16) {
  647. isif_cfg.bayer.config_params.compress.alg =
  648. ISIF_NO_COMPRESSION;
  649. isif_cfg.data_pack = ISIF_PACK_16BIT;
  650. } else
  651. return -EINVAL;
  652. isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
  653. } else {
  654. if (pixfmt == V4L2_PIX_FMT_YUYV)
  655. isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
  656. else if (pixfmt == V4L2_PIX_FMT_UYVY)
  657. isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
  658. else
  659. return -EINVAL;
  660. isif_cfg.data_pack = ISIF_PACK_8BIT;
  661. }
  662. return 0;
  663. }
  664. static u32 isif_get_pixel_format(void)
  665. {
  666. u32 pixfmt;
  667. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  668. if (isif_cfg.bayer.config_params.compress.alg == ISIF_ALAW ||
  669. isif_cfg.bayer.config_params.compress.alg == ISIF_DPCM)
  670. pixfmt = V4L2_PIX_FMT_SBGGR8;
  671. else
  672. pixfmt = V4L2_PIX_FMT_SBGGR16;
  673. else {
  674. if (isif_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
  675. pixfmt = V4L2_PIX_FMT_YUYV;
  676. else
  677. pixfmt = V4L2_PIX_FMT_UYVY;
  678. }
  679. return pixfmt;
  680. }
  681. static int isif_set_image_window(struct v4l2_rect *win)
  682. {
  683. if (isif_cfg.if_type == VPFE_RAW_BAYER) {
  684. isif_cfg.bayer.win.top = win->top;
  685. isif_cfg.bayer.win.left = win->left;
  686. isif_cfg.bayer.win.width = win->width;
  687. isif_cfg.bayer.win.height = win->height;
  688. } else {
  689. isif_cfg.ycbcr.win.top = win->top;
  690. isif_cfg.ycbcr.win.left = win->left;
  691. isif_cfg.ycbcr.win.width = win->width;
  692. isif_cfg.ycbcr.win.height = win->height;
  693. }
  694. return 0;
  695. }
  696. static void isif_get_image_window(struct v4l2_rect *win)
  697. {
  698. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  699. *win = isif_cfg.bayer.win;
  700. else
  701. *win = isif_cfg.ycbcr.win;
  702. }
  703. static unsigned int isif_get_line_length(void)
  704. {
  705. unsigned int len;
  706. if (isif_cfg.if_type == VPFE_RAW_BAYER) {
  707. if (isif_cfg.data_pack == ISIF_PACK_8BIT)
  708. len = ((isif_cfg.bayer.win.width));
  709. else if (isif_cfg.data_pack == ISIF_PACK_12BIT)
  710. len = (((isif_cfg.bayer.win.width * 2) +
  711. (isif_cfg.bayer.win.width >> 2)));
  712. else
  713. len = (((isif_cfg.bayer.win.width * 2)));
  714. } else
  715. len = (((isif_cfg.ycbcr.win.width * 2)));
  716. return ALIGN(len, 32);
  717. }
  718. static int isif_set_frame_format(enum ccdc_frmfmt frm_fmt)
  719. {
  720. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  721. isif_cfg.bayer.frm_fmt = frm_fmt;
  722. else
  723. isif_cfg.ycbcr.frm_fmt = frm_fmt;
  724. return 0;
  725. }
  726. static enum ccdc_frmfmt isif_get_frame_format(void)
  727. {
  728. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  729. return isif_cfg.bayer.frm_fmt;
  730. return isif_cfg.ycbcr.frm_fmt;
  731. }
  732. static int isif_getfid(void)
  733. {
  734. return (regr(MODESET) >> 15) & 0x1;
  735. }
  736. /* misc operations */
  737. static void isif_setfbaddr(unsigned long addr)
  738. {
  739. regw((addr >> 21) & 0x07ff, CADU);
  740. regw((addr >> 5) & 0x0ffff, CADL);
  741. }
  742. static int isif_set_hw_if_params(struct vpfe_hw_if_param *params)
  743. {
  744. isif_cfg.if_type = params->if_type;
  745. switch (params->if_type) {
  746. case VPFE_BT656:
  747. case VPFE_BT656_10BIT:
  748. case VPFE_YCBCR_SYNC_8:
  749. isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT;
  750. isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
  751. break;
  752. case VPFE_BT1120:
  753. case VPFE_YCBCR_SYNC_16:
  754. isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_16BIT;
  755. isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
  756. break;
  757. case VPFE_RAW_BAYER:
  758. isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
  759. break;
  760. default:
  761. dev_dbg(isif_cfg.dev, "Invalid interface type\n");
  762. return -EINVAL;
  763. }
  764. return 0;
  765. }
  766. /* This function will configure ISIF for YCbCr parameters. */
  767. static int isif_config_ycbcr(void)
  768. {
  769. struct isif_ycbcr_config *params = &isif_cfg.ycbcr;
  770. u32 modeset = 0, ccdcfg = 0;
  771. dev_dbg(isif_cfg.dev, "\nStarting isif_config_ycbcr...");
  772. /* configure pixel format or input mode */
  773. modeset = modeset | (params->pix_fmt << ISIF_INPUT_SHIFT) |
  774. (params->frm_fmt << ISIF_FRM_FMT_SHIFT) |
  775. (params->fid_pol << ISIF_FID_POL_SHIFT) |
  776. (params->hd_pol << ISIF_HD_POL_SHIFT) |
  777. (params->vd_pol << ISIF_VD_POL_SHIFT);
  778. /* pack the data to 8-bit ISIFCFG */
  779. switch (isif_cfg.if_type) {
  780. case VPFE_BT656:
  781. if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
  782. dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
  783. return -EINVAL;
  784. }
  785. modeset |= (VPFE_PINPOL_NEGATIVE << ISIF_VD_POL_SHIFT);
  786. regw(3, REC656IF);
  787. ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR;
  788. break;
  789. case VPFE_BT656_10BIT:
  790. if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
  791. dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
  792. return -EINVAL;
  793. }
  794. /* setup BT.656, embedded sync */
  795. regw(3, REC656IF);
  796. /* enable 10 bit mode in ccdcfg */
  797. ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR |
  798. ISIF_BW656_ENABLE;
  799. break;
  800. case VPFE_BT1120:
  801. if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
  802. dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
  803. return -EINVAL;
  804. }
  805. regw(3, REC656IF);
  806. break;
  807. case VPFE_YCBCR_SYNC_8:
  808. ccdcfg |= ISIF_DATA_PACK8;
  809. ccdcfg |= ISIF_YCINSWP_YCBCR;
  810. if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
  811. dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
  812. return -EINVAL;
  813. }
  814. break;
  815. case VPFE_YCBCR_SYNC_16:
  816. if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
  817. dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
  818. return -EINVAL;
  819. }
  820. break;
  821. default:
  822. /* should never come here */
  823. dev_dbg(isif_cfg.dev, "Invalid interface type\n");
  824. return -EINVAL;
  825. }
  826. regw(modeset, MODESET);
  827. /* Set up pix order */
  828. ccdcfg |= params->pix_order << ISIF_PIX_ORDER_SHIFT;
  829. regw(ccdcfg, CCDCFG);
  830. /* configure video window */
  831. if ((isif_cfg.if_type == VPFE_BT1120) ||
  832. (isif_cfg.if_type == VPFE_YCBCR_SYNC_16))
  833. isif_setwin(&params->win, params->frm_fmt, 1);
  834. else
  835. isif_setwin(&params->win, params->frm_fmt, 2);
  836. /*
  837. * configure the horizontal line offset
  838. * this is done by rounding up width to a multiple of 16 pixels
  839. * and multiply by two to account for y:cb:cr 4:2:2 data
  840. */
  841. regw(((((params->win.width * 2) + 31) & 0xffffffe0) >> 5), HSIZE);
  842. /* configure the memory line offset */
  843. if ((params->frm_fmt == CCDC_FRMFMT_INTERLACED) &&
  844. (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED))
  845. /* two fields are interleaved in memory */
  846. regw(0x00000249, SDOFST);
  847. return 0;
  848. }
  849. static int isif_configure(void)
  850. {
  851. if (isif_cfg.if_type == VPFE_RAW_BAYER)
  852. return isif_config_raw();
  853. return isif_config_ycbcr();
  854. }
  855. static int isif_close(struct device *device)
  856. {
  857. /* copy defaults to module params */
  858. isif_cfg.bayer.config_params = isif_config_defaults;
  859. return 0;
  860. }
  861. static const struct ccdc_hw_device isif_hw_dev = {
  862. .name = "ISIF",
  863. .owner = THIS_MODULE,
  864. .hw_ops = {
  865. .open = isif_open,
  866. .close = isif_close,
  867. .enable = isif_enable,
  868. .enable_out_to_sdram = isif_enable_output_to_sdram,
  869. .set_hw_if_params = isif_set_hw_if_params,
  870. .configure = isif_configure,
  871. .set_buftype = isif_set_buftype,
  872. .get_buftype = isif_get_buftype,
  873. .enum_pix = isif_enum_pix,
  874. .set_pixel_format = isif_set_pixel_format,
  875. .get_pixel_format = isif_get_pixel_format,
  876. .set_frame_format = isif_set_frame_format,
  877. .get_frame_format = isif_get_frame_format,
  878. .set_image_window = isif_set_image_window,
  879. .get_image_window = isif_get_image_window,
  880. .get_line_length = isif_get_line_length,
  881. .setfbaddr = isif_setfbaddr,
  882. .getfid = isif_getfid,
  883. },
  884. };
  885. static int isif_probe(struct platform_device *pdev)
  886. {
  887. void (*setup_pinmux)(void);
  888. struct resource *res;
  889. void __iomem *addr;
  890. int status = 0, i;
  891. /* Platform data holds setup_pinmux function ptr */
  892. if (!pdev->dev.platform_data)
  893. return -ENODEV;
  894. /*
  895. * first try to register with vpfe. If not correct platform, then we
  896. * don't have to iomap
  897. */
  898. status = vpfe_register_ccdc_device(&isif_hw_dev);
  899. if (status < 0)
  900. return status;
  901. setup_pinmux = pdev->dev.platform_data;
  902. /*
  903. * setup Mux configuration for ccdc which may be different for
  904. * different SoCs using this CCDC
  905. */
  906. setup_pinmux();
  907. i = 0;
  908. /* Get the ISIF base address, linearization table0 and table1 addr. */
  909. while (i < 3) {
  910. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  911. if (!res) {
  912. status = -ENODEV;
  913. goto fail_nobase_res;
  914. }
  915. res = request_mem_region(res->start, resource_size(res),
  916. res->name);
  917. if (!res) {
  918. status = -EBUSY;
  919. goto fail_nobase_res;
  920. }
  921. addr = ioremap_nocache(res->start, resource_size(res));
  922. if (!addr) {
  923. status = -ENOMEM;
  924. goto fail_base_iomap;
  925. }
  926. switch (i) {
  927. case 0:
  928. /* ISIF base address */
  929. isif_cfg.base_addr = addr;
  930. break;
  931. case 1:
  932. /* ISIF linear tbl0 address */
  933. isif_cfg.linear_tbl0_addr = addr;
  934. break;
  935. default:
  936. /* ISIF linear tbl0 address */
  937. isif_cfg.linear_tbl1_addr = addr;
  938. break;
  939. }
  940. i++;
  941. }
  942. isif_cfg.dev = &pdev->dev;
  943. printk(KERN_NOTICE "%s is registered with vpfe.\n",
  944. isif_hw_dev.name);
  945. return 0;
  946. fail_base_iomap:
  947. release_mem_region(res->start, resource_size(res));
  948. i--;
  949. fail_nobase_res:
  950. if (isif_cfg.base_addr)
  951. iounmap(isif_cfg.base_addr);
  952. if (isif_cfg.linear_tbl0_addr)
  953. iounmap(isif_cfg.linear_tbl0_addr);
  954. while (i >= 0) {
  955. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  956. if (res)
  957. release_mem_region(res->start, resource_size(res));
  958. i--;
  959. }
  960. vpfe_unregister_ccdc_device(&isif_hw_dev);
  961. return status;
  962. }
  963. static int isif_remove(struct platform_device *pdev)
  964. {
  965. struct resource *res;
  966. int i = 0;
  967. iounmap(isif_cfg.base_addr);
  968. iounmap(isif_cfg.linear_tbl0_addr);
  969. iounmap(isif_cfg.linear_tbl1_addr);
  970. while (i < 3) {
  971. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  972. if (res)
  973. release_mem_region(res->start, resource_size(res));
  974. i++;
  975. }
  976. vpfe_unregister_ccdc_device(&isif_hw_dev);
  977. return 0;
  978. }
  979. static struct platform_driver isif_driver = {
  980. .driver = {
  981. .name = "isif",
  982. },
  983. .remove = isif_remove,
  984. .probe = isif_probe,
  985. };
  986. module_platform_driver(isif_driver);
  987. MODULE_LICENSE("GPL");