mipi-csis.c 27 KB

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  1. /*
  2. * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
  3. *
  4. * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/irq.h>
  18. #include <linux/kernel.h>
  19. #include <linux/memory.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_graph.h>
  23. #include <linux/phy/phy.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/regulator/consumer.h>
  27. #include <linux/sizes.h>
  28. #include <linux/slab.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/videodev2.h>
  31. #include <media/drv-intf/exynos-fimc.h>
  32. #include <media/v4l2-fwnode.h>
  33. #include <media/v4l2-subdev.h>
  34. #include "mipi-csis.h"
  35. static int debug;
  36. module_param(debug, int, 0644);
  37. MODULE_PARM_DESC(debug, "Debug level (0-2)");
  38. /* Register map definition */
  39. /* CSIS global control */
  40. #define S5PCSIS_CTRL 0x00
  41. #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
  42. #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
  43. #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
  44. #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
  45. #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
  46. #define S5PCSIS_CTRL_RESET (1 << 4)
  47. #define S5PCSIS_CTRL_ENABLE (1 << 0)
  48. /* D-PHY control */
  49. #define S5PCSIS_DPHYCTRL 0x04
  50. #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
  51. #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
  52. #define S5PCSIS_CONFIG 0x08
  53. #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
  54. #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
  55. #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
  56. #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
  57. /* User defined formats, x = 1...4 */
  58. #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
  59. #define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
  60. #define S5PCSIS_CFG_NR_LANE_MASK 3
  61. /* Interrupt mask */
  62. #define S5PCSIS_INTMSK 0x10
  63. #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
  64. #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
  65. #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
  66. #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28)
  67. #define S5PCSIS_INTMSK_FRAME_START (1 << 27)
  68. #define S5PCSIS_INTMSK_FRAME_END (1 << 26)
  69. #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12)
  70. #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5)
  71. #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4)
  72. #define S5PCSIS_INTMSK_ERR_OVER (1 << 3)
  73. #define S5PCSIS_INTMSK_ERR_ECC (1 << 2)
  74. #define S5PCSIS_INTMSK_ERR_CRC (1 << 1)
  75. #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0)
  76. #define S5PCSIS_INTMSK_EXYNOS4_EN_ALL 0xf000103f
  77. #define S5PCSIS_INTMSK_EXYNOS5_EN_ALL 0xfc00103f
  78. /* Interrupt source */
  79. #define S5PCSIS_INTSRC 0x14
  80. #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31)
  81. #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30)
  82. #define S5PCSIS_INTSRC_EVEN (0x3 << 30)
  83. #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29)
  84. #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28)
  85. #define S5PCSIS_INTSRC_ODD (0x3 << 28)
  86. #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
  87. #define S5PCSIS_INTSRC_FRAME_START (1 << 27)
  88. #define S5PCSIS_INTSRC_FRAME_END (1 << 26)
  89. #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12)
  90. #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5)
  91. #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4)
  92. #define S5PCSIS_INTSRC_ERR_OVER (1 << 3)
  93. #define S5PCSIS_INTSRC_ERR_ECC (1 << 2)
  94. #define S5PCSIS_INTSRC_ERR_CRC (1 << 1)
  95. #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0)
  96. #define S5PCSIS_INTSRC_ERRORS 0xf03f
  97. /* Pixel resolution */
  98. #define S5PCSIS_RESOL 0x2c
  99. #define CSIS_MAX_PIX_WIDTH 0xffff
  100. #define CSIS_MAX_PIX_HEIGHT 0xffff
  101. /* Non-image packet data buffers */
  102. #define S5PCSIS_PKTDATA_ODD 0x2000
  103. #define S5PCSIS_PKTDATA_EVEN 0x3000
  104. #define S5PCSIS_PKTDATA_SIZE SZ_4K
  105. enum {
  106. CSIS_CLK_MUX,
  107. CSIS_CLK_GATE,
  108. };
  109. static char *csi_clock_name[] = {
  110. [CSIS_CLK_MUX] = "sclk_csis",
  111. [CSIS_CLK_GATE] = "csis",
  112. };
  113. #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
  114. #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
  115. static const char * const csis_supply_name[] = {
  116. "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */
  117. "vddio", /* CSIS I/O and PLL (1.8V) supply */
  118. };
  119. #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
  120. enum {
  121. ST_POWERED = 1,
  122. ST_STREAMING = 2,
  123. ST_SUSPENDED = 4,
  124. };
  125. struct s5pcsis_event {
  126. u32 mask;
  127. const char * const name;
  128. unsigned int counter;
  129. };
  130. static const struct s5pcsis_event s5pcsis_events[] = {
  131. /* Errors */
  132. { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
  133. { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
  134. { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
  135. { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
  136. { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" },
  137. { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" },
  138. { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
  139. /* Non-image data receive events */
  140. { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
  141. { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
  142. { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
  143. { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
  144. /* Frame start/end */
  145. { S5PCSIS_INTSRC_FRAME_START, "Frame Start" },
  146. { S5PCSIS_INTSRC_FRAME_END, "Frame End" },
  147. };
  148. #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
  149. struct csis_pktbuf {
  150. u32 *data;
  151. unsigned int len;
  152. };
  153. struct csis_drvdata {
  154. /* Mask of all used interrupts in S5PCSIS_INTMSK register */
  155. u32 interrupt_mask;
  156. };
  157. /**
  158. * struct csis_state - the driver's internal state data structure
  159. * @lock: mutex serializing the subdev and power management operations,
  160. * protecting @format and @flags members
  161. * @pads: CSIS pads array
  162. * @sd: v4l2_subdev associated with CSIS device instance
  163. * @index: the hardware instance index
  164. * @pdev: CSIS platform device
  165. * @phy: pointer to the CSIS generic PHY
  166. * @regs: mmaped I/O registers memory
  167. * @supplies: CSIS regulator supplies
  168. * @clock: CSIS clocks
  169. * @irq: requested s5p-mipi-csis irq number
  170. * @interrupt_mask: interrupt mask of the all used interrupts
  171. * @flags: the state variable for power and streaming control
  172. * @clk_frequency: device bus clock frequency
  173. * @hs_settle: HS-RX settle time
  174. * @num_lanes: number of MIPI-CSI data lanes used
  175. * @max_num_lanes: maximum number of MIPI-CSI data lanes supported
  176. * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM
  177. * @csis_fmt: current CSIS pixel format
  178. * @format: common media bus format for the source and sink pad
  179. * @slock: spinlock protecting structure members below
  180. * @pkt_buf: the frame embedded (non-image) data buffer
  181. * @events: MIPI-CSIS event (error) counters
  182. */
  183. struct csis_state {
  184. struct mutex lock;
  185. struct media_pad pads[CSIS_PADS_NUM];
  186. struct v4l2_subdev sd;
  187. u8 index;
  188. struct platform_device *pdev;
  189. struct phy *phy;
  190. void __iomem *regs;
  191. struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
  192. struct clk *clock[NUM_CSIS_CLOCKS];
  193. int irq;
  194. u32 interrupt_mask;
  195. u32 flags;
  196. u32 clk_frequency;
  197. u32 hs_settle;
  198. u32 num_lanes;
  199. u32 max_num_lanes;
  200. u8 wclk_ext;
  201. const struct csis_pix_format *csis_fmt;
  202. struct v4l2_mbus_framefmt format;
  203. spinlock_t slock;
  204. struct csis_pktbuf pkt_buf;
  205. struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
  206. };
  207. /**
  208. * struct csis_pix_format - CSIS pixel format description
  209. * @pix_width_alignment: horizontal pixel alignment, width will be
  210. * multiple of 2^pix_width_alignment
  211. * @code: corresponding media bus code
  212. * @fmt_reg: S5PCSIS_CONFIG register value
  213. * @data_alignment: MIPI-CSI data alignment in bits
  214. */
  215. struct csis_pix_format {
  216. unsigned int pix_width_alignment;
  217. u32 code;
  218. u32 fmt_reg;
  219. u8 data_alignment;
  220. };
  221. static const struct csis_pix_format s5pcsis_formats[] = {
  222. {
  223. .code = MEDIA_BUS_FMT_VYUY8_2X8,
  224. .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
  225. .data_alignment = 32,
  226. }, {
  227. .code = MEDIA_BUS_FMT_JPEG_1X8,
  228. .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
  229. .data_alignment = 32,
  230. }, {
  231. .code = MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8,
  232. .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
  233. .data_alignment = 32,
  234. }, {
  235. .code = MEDIA_BUS_FMT_SGRBG8_1X8,
  236. .fmt_reg = S5PCSIS_CFG_FMT_RAW8,
  237. .data_alignment = 24,
  238. }, {
  239. .code = MEDIA_BUS_FMT_SGRBG10_1X10,
  240. .fmt_reg = S5PCSIS_CFG_FMT_RAW10,
  241. .data_alignment = 24,
  242. }, {
  243. .code = MEDIA_BUS_FMT_SGRBG12_1X12,
  244. .fmt_reg = S5PCSIS_CFG_FMT_RAW12,
  245. .data_alignment = 24,
  246. }
  247. };
  248. #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
  249. #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
  250. static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
  251. {
  252. return container_of(sdev, struct csis_state, sd);
  253. }
  254. static const struct csis_pix_format *find_csis_format(
  255. struct v4l2_mbus_framefmt *mf)
  256. {
  257. int i;
  258. for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
  259. if (mf->code == s5pcsis_formats[i].code)
  260. return &s5pcsis_formats[i];
  261. return NULL;
  262. }
  263. static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
  264. {
  265. u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
  266. if (on)
  267. val |= state->interrupt_mask;
  268. else
  269. val &= ~state->interrupt_mask;
  270. s5pcsis_write(state, S5PCSIS_INTMSK, val);
  271. }
  272. static void s5pcsis_reset(struct csis_state *state)
  273. {
  274. u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
  275. s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
  276. udelay(10);
  277. }
  278. static void s5pcsis_system_enable(struct csis_state *state, int on)
  279. {
  280. u32 val, mask;
  281. val = s5pcsis_read(state, S5PCSIS_CTRL);
  282. if (on)
  283. val |= S5PCSIS_CTRL_ENABLE;
  284. else
  285. val &= ~S5PCSIS_CTRL_ENABLE;
  286. s5pcsis_write(state, S5PCSIS_CTRL, val);
  287. val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
  288. val &= ~S5PCSIS_DPHYCTRL_ENABLE;
  289. if (on) {
  290. mask = (1 << (state->num_lanes + 1)) - 1;
  291. val |= (mask & S5PCSIS_DPHYCTRL_ENABLE);
  292. }
  293. s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
  294. }
  295. /* Called with the state.lock mutex held */
  296. static void __s5pcsis_set_format(struct csis_state *state)
  297. {
  298. struct v4l2_mbus_framefmt *mf = &state->format;
  299. u32 val;
  300. v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n",
  301. mf->code, mf->width, mf->height);
  302. /* Color format */
  303. val = s5pcsis_read(state, S5PCSIS_CONFIG);
  304. val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
  305. s5pcsis_write(state, S5PCSIS_CONFIG, val);
  306. /* Pixel resolution */
  307. val = (mf->width << 16) | mf->height;
  308. s5pcsis_write(state, S5PCSIS_RESOL, val);
  309. }
  310. static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
  311. {
  312. u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
  313. val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
  314. s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
  315. }
  316. static void s5pcsis_set_params(struct csis_state *state)
  317. {
  318. u32 val;
  319. val = s5pcsis_read(state, S5PCSIS_CONFIG);
  320. val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1);
  321. s5pcsis_write(state, S5PCSIS_CONFIG, val);
  322. __s5pcsis_set_format(state);
  323. s5pcsis_set_hsync_settle(state, state->hs_settle);
  324. val = s5pcsis_read(state, S5PCSIS_CTRL);
  325. if (state->csis_fmt->data_alignment == 32)
  326. val |= S5PCSIS_CTRL_ALIGN_32BIT;
  327. else /* 24-bits */
  328. val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
  329. val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
  330. if (state->wclk_ext)
  331. val |= S5PCSIS_CTRL_WCLK_EXTCLK;
  332. s5pcsis_write(state, S5PCSIS_CTRL, val);
  333. /* Update the shadow register. */
  334. val = s5pcsis_read(state, S5PCSIS_CTRL);
  335. s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
  336. }
  337. static void s5pcsis_clk_put(struct csis_state *state)
  338. {
  339. int i;
  340. for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
  341. if (IS_ERR(state->clock[i]))
  342. continue;
  343. clk_unprepare(state->clock[i]);
  344. clk_put(state->clock[i]);
  345. state->clock[i] = ERR_PTR(-EINVAL);
  346. }
  347. }
  348. static int s5pcsis_clk_get(struct csis_state *state)
  349. {
  350. struct device *dev = &state->pdev->dev;
  351. int i, ret;
  352. for (i = 0; i < NUM_CSIS_CLOCKS; i++)
  353. state->clock[i] = ERR_PTR(-EINVAL);
  354. for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
  355. state->clock[i] = clk_get(dev, csi_clock_name[i]);
  356. if (IS_ERR(state->clock[i])) {
  357. ret = PTR_ERR(state->clock[i]);
  358. goto err;
  359. }
  360. ret = clk_prepare(state->clock[i]);
  361. if (ret < 0) {
  362. clk_put(state->clock[i]);
  363. state->clock[i] = ERR_PTR(-EINVAL);
  364. goto err;
  365. }
  366. }
  367. return 0;
  368. err:
  369. s5pcsis_clk_put(state);
  370. dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
  371. return ret;
  372. }
  373. static void dump_regs(struct csis_state *state, const char *label)
  374. {
  375. struct {
  376. u32 offset;
  377. const char * const name;
  378. } registers[] = {
  379. { 0x00, "CTRL" },
  380. { 0x04, "DPHYCTRL" },
  381. { 0x08, "CONFIG" },
  382. { 0x0c, "DPHYSTS" },
  383. { 0x10, "INTMSK" },
  384. { 0x2c, "RESOL" },
  385. { 0x38, "SDW_CONFIG" },
  386. };
  387. u32 i;
  388. v4l2_info(&state->sd, "--- %s ---\n", label);
  389. for (i = 0; i < ARRAY_SIZE(registers); i++) {
  390. u32 cfg = s5pcsis_read(state, registers[i].offset);
  391. v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg);
  392. }
  393. }
  394. static void s5pcsis_start_stream(struct csis_state *state)
  395. {
  396. s5pcsis_reset(state);
  397. s5pcsis_set_params(state);
  398. s5pcsis_system_enable(state, true);
  399. s5pcsis_enable_interrupts(state, true);
  400. }
  401. static void s5pcsis_stop_stream(struct csis_state *state)
  402. {
  403. s5pcsis_enable_interrupts(state, false);
  404. s5pcsis_system_enable(state, false);
  405. }
  406. static void s5pcsis_clear_counters(struct csis_state *state)
  407. {
  408. unsigned long flags;
  409. int i;
  410. spin_lock_irqsave(&state->slock, flags);
  411. for (i = 0; i < S5PCSIS_NUM_EVENTS; i++)
  412. state->events[i].counter = 0;
  413. spin_unlock_irqrestore(&state->slock, flags);
  414. }
  415. static void s5pcsis_log_counters(struct csis_state *state, bool non_errors)
  416. {
  417. int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4;
  418. unsigned long flags;
  419. spin_lock_irqsave(&state->slock, flags);
  420. for (i--; i >= 0; i--) {
  421. if (state->events[i].counter > 0 || debug)
  422. v4l2_info(&state->sd, "%s events: %d\n",
  423. state->events[i].name,
  424. state->events[i].counter);
  425. }
  426. spin_unlock_irqrestore(&state->slock, flags);
  427. }
  428. /*
  429. * V4L2 subdev operations
  430. */
  431. static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
  432. {
  433. struct csis_state *state = sd_to_csis_state(sd);
  434. struct device *dev = &state->pdev->dev;
  435. if (on)
  436. return pm_runtime_get_sync(dev);
  437. return pm_runtime_put_sync(dev);
  438. }
  439. static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
  440. {
  441. struct csis_state *state = sd_to_csis_state(sd);
  442. int ret = 0;
  443. v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
  444. __func__, enable, state->flags);
  445. if (enable) {
  446. s5pcsis_clear_counters(state);
  447. ret = pm_runtime_get_sync(&state->pdev->dev);
  448. if (ret && ret != 1) {
  449. pm_runtime_put_noidle(&state->pdev->dev);
  450. return ret;
  451. }
  452. }
  453. mutex_lock(&state->lock);
  454. if (enable) {
  455. if (state->flags & ST_SUSPENDED) {
  456. ret = -EBUSY;
  457. goto unlock;
  458. }
  459. s5pcsis_start_stream(state);
  460. state->flags |= ST_STREAMING;
  461. } else {
  462. s5pcsis_stop_stream(state);
  463. state->flags &= ~ST_STREAMING;
  464. if (debug > 0)
  465. s5pcsis_log_counters(state, true);
  466. }
  467. unlock:
  468. mutex_unlock(&state->lock);
  469. if (!enable)
  470. pm_runtime_put(&state->pdev->dev);
  471. return ret == 1 ? 0 : ret;
  472. }
  473. static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
  474. struct v4l2_subdev_pad_config *cfg,
  475. struct v4l2_subdev_mbus_code_enum *code)
  476. {
  477. if (code->index >= ARRAY_SIZE(s5pcsis_formats))
  478. return -EINVAL;
  479. code->code = s5pcsis_formats[code->index].code;
  480. return 0;
  481. }
  482. static struct csis_pix_format const *s5pcsis_try_format(
  483. struct v4l2_mbus_framefmt *mf)
  484. {
  485. struct csis_pix_format const *csis_fmt;
  486. csis_fmt = find_csis_format(mf);
  487. if (csis_fmt == NULL)
  488. csis_fmt = &s5pcsis_formats[0];
  489. mf->code = csis_fmt->code;
  490. v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
  491. csis_fmt->pix_width_alignment,
  492. &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
  493. 0);
  494. return csis_fmt;
  495. }
  496. static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
  497. struct csis_state *state, struct v4l2_subdev_pad_config *cfg,
  498. enum v4l2_subdev_format_whence which)
  499. {
  500. if (which == V4L2_SUBDEV_FORMAT_TRY)
  501. return cfg ? v4l2_subdev_get_try_format(&state->sd, cfg, 0) : NULL;
  502. return &state->format;
  503. }
  504. static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
  505. struct v4l2_subdev_format *fmt)
  506. {
  507. struct csis_state *state = sd_to_csis_state(sd);
  508. struct csis_pix_format const *csis_fmt;
  509. struct v4l2_mbus_framefmt *mf;
  510. mf = __s5pcsis_get_format(state, cfg, fmt->which);
  511. if (fmt->pad == CSIS_PAD_SOURCE) {
  512. if (mf) {
  513. mutex_lock(&state->lock);
  514. fmt->format = *mf;
  515. mutex_unlock(&state->lock);
  516. }
  517. return 0;
  518. }
  519. csis_fmt = s5pcsis_try_format(&fmt->format);
  520. if (mf) {
  521. mutex_lock(&state->lock);
  522. *mf = fmt->format;
  523. if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  524. state->csis_fmt = csis_fmt;
  525. mutex_unlock(&state->lock);
  526. }
  527. return 0;
  528. }
  529. static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
  530. struct v4l2_subdev_format *fmt)
  531. {
  532. struct csis_state *state = sd_to_csis_state(sd);
  533. struct v4l2_mbus_framefmt *mf;
  534. mf = __s5pcsis_get_format(state, cfg, fmt->which);
  535. if (!mf)
  536. return -EINVAL;
  537. mutex_lock(&state->lock);
  538. fmt->format = *mf;
  539. mutex_unlock(&state->lock);
  540. return 0;
  541. }
  542. static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf,
  543. unsigned int *size)
  544. {
  545. struct csis_state *state = sd_to_csis_state(sd);
  546. unsigned long flags;
  547. *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE);
  548. spin_lock_irqsave(&state->slock, flags);
  549. state->pkt_buf.data = buf;
  550. state->pkt_buf.len = *size;
  551. spin_unlock_irqrestore(&state->slock, flags);
  552. return 0;
  553. }
  554. static int s5pcsis_log_status(struct v4l2_subdev *sd)
  555. {
  556. struct csis_state *state = sd_to_csis_state(sd);
  557. mutex_lock(&state->lock);
  558. s5pcsis_log_counters(state, true);
  559. if (debug && (state->flags & ST_POWERED))
  560. dump_regs(state, __func__);
  561. mutex_unlock(&state->lock);
  562. return 0;
  563. }
  564. static const struct v4l2_subdev_core_ops s5pcsis_core_ops = {
  565. .s_power = s5pcsis_s_power,
  566. .log_status = s5pcsis_log_status,
  567. };
  568. static const struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
  569. .enum_mbus_code = s5pcsis_enum_mbus_code,
  570. .get_fmt = s5pcsis_get_fmt,
  571. .set_fmt = s5pcsis_set_fmt,
  572. };
  573. static const struct v4l2_subdev_video_ops s5pcsis_video_ops = {
  574. .s_rx_buffer = s5pcsis_s_rx_buffer,
  575. .s_stream = s5pcsis_s_stream,
  576. };
  577. static const struct v4l2_subdev_ops s5pcsis_subdev_ops = {
  578. .core = &s5pcsis_core_ops,
  579. .pad = &s5pcsis_pad_ops,
  580. .video = &s5pcsis_video_ops,
  581. };
  582. static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
  583. {
  584. struct csis_state *state = dev_id;
  585. struct csis_pktbuf *pktbuf = &state->pkt_buf;
  586. unsigned long flags;
  587. u32 status;
  588. status = s5pcsis_read(state, S5PCSIS_INTSRC);
  589. spin_lock_irqsave(&state->slock, flags);
  590. if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
  591. u32 offset;
  592. if (status & S5PCSIS_INTSRC_EVEN)
  593. offset = S5PCSIS_PKTDATA_EVEN;
  594. else
  595. offset = S5PCSIS_PKTDATA_ODD;
  596. memcpy(pktbuf->data, (u8 __force *)state->regs + offset,
  597. pktbuf->len);
  598. pktbuf->data = NULL;
  599. rmb();
  600. }
  601. /* Update the event/error counters */
  602. if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
  603. int i;
  604. for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) {
  605. if (!(status & state->events[i].mask))
  606. continue;
  607. state->events[i].counter++;
  608. v4l2_dbg(2, debug, &state->sd, "%s: %d\n",
  609. state->events[i].name,
  610. state->events[i].counter);
  611. }
  612. v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status);
  613. }
  614. spin_unlock_irqrestore(&state->slock, flags);
  615. s5pcsis_write(state, S5PCSIS_INTSRC, status);
  616. return IRQ_HANDLED;
  617. }
  618. static int s5pcsis_parse_dt(struct platform_device *pdev,
  619. struct csis_state *state)
  620. {
  621. struct device_node *node = pdev->dev.of_node;
  622. struct v4l2_fwnode_endpoint endpoint;
  623. int ret;
  624. if (of_property_read_u32(node, "clock-frequency",
  625. &state->clk_frequency))
  626. state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
  627. if (of_property_read_u32(node, "bus-width",
  628. &state->max_num_lanes))
  629. return -EINVAL;
  630. node = of_graph_get_next_endpoint(node, NULL);
  631. if (!node) {
  632. dev_err(&pdev->dev, "No port node at %pOF\n",
  633. pdev->dev.of_node);
  634. return -EINVAL;
  635. }
  636. /* Get port node and validate MIPI-CSI channel id. */
  637. ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &endpoint);
  638. if (ret)
  639. goto err;
  640. state->index = endpoint.base.port - FIMC_INPUT_MIPI_CSI2_0;
  641. if (state->index >= CSIS_MAX_ENTITIES) {
  642. ret = -ENXIO;
  643. goto err;
  644. }
  645. /* Get MIPI CSI-2 bus configration from the endpoint node. */
  646. of_property_read_u32(node, "samsung,csis-hs-settle",
  647. &state->hs_settle);
  648. state->wclk_ext = of_property_read_bool(node,
  649. "samsung,csis-wclk");
  650. state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes;
  651. err:
  652. of_node_put(node);
  653. return ret;
  654. }
  655. static int s5pcsis_pm_resume(struct device *dev, bool runtime);
  656. static const struct of_device_id s5pcsis_of_match[];
  657. static int s5pcsis_probe(struct platform_device *pdev)
  658. {
  659. const struct of_device_id *of_id;
  660. const struct csis_drvdata *drv_data;
  661. struct device *dev = &pdev->dev;
  662. struct resource *mem_res;
  663. struct csis_state *state;
  664. int ret = -ENOMEM;
  665. int i;
  666. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  667. if (!state)
  668. return -ENOMEM;
  669. mutex_init(&state->lock);
  670. spin_lock_init(&state->slock);
  671. state->pdev = pdev;
  672. of_id = of_match_node(s5pcsis_of_match, dev->of_node);
  673. if (WARN_ON(of_id == NULL))
  674. return -EINVAL;
  675. drv_data = of_id->data;
  676. state->interrupt_mask = drv_data->interrupt_mask;
  677. ret = s5pcsis_parse_dt(pdev, state);
  678. if (ret < 0)
  679. return ret;
  680. if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) {
  681. dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n",
  682. state->num_lanes, state->max_num_lanes);
  683. return -EINVAL;
  684. }
  685. state->phy = devm_phy_get(dev, "csis");
  686. if (IS_ERR(state->phy))
  687. return PTR_ERR(state->phy);
  688. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  689. state->regs = devm_ioremap_resource(dev, mem_res);
  690. if (IS_ERR(state->regs))
  691. return PTR_ERR(state->regs);
  692. state->irq = platform_get_irq(pdev, 0);
  693. if (state->irq < 0) {
  694. dev_err(dev, "Failed to get irq\n");
  695. return state->irq;
  696. }
  697. for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
  698. state->supplies[i].supply = csis_supply_name[i];
  699. ret = devm_regulator_bulk_get(dev, CSIS_NUM_SUPPLIES,
  700. state->supplies);
  701. if (ret)
  702. return ret;
  703. ret = s5pcsis_clk_get(state);
  704. if (ret < 0)
  705. return ret;
  706. if (state->clk_frequency)
  707. ret = clk_set_rate(state->clock[CSIS_CLK_MUX],
  708. state->clk_frequency);
  709. else
  710. dev_WARN(dev, "No clock frequency specified!\n");
  711. if (ret < 0)
  712. goto e_clkput;
  713. ret = clk_enable(state->clock[CSIS_CLK_MUX]);
  714. if (ret < 0)
  715. goto e_clkput;
  716. ret = devm_request_irq(dev, state->irq, s5pcsis_irq_handler,
  717. 0, dev_name(dev), state);
  718. if (ret) {
  719. dev_err(dev, "Interrupt request failed\n");
  720. goto e_clkdis;
  721. }
  722. v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
  723. state->sd.owner = THIS_MODULE;
  724. snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d",
  725. CSIS_SUBDEV_NAME, state->index);
  726. state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  727. state->csis_fmt = &s5pcsis_formats[0];
  728. state->format.code = s5pcsis_formats[0].code;
  729. state->format.width = S5PCSIS_DEF_PIX_WIDTH;
  730. state->format.height = S5PCSIS_DEF_PIX_HEIGHT;
  731. state->sd.entity.function = MEDIA_ENT_F_IO_V4L;
  732. state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  733. state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
  734. ret = media_entity_pads_init(&state->sd.entity,
  735. CSIS_PADS_NUM, state->pads);
  736. if (ret < 0)
  737. goto e_clkdis;
  738. /* This allows to retrieve the platform device id by the host driver */
  739. v4l2_set_subdevdata(&state->sd, pdev);
  740. /* .. and a pointer to the subdev. */
  741. platform_set_drvdata(pdev, &state->sd);
  742. memcpy(state->events, s5pcsis_events, sizeof(state->events));
  743. pm_runtime_enable(dev);
  744. if (!pm_runtime_enabled(dev)) {
  745. ret = s5pcsis_pm_resume(dev, true);
  746. if (ret < 0)
  747. goto e_m_ent;
  748. }
  749. dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
  750. state->num_lanes, state->hs_settle, state->wclk_ext,
  751. state->clk_frequency);
  752. return 0;
  753. e_m_ent:
  754. media_entity_cleanup(&state->sd.entity);
  755. e_clkdis:
  756. clk_disable(state->clock[CSIS_CLK_MUX]);
  757. e_clkput:
  758. s5pcsis_clk_put(state);
  759. return ret;
  760. }
  761. static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
  762. {
  763. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  764. struct csis_state *state = sd_to_csis_state(sd);
  765. int ret = 0;
  766. v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
  767. __func__, state->flags);
  768. mutex_lock(&state->lock);
  769. if (state->flags & ST_POWERED) {
  770. s5pcsis_stop_stream(state);
  771. ret = phy_power_off(state->phy);
  772. if (ret)
  773. goto unlock;
  774. ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
  775. state->supplies);
  776. if (ret)
  777. goto unlock;
  778. clk_disable(state->clock[CSIS_CLK_GATE]);
  779. state->flags &= ~ST_POWERED;
  780. if (!runtime)
  781. state->flags |= ST_SUSPENDED;
  782. }
  783. unlock:
  784. mutex_unlock(&state->lock);
  785. return ret ? -EAGAIN : 0;
  786. }
  787. static int s5pcsis_pm_resume(struct device *dev, bool runtime)
  788. {
  789. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  790. struct csis_state *state = sd_to_csis_state(sd);
  791. int ret = 0;
  792. v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
  793. __func__, state->flags);
  794. mutex_lock(&state->lock);
  795. if (!runtime && !(state->flags & ST_SUSPENDED))
  796. goto unlock;
  797. if (!(state->flags & ST_POWERED)) {
  798. ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
  799. state->supplies);
  800. if (ret)
  801. goto unlock;
  802. ret = phy_power_on(state->phy);
  803. if (!ret) {
  804. state->flags |= ST_POWERED;
  805. } else {
  806. regulator_bulk_disable(CSIS_NUM_SUPPLIES,
  807. state->supplies);
  808. goto unlock;
  809. }
  810. clk_enable(state->clock[CSIS_CLK_GATE]);
  811. }
  812. if (state->flags & ST_STREAMING)
  813. s5pcsis_start_stream(state);
  814. state->flags &= ~ST_SUSPENDED;
  815. unlock:
  816. mutex_unlock(&state->lock);
  817. return ret ? -EAGAIN : 0;
  818. }
  819. #ifdef CONFIG_PM_SLEEP
  820. static int s5pcsis_suspend(struct device *dev)
  821. {
  822. return s5pcsis_pm_suspend(dev, false);
  823. }
  824. static int s5pcsis_resume(struct device *dev)
  825. {
  826. return s5pcsis_pm_resume(dev, false);
  827. }
  828. #endif
  829. #ifdef CONFIG_PM
  830. static int s5pcsis_runtime_suspend(struct device *dev)
  831. {
  832. return s5pcsis_pm_suspend(dev, true);
  833. }
  834. static int s5pcsis_runtime_resume(struct device *dev)
  835. {
  836. return s5pcsis_pm_resume(dev, true);
  837. }
  838. #endif
  839. static int s5pcsis_remove(struct platform_device *pdev)
  840. {
  841. struct v4l2_subdev *sd = platform_get_drvdata(pdev);
  842. struct csis_state *state = sd_to_csis_state(sd);
  843. pm_runtime_disable(&pdev->dev);
  844. s5pcsis_pm_suspend(&pdev->dev, true);
  845. clk_disable(state->clock[CSIS_CLK_MUX]);
  846. pm_runtime_set_suspended(&pdev->dev);
  847. s5pcsis_clk_put(state);
  848. media_entity_cleanup(&state->sd.entity);
  849. return 0;
  850. }
  851. static const struct dev_pm_ops s5pcsis_pm_ops = {
  852. SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
  853. NULL)
  854. SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
  855. };
  856. static const struct csis_drvdata exynos4_csis_drvdata = {
  857. .interrupt_mask = S5PCSIS_INTMSK_EXYNOS4_EN_ALL,
  858. };
  859. static const struct csis_drvdata exynos5_csis_drvdata = {
  860. .interrupt_mask = S5PCSIS_INTMSK_EXYNOS5_EN_ALL,
  861. };
  862. static const struct of_device_id s5pcsis_of_match[] = {
  863. {
  864. .compatible = "samsung,s5pv210-csis",
  865. .data = &exynos4_csis_drvdata,
  866. }, {
  867. .compatible = "samsung,exynos4210-csis",
  868. .data = &exynos4_csis_drvdata,
  869. }, {
  870. .compatible = "samsung,exynos5250-csis",
  871. .data = &exynos5_csis_drvdata,
  872. },
  873. { /* sentinel */ },
  874. };
  875. MODULE_DEVICE_TABLE(of, s5pcsis_of_match);
  876. static struct platform_driver s5pcsis_driver = {
  877. .probe = s5pcsis_probe,
  878. .remove = s5pcsis_remove,
  879. .driver = {
  880. .of_match_table = s5pcsis_of_match,
  881. .name = CSIS_DRIVER_NAME,
  882. .pm = &s5pcsis_pm_ops,
  883. },
  884. };
  885. module_platform_driver(s5pcsis_driver);
  886. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  887. MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver");
  888. MODULE_LICENSE("GPL");