isp.c 62 KB

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  1. /*
  2. * isp.c
  3. *
  4. * TI OMAP3 ISP - Core
  5. *
  6. * Copyright (C) 2006-2010 Nokia Corporation
  7. * Copyright (C) 2007-2009 Texas Instruments, Inc.
  8. *
  9. * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10. * Sakari Ailus <sakari.ailus@iki.fi>
  11. *
  12. * Contributors:
  13. * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  14. * Sakari Ailus <sakari.ailus@iki.fi>
  15. * David Cohen <dacohen@gmail.com>
  16. * Stanimir Varbanov <svarbanov@mm-sol.com>
  17. * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
  18. * Tuukka Toivonen <tuukkat76@gmail.com>
  19. * Sergio Aguirre <saaguirre@ti.com>
  20. * Antti Koskipaa <akoskipa@gmail.com>
  21. * Ivan T. Ivanov <iivanov@mm-sol.com>
  22. * RaniSuneela <r-m@ti.com>
  23. * Atanas Filipov <afilipov@mm-sol.com>
  24. * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
  25. * Hiroshi DOYU <hiroshi.doyu@nokia.com>
  26. * Nayden Kanchev <nkanchev@mm-sol.com>
  27. * Phil Carmody <ext-phil.2.carmody@nokia.com>
  28. * Artem Bityutskiy <artem.bityutskiy@nokia.com>
  29. * Dominic Curran <dcurran@ti.com>
  30. * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
  31. * Pallavi Kulkarni <p-kulkarni@ti.com>
  32. * Vaibhav Hiremath <hvaibhav@ti.com>
  33. * Mohit Jalori <mjalori@ti.com>
  34. * Sameer Venkatraman <sameerv@ti.com>
  35. * Senthilvadivu Guruswamy <svadivu@ti.com>
  36. * Thara Gopinath <thara@ti.com>
  37. * Toni Leinonen <toni.leinonen@nokia.com>
  38. * Troy Laramy <t-laramy@ti.com>
  39. *
  40. * This program is free software; you can redistribute it and/or modify
  41. * it under the terms of the GNU General Public License version 2 as
  42. * published by the Free Software Foundation.
  43. */
  44. #include <asm/cacheflush.h>
  45. #include <linux/clk.h>
  46. #include <linux/clkdev.h>
  47. #include <linux/delay.h>
  48. #include <linux/device.h>
  49. #include <linux/dma-mapping.h>
  50. #include <linux/i2c.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/mfd/syscon.h>
  53. #include <linux/module.h>
  54. #include <linux/omap-iommu.h>
  55. #include <linux/platform_device.h>
  56. #include <linux/property.h>
  57. #include <linux/regulator/consumer.h>
  58. #include <linux/slab.h>
  59. #include <linux/sched.h>
  60. #include <linux/vmalloc.h>
  61. #ifdef CONFIG_ARM_DMA_USE_IOMMU
  62. #include <asm/dma-iommu.h>
  63. #endif
  64. #include <media/v4l2-common.h>
  65. #include <media/v4l2-fwnode.h>
  66. #include <media/v4l2-device.h>
  67. #include <media/v4l2-mc.h>
  68. #include "isp.h"
  69. #include "ispreg.h"
  70. #include "ispccdc.h"
  71. #include "isppreview.h"
  72. #include "ispresizer.h"
  73. #include "ispcsi2.h"
  74. #include "ispccp2.h"
  75. #include "isph3a.h"
  76. #include "isphist.h"
  77. static unsigned int autoidle;
  78. module_param(autoidle, int, 0444);
  79. MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
  80. static void isp_save_ctx(struct isp_device *isp);
  81. static void isp_restore_ctx(struct isp_device *isp);
  82. static const struct isp_res_mapping isp_res_maps[] = {
  83. {
  84. .isp_rev = ISP_REVISION_2_0,
  85. .offset = {
  86. /* first MMIO area */
  87. 0x0000, /* base, len 0x0070 */
  88. 0x0400, /* ccp2, len 0x01f0 */
  89. 0x0600, /* ccdc, len 0x00a8 */
  90. 0x0a00, /* hist, len 0x0048 */
  91. 0x0c00, /* h3a, len 0x0060 */
  92. 0x0e00, /* preview, len 0x00a0 */
  93. 0x1000, /* resizer, len 0x00ac */
  94. 0x1200, /* sbl, len 0x00fc */
  95. /* second MMIO area */
  96. 0x0000, /* csi2a, len 0x0170 */
  97. 0x0170, /* csiphy2, len 0x000c */
  98. },
  99. .phy_type = ISP_PHY_TYPE_3430,
  100. },
  101. {
  102. .isp_rev = ISP_REVISION_15_0,
  103. .offset = {
  104. /* first MMIO area */
  105. 0x0000, /* base, len 0x0070 */
  106. 0x0400, /* ccp2, len 0x01f0 */
  107. 0x0600, /* ccdc, len 0x00a8 */
  108. 0x0a00, /* hist, len 0x0048 */
  109. 0x0c00, /* h3a, len 0x0060 */
  110. 0x0e00, /* preview, len 0x00a0 */
  111. 0x1000, /* resizer, len 0x00ac */
  112. 0x1200, /* sbl, len 0x00fc */
  113. /* second MMIO area */
  114. 0x0000, /* csi2a, len 0x0170 (1st area) */
  115. 0x0170, /* csiphy2, len 0x000c */
  116. 0x01c0, /* csi2a, len 0x0040 (2nd area) */
  117. 0x0400, /* csi2c, len 0x0170 (1st area) */
  118. 0x0570, /* csiphy1, len 0x000c */
  119. 0x05c0, /* csi2c, len 0x0040 (2nd area) */
  120. },
  121. .phy_type = ISP_PHY_TYPE_3630,
  122. },
  123. };
  124. /* Structure for saving/restoring ISP module registers */
  125. static struct isp_reg isp_reg_list[] = {
  126. {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
  127. {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
  128. {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
  129. {0, ISP_TOK_TERM, 0}
  130. };
  131. /*
  132. * omap3isp_flush - Post pending L3 bus writes by doing a register readback
  133. * @isp: OMAP3 ISP device
  134. *
  135. * In order to force posting of pending writes, we need to write and
  136. * readback the same register, in this case the revision register.
  137. *
  138. * See this link for reference:
  139. * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
  140. */
  141. void omap3isp_flush(struct isp_device *isp)
  142. {
  143. isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
  144. isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
  145. }
  146. /* -----------------------------------------------------------------------------
  147. * XCLK
  148. */
  149. #define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
  150. static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
  151. {
  152. switch (xclk->id) {
  153. case ISP_XCLK_A:
  154. isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
  155. ISPTCTRL_CTRL_DIVA_MASK,
  156. divider << ISPTCTRL_CTRL_DIVA_SHIFT);
  157. break;
  158. case ISP_XCLK_B:
  159. isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
  160. ISPTCTRL_CTRL_DIVB_MASK,
  161. divider << ISPTCTRL_CTRL_DIVB_SHIFT);
  162. break;
  163. }
  164. }
  165. static int isp_xclk_prepare(struct clk_hw *hw)
  166. {
  167. struct isp_xclk *xclk = to_isp_xclk(hw);
  168. omap3isp_get(xclk->isp);
  169. return 0;
  170. }
  171. static void isp_xclk_unprepare(struct clk_hw *hw)
  172. {
  173. struct isp_xclk *xclk = to_isp_xclk(hw);
  174. omap3isp_put(xclk->isp);
  175. }
  176. static int isp_xclk_enable(struct clk_hw *hw)
  177. {
  178. struct isp_xclk *xclk = to_isp_xclk(hw);
  179. unsigned long flags;
  180. spin_lock_irqsave(&xclk->lock, flags);
  181. isp_xclk_update(xclk, xclk->divider);
  182. xclk->enabled = true;
  183. spin_unlock_irqrestore(&xclk->lock, flags);
  184. return 0;
  185. }
  186. static void isp_xclk_disable(struct clk_hw *hw)
  187. {
  188. struct isp_xclk *xclk = to_isp_xclk(hw);
  189. unsigned long flags;
  190. spin_lock_irqsave(&xclk->lock, flags);
  191. isp_xclk_update(xclk, 0);
  192. xclk->enabled = false;
  193. spin_unlock_irqrestore(&xclk->lock, flags);
  194. }
  195. static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
  196. unsigned long parent_rate)
  197. {
  198. struct isp_xclk *xclk = to_isp_xclk(hw);
  199. return parent_rate / xclk->divider;
  200. }
  201. static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
  202. {
  203. u32 divider;
  204. if (*rate >= parent_rate) {
  205. *rate = parent_rate;
  206. return ISPTCTRL_CTRL_DIV_BYPASS;
  207. }
  208. if (*rate == 0)
  209. *rate = 1;
  210. divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
  211. if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
  212. divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
  213. *rate = parent_rate / divider;
  214. return divider;
  215. }
  216. static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
  217. unsigned long *parent_rate)
  218. {
  219. isp_xclk_calc_divider(&rate, *parent_rate);
  220. return rate;
  221. }
  222. static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
  223. unsigned long parent_rate)
  224. {
  225. struct isp_xclk *xclk = to_isp_xclk(hw);
  226. unsigned long flags;
  227. u32 divider;
  228. divider = isp_xclk_calc_divider(&rate, parent_rate);
  229. spin_lock_irqsave(&xclk->lock, flags);
  230. xclk->divider = divider;
  231. if (xclk->enabled)
  232. isp_xclk_update(xclk, divider);
  233. spin_unlock_irqrestore(&xclk->lock, flags);
  234. dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
  235. __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
  236. return 0;
  237. }
  238. static const struct clk_ops isp_xclk_ops = {
  239. .prepare = isp_xclk_prepare,
  240. .unprepare = isp_xclk_unprepare,
  241. .enable = isp_xclk_enable,
  242. .disable = isp_xclk_disable,
  243. .recalc_rate = isp_xclk_recalc_rate,
  244. .round_rate = isp_xclk_round_rate,
  245. .set_rate = isp_xclk_set_rate,
  246. };
  247. static const char *isp_xclk_parent_name = "cam_mclk";
  248. static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
  249. {
  250. unsigned int idx = clkspec->args[0];
  251. struct isp_device *isp = data;
  252. if (idx >= ARRAY_SIZE(isp->xclks))
  253. return ERR_PTR(-ENOENT);
  254. return isp->xclks[idx].clk;
  255. }
  256. static int isp_xclk_init(struct isp_device *isp)
  257. {
  258. struct device_node *np = isp->dev->of_node;
  259. struct clk_init_data init = {};
  260. unsigned int i;
  261. for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
  262. isp->xclks[i].clk = ERR_PTR(-EINVAL);
  263. for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
  264. struct isp_xclk *xclk = &isp->xclks[i];
  265. xclk->isp = isp;
  266. xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
  267. xclk->divider = 1;
  268. spin_lock_init(&xclk->lock);
  269. init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
  270. init.ops = &isp_xclk_ops;
  271. init.parent_names = &isp_xclk_parent_name;
  272. init.num_parents = 1;
  273. xclk->hw.init = &init;
  274. /*
  275. * The first argument is NULL in order to avoid circular
  276. * reference, as this driver takes reference on the
  277. * sensor subdevice modules and the sensors would take
  278. * reference on this module through clk_get().
  279. */
  280. xclk->clk = clk_register(NULL, &xclk->hw);
  281. if (IS_ERR(xclk->clk))
  282. return PTR_ERR(xclk->clk);
  283. }
  284. if (np)
  285. of_clk_add_provider(np, isp_xclk_src_get, isp);
  286. return 0;
  287. }
  288. static void isp_xclk_cleanup(struct isp_device *isp)
  289. {
  290. struct device_node *np = isp->dev->of_node;
  291. unsigned int i;
  292. if (np)
  293. of_clk_del_provider(np);
  294. for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
  295. struct isp_xclk *xclk = &isp->xclks[i];
  296. if (!IS_ERR(xclk->clk))
  297. clk_unregister(xclk->clk);
  298. }
  299. }
  300. /* -----------------------------------------------------------------------------
  301. * Interrupts
  302. */
  303. /*
  304. * isp_enable_interrupts - Enable ISP interrupts.
  305. * @isp: OMAP3 ISP device
  306. */
  307. static void isp_enable_interrupts(struct isp_device *isp)
  308. {
  309. static const u32 irq = IRQ0ENABLE_CSIA_IRQ
  310. | IRQ0ENABLE_CSIB_IRQ
  311. | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
  312. | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
  313. | IRQ0ENABLE_CCDC_VD0_IRQ
  314. | IRQ0ENABLE_CCDC_VD1_IRQ
  315. | IRQ0ENABLE_HS_VS_IRQ
  316. | IRQ0ENABLE_HIST_DONE_IRQ
  317. | IRQ0ENABLE_H3A_AWB_DONE_IRQ
  318. | IRQ0ENABLE_H3A_AF_DONE_IRQ
  319. | IRQ0ENABLE_PRV_DONE_IRQ
  320. | IRQ0ENABLE_RSZ_DONE_IRQ;
  321. isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
  322. isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
  323. }
  324. /*
  325. * isp_disable_interrupts - Disable ISP interrupts.
  326. * @isp: OMAP3 ISP device
  327. */
  328. static void isp_disable_interrupts(struct isp_device *isp)
  329. {
  330. isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
  331. }
  332. /*
  333. * isp_core_init - ISP core settings
  334. * @isp: OMAP3 ISP device
  335. * @idle: Consider idle state.
  336. *
  337. * Set the power settings for the ISP and SBL bus and configure the HS/VS
  338. * interrupt source.
  339. *
  340. * We need to configure the HS/VS interrupt source before interrupts get
  341. * enabled, as the sensor might be free-running and the ISP default setting
  342. * (HS edge) would put an unnecessary burden on the CPU.
  343. */
  344. static void isp_core_init(struct isp_device *isp, int idle)
  345. {
  346. isp_reg_writel(isp,
  347. ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
  348. ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
  349. ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
  350. ((isp->revision == ISP_REVISION_15_0) ?
  351. ISP_SYSCONFIG_AUTOIDLE : 0),
  352. OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
  353. isp_reg_writel(isp,
  354. (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
  355. ISPCTRL_SYNC_DETECT_VSRISE,
  356. OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
  357. }
  358. /*
  359. * Configure the bridge and lane shifter. Valid inputs are
  360. *
  361. * CCDC_INPUT_PARALLEL: Parallel interface
  362. * CCDC_INPUT_CSI2A: CSI2a receiver
  363. * CCDC_INPUT_CCP2B: CCP2b receiver
  364. * CCDC_INPUT_CSI2C: CSI2c receiver
  365. *
  366. * The bridge and lane shifter are configured according to the selected input
  367. * and the ISP platform data.
  368. */
  369. void omap3isp_configure_bridge(struct isp_device *isp,
  370. enum ccdc_input_entity input,
  371. const struct isp_parallel_cfg *parcfg,
  372. unsigned int shift, unsigned int bridge)
  373. {
  374. u32 ispctrl_val;
  375. ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
  376. ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
  377. ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
  378. ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
  379. ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
  380. ispctrl_val |= bridge;
  381. switch (input) {
  382. case CCDC_INPUT_PARALLEL:
  383. ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
  384. ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
  385. shift += parcfg->data_lane_shift;
  386. break;
  387. case CCDC_INPUT_CSI2A:
  388. ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
  389. break;
  390. case CCDC_INPUT_CCP2B:
  391. ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
  392. break;
  393. case CCDC_INPUT_CSI2C:
  394. ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
  395. break;
  396. default:
  397. return;
  398. }
  399. ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
  400. isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
  401. }
  402. void omap3isp_hist_dma_done(struct isp_device *isp)
  403. {
  404. if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
  405. omap3isp_stat_pcr_busy(&isp->isp_hist)) {
  406. /* Histogram cannot be enabled in this frame anymore */
  407. atomic_set(&isp->isp_hist.buf_err, 1);
  408. dev_dbg(isp->dev,
  409. "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
  410. }
  411. }
  412. static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
  413. {
  414. static const char *name[] = {
  415. "CSIA_IRQ",
  416. "res1",
  417. "res2",
  418. "CSIB_LCM_IRQ",
  419. "CSIB_IRQ",
  420. "res5",
  421. "res6",
  422. "res7",
  423. "CCDC_VD0_IRQ",
  424. "CCDC_VD1_IRQ",
  425. "CCDC_VD2_IRQ",
  426. "CCDC_ERR_IRQ",
  427. "H3A_AF_DONE_IRQ",
  428. "H3A_AWB_DONE_IRQ",
  429. "res14",
  430. "res15",
  431. "HIST_DONE_IRQ",
  432. "CCDC_LSC_DONE",
  433. "CCDC_LSC_PREFETCH_COMPLETED",
  434. "CCDC_LSC_PREFETCH_ERROR",
  435. "PRV_DONE_IRQ",
  436. "CBUFF_IRQ",
  437. "res22",
  438. "res23",
  439. "RSZ_DONE_IRQ",
  440. "OVF_IRQ",
  441. "res26",
  442. "res27",
  443. "MMU_ERR_IRQ",
  444. "OCP_ERR_IRQ",
  445. "SEC_ERR_IRQ",
  446. "HS_VS_IRQ",
  447. };
  448. int i;
  449. dev_dbg(isp->dev, "ISP IRQ: ");
  450. for (i = 0; i < ARRAY_SIZE(name); i++) {
  451. if ((1 << i) & irqstatus)
  452. printk(KERN_CONT "%s ", name[i]);
  453. }
  454. printk(KERN_CONT "\n");
  455. }
  456. static void isp_isr_sbl(struct isp_device *isp)
  457. {
  458. struct device *dev = isp->dev;
  459. struct isp_pipeline *pipe;
  460. u32 sbl_pcr;
  461. /*
  462. * Handle shared buffer logic overflows for video buffers.
  463. * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
  464. */
  465. sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
  466. isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
  467. sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
  468. if (sbl_pcr)
  469. dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
  470. if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
  471. pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
  472. if (pipe != NULL)
  473. pipe->error = true;
  474. }
  475. if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
  476. pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
  477. if (pipe != NULL)
  478. pipe->error = true;
  479. }
  480. if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
  481. pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
  482. if (pipe != NULL)
  483. pipe->error = true;
  484. }
  485. if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
  486. pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
  487. if (pipe != NULL)
  488. pipe->error = true;
  489. }
  490. if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
  491. | ISPSBL_PCR_RSZ2_WBL_OVF
  492. | ISPSBL_PCR_RSZ3_WBL_OVF
  493. | ISPSBL_PCR_RSZ4_WBL_OVF)) {
  494. pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
  495. if (pipe != NULL)
  496. pipe->error = true;
  497. }
  498. if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
  499. omap3isp_stat_sbl_overflow(&isp->isp_af);
  500. if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
  501. omap3isp_stat_sbl_overflow(&isp->isp_aewb);
  502. }
  503. /*
  504. * isp_isr - Interrupt Service Routine for Camera ISP module.
  505. * @irq: Not used currently.
  506. * @_isp: Pointer to the OMAP3 ISP device
  507. *
  508. * Handles the corresponding callback if plugged in.
  509. */
  510. static irqreturn_t isp_isr(int irq, void *_isp)
  511. {
  512. static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
  513. IRQ0STATUS_CCDC_LSC_DONE_IRQ |
  514. IRQ0STATUS_CCDC_VD0_IRQ |
  515. IRQ0STATUS_CCDC_VD1_IRQ |
  516. IRQ0STATUS_HS_VS_IRQ;
  517. struct isp_device *isp = _isp;
  518. u32 irqstatus;
  519. irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
  520. isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
  521. isp_isr_sbl(isp);
  522. if (irqstatus & IRQ0STATUS_CSIA_IRQ)
  523. omap3isp_csi2_isr(&isp->isp_csi2a);
  524. if (irqstatus & IRQ0STATUS_CSIB_IRQ)
  525. omap3isp_ccp2_isr(&isp->isp_ccp2);
  526. if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
  527. if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
  528. omap3isp_preview_isr_frame_sync(&isp->isp_prev);
  529. if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
  530. omap3isp_resizer_isr_frame_sync(&isp->isp_res);
  531. omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
  532. omap3isp_stat_isr_frame_sync(&isp->isp_af);
  533. omap3isp_stat_isr_frame_sync(&isp->isp_hist);
  534. }
  535. if (irqstatus & ccdc_events)
  536. omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
  537. if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
  538. if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
  539. omap3isp_resizer_isr_frame_sync(&isp->isp_res);
  540. omap3isp_preview_isr(&isp->isp_prev);
  541. }
  542. if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
  543. omap3isp_resizer_isr(&isp->isp_res);
  544. if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
  545. omap3isp_stat_isr(&isp->isp_aewb);
  546. if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
  547. omap3isp_stat_isr(&isp->isp_af);
  548. if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
  549. omap3isp_stat_isr(&isp->isp_hist);
  550. omap3isp_flush(isp);
  551. #if defined(DEBUG) && defined(ISP_ISR_DEBUG)
  552. isp_isr_dbg(isp, irqstatus);
  553. #endif
  554. return IRQ_HANDLED;
  555. }
  556. static const struct media_device_ops isp_media_ops = {
  557. .link_notify = v4l2_pipeline_link_notify,
  558. };
  559. /* -----------------------------------------------------------------------------
  560. * Pipeline stream management
  561. */
  562. /*
  563. * isp_pipeline_enable - Enable streaming on a pipeline
  564. * @pipe: ISP pipeline
  565. * @mode: Stream mode (single shot or continuous)
  566. *
  567. * Walk the entities chain starting at the pipeline output video node and start
  568. * all modules in the chain in the given mode.
  569. *
  570. * Return 0 if successful, or the return value of the failed video::s_stream
  571. * operation otherwise.
  572. */
  573. static int isp_pipeline_enable(struct isp_pipeline *pipe,
  574. enum isp_pipeline_stream_state mode)
  575. {
  576. struct isp_device *isp = pipe->output->isp;
  577. struct media_entity *entity;
  578. struct media_pad *pad;
  579. struct v4l2_subdev *subdev;
  580. unsigned long flags;
  581. int ret;
  582. /* Refuse to start streaming if an entity included in the pipeline has
  583. * crashed. This check must be performed before the loop below to avoid
  584. * starting entities if the pipeline won't start anyway (those entities
  585. * would then likely fail to stop, making the problem worse).
  586. */
  587. if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
  588. return -EIO;
  589. spin_lock_irqsave(&pipe->lock, flags);
  590. pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
  591. spin_unlock_irqrestore(&pipe->lock, flags);
  592. pipe->do_propagation = false;
  593. entity = &pipe->output->video.entity;
  594. while (1) {
  595. pad = &entity->pads[0];
  596. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  597. break;
  598. pad = media_entity_remote_pad(pad);
  599. if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
  600. break;
  601. entity = pad->entity;
  602. subdev = media_entity_to_v4l2_subdev(entity);
  603. ret = v4l2_subdev_call(subdev, video, s_stream, mode);
  604. if (ret < 0 && ret != -ENOIOCTLCMD)
  605. return ret;
  606. if (subdev == &isp->isp_ccdc.subdev) {
  607. v4l2_subdev_call(&isp->isp_aewb.subdev, video,
  608. s_stream, mode);
  609. v4l2_subdev_call(&isp->isp_af.subdev, video,
  610. s_stream, mode);
  611. v4l2_subdev_call(&isp->isp_hist.subdev, video,
  612. s_stream, mode);
  613. pipe->do_propagation = true;
  614. }
  615. /* Stop at the first external sub-device. */
  616. if (subdev->dev != isp->dev)
  617. break;
  618. }
  619. return 0;
  620. }
  621. static int isp_pipeline_wait_resizer(struct isp_device *isp)
  622. {
  623. return omap3isp_resizer_busy(&isp->isp_res);
  624. }
  625. static int isp_pipeline_wait_preview(struct isp_device *isp)
  626. {
  627. return omap3isp_preview_busy(&isp->isp_prev);
  628. }
  629. static int isp_pipeline_wait_ccdc(struct isp_device *isp)
  630. {
  631. return omap3isp_stat_busy(&isp->isp_af)
  632. || omap3isp_stat_busy(&isp->isp_aewb)
  633. || omap3isp_stat_busy(&isp->isp_hist)
  634. || omap3isp_ccdc_busy(&isp->isp_ccdc);
  635. }
  636. #define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
  637. static int isp_pipeline_wait(struct isp_device *isp,
  638. int(*busy)(struct isp_device *isp))
  639. {
  640. unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
  641. while (!time_after(jiffies, timeout)) {
  642. if (!busy(isp))
  643. return 0;
  644. }
  645. return 1;
  646. }
  647. /*
  648. * isp_pipeline_disable - Disable streaming on a pipeline
  649. * @pipe: ISP pipeline
  650. *
  651. * Walk the entities chain starting at the pipeline output video node and stop
  652. * all modules in the chain. Wait synchronously for the modules to be stopped if
  653. * necessary.
  654. *
  655. * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
  656. * can't be stopped (in which case a software reset of the ISP is probably
  657. * necessary).
  658. */
  659. static int isp_pipeline_disable(struct isp_pipeline *pipe)
  660. {
  661. struct isp_device *isp = pipe->output->isp;
  662. struct media_entity *entity;
  663. struct media_pad *pad;
  664. struct v4l2_subdev *subdev;
  665. int failure = 0;
  666. int ret;
  667. /*
  668. * We need to stop all the modules after CCDC first or they'll
  669. * never stop since they may not get a full frame from CCDC.
  670. */
  671. entity = &pipe->output->video.entity;
  672. while (1) {
  673. pad = &entity->pads[0];
  674. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  675. break;
  676. pad = media_entity_remote_pad(pad);
  677. if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
  678. break;
  679. entity = pad->entity;
  680. subdev = media_entity_to_v4l2_subdev(entity);
  681. if (subdev == &isp->isp_ccdc.subdev) {
  682. v4l2_subdev_call(&isp->isp_aewb.subdev,
  683. video, s_stream, 0);
  684. v4l2_subdev_call(&isp->isp_af.subdev,
  685. video, s_stream, 0);
  686. v4l2_subdev_call(&isp->isp_hist.subdev,
  687. video, s_stream, 0);
  688. }
  689. ret = v4l2_subdev_call(subdev, video, s_stream, 0);
  690. if (subdev == &isp->isp_res.subdev)
  691. ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
  692. else if (subdev == &isp->isp_prev.subdev)
  693. ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
  694. else if (subdev == &isp->isp_ccdc.subdev)
  695. ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
  696. /* Handle stop failures. An entity that fails to stop can
  697. * usually just be restarted. Flag the stop failure nonetheless
  698. * to trigger an ISP reset the next time the device is released,
  699. * just in case.
  700. *
  701. * The preview engine is a special case. A failure to stop can
  702. * mean a hardware crash. When that happens the preview engine
  703. * won't respond to read/write operations on the L4 bus anymore,
  704. * resulting in a bus fault and a kernel oops next time it gets
  705. * accessed. Mark it as crashed to prevent pipelines including
  706. * it from being started.
  707. */
  708. if (ret) {
  709. dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
  710. isp->stop_failure = true;
  711. if (subdev == &isp->isp_prev.subdev)
  712. media_entity_enum_set(&isp->crashed,
  713. &subdev->entity);
  714. failure = -ETIMEDOUT;
  715. }
  716. /* Stop at the first external sub-device. */
  717. if (subdev->dev != isp->dev)
  718. break;
  719. }
  720. return failure;
  721. }
  722. /*
  723. * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
  724. * @pipe: ISP pipeline
  725. * @state: Stream state (stopped, single shot or continuous)
  726. *
  727. * Set the pipeline to the given stream state. Pipelines can be started in
  728. * single-shot or continuous mode.
  729. *
  730. * Return 0 if successful, or the return value of the failed video::s_stream
  731. * operation otherwise. The pipeline state is not updated when the operation
  732. * fails, except when stopping the pipeline.
  733. */
  734. int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
  735. enum isp_pipeline_stream_state state)
  736. {
  737. int ret;
  738. if (state == ISP_PIPELINE_STREAM_STOPPED)
  739. ret = isp_pipeline_disable(pipe);
  740. else
  741. ret = isp_pipeline_enable(pipe, state);
  742. if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
  743. pipe->stream_state = state;
  744. return ret;
  745. }
  746. /*
  747. * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
  748. * @pipe: ISP pipeline
  749. *
  750. * Cancelling a stream mark all buffers on all video nodes in the pipeline as
  751. * erroneous and makes sure no new buffer can be queued. This function is called
  752. * when a fatal error that prevents any further operation on the pipeline
  753. * occurs.
  754. */
  755. void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
  756. {
  757. if (pipe->input)
  758. omap3isp_video_cancel_stream(pipe->input);
  759. if (pipe->output)
  760. omap3isp_video_cancel_stream(pipe->output);
  761. }
  762. /*
  763. * isp_pipeline_resume - Resume streaming on a pipeline
  764. * @pipe: ISP pipeline
  765. *
  766. * Resume video output and input and re-enable pipeline.
  767. */
  768. static void isp_pipeline_resume(struct isp_pipeline *pipe)
  769. {
  770. int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
  771. omap3isp_video_resume(pipe->output, !singleshot);
  772. if (singleshot)
  773. omap3isp_video_resume(pipe->input, 0);
  774. isp_pipeline_enable(pipe, pipe->stream_state);
  775. }
  776. /*
  777. * isp_pipeline_suspend - Suspend streaming on a pipeline
  778. * @pipe: ISP pipeline
  779. *
  780. * Suspend pipeline.
  781. */
  782. static void isp_pipeline_suspend(struct isp_pipeline *pipe)
  783. {
  784. isp_pipeline_disable(pipe);
  785. }
  786. /*
  787. * isp_pipeline_is_last - Verify if entity has an enabled link to the output
  788. * video node
  789. * @me: ISP module's media entity
  790. *
  791. * Returns 1 if the entity has an enabled link to the output video node or 0
  792. * otherwise. It's true only while pipeline can have no more than one output
  793. * node.
  794. */
  795. static int isp_pipeline_is_last(struct media_entity *me)
  796. {
  797. struct isp_pipeline *pipe;
  798. struct media_pad *pad;
  799. if (!me->pipe)
  800. return 0;
  801. pipe = to_isp_pipeline(me);
  802. if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
  803. return 0;
  804. pad = media_entity_remote_pad(&pipe->output->pad);
  805. return pad->entity == me;
  806. }
  807. /*
  808. * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
  809. * @me: ISP module's media entity
  810. *
  811. * Suspend the whole pipeline if module's entity has an enabled link to the
  812. * output video node. It works only while pipeline can have no more than one
  813. * output node.
  814. */
  815. static void isp_suspend_module_pipeline(struct media_entity *me)
  816. {
  817. if (isp_pipeline_is_last(me))
  818. isp_pipeline_suspend(to_isp_pipeline(me));
  819. }
  820. /*
  821. * isp_resume_module_pipeline - Resume pipeline to which belongs the module
  822. * @me: ISP module's media entity
  823. *
  824. * Resume the whole pipeline if module's entity has an enabled link to the
  825. * output video node. It works only while pipeline can have no more than one
  826. * output node.
  827. */
  828. static void isp_resume_module_pipeline(struct media_entity *me)
  829. {
  830. if (isp_pipeline_is_last(me))
  831. isp_pipeline_resume(to_isp_pipeline(me));
  832. }
  833. /*
  834. * isp_suspend_modules - Suspend ISP submodules.
  835. * @isp: OMAP3 ISP device
  836. *
  837. * Returns 0 if suspend left in idle state all the submodules properly,
  838. * or returns 1 if a general Reset is required to suspend the submodules.
  839. */
  840. static int __maybe_unused isp_suspend_modules(struct isp_device *isp)
  841. {
  842. unsigned long timeout;
  843. omap3isp_stat_suspend(&isp->isp_aewb);
  844. omap3isp_stat_suspend(&isp->isp_af);
  845. omap3isp_stat_suspend(&isp->isp_hist);
  846. isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
  847. isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
  848. isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
  849. isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
  850. isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
  851. timeout = jiffies + ISP_STOP_TIMEOUT;
  852. while (omap3isp_stat_busy(&isp->isp_af)
  853. || omap3isp_stat_busy(&isp->isp_aewb)
  854. || omap3isp_stat_busy(&isp->isp_hist)
  855. || omap3isp_preview_busy(&isp->isp_prev)
  856. || omap3isp_resizer_busy(&isp->isp_res)
  857. || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
  858. if (time_after(jiffies, timeout)) {
  859. dev_info(isp->dev, "can't stop modules.\n");
  860. return 1;
  861. }
  862. msleep(1);
  863. }
  864. return 0;
  865. }
  866. /*
  867. * isp_resume_modules - Resume ISP submodules.
  868. * @isp: OMAP3 ISP device
  869. */
  870. static void __maybe_unused isp_resume_modules(struct isp_device *isp)
  871. {
  872. omap3isp_stat_resume(&isp->isp_aewb);
  873. omap3isp_stat_resume(&isp->isp_af);
  874. omap3isp_stat_resume(&isp->isp_hist);
  875. isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
  876. isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
  877. isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
  878. isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
  879. isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
  880. }
  881. /*
  882. * isp_reset - Reset ISP with a timeout wait for idle.
  883. * @isp: OMAP3 ISP device
  884. */
  885. static int isp_reset(struct isp_device *isp)
  886. {
  887. unsigned long timeout = 0;
  888. isp_reg_writel(isp,
  889. isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
  890. | ISP_SYSCONFIG_SOFTRESET,
  891. OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
  892. while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
  893. ISP_SYSSTATUS) & 0x1)) {
  894. if (timeout++ > 10000) {
  895. dev_alert(isp->dev, "cannot reset ISP\n");
  896. return -ETIMEDOUT;
  897. }
  898. udelay(1);
  899. }
  900. isp->stop_failure = false;
  901. media_entity_enum_zero(&isp->crashed);
  902. return 0;
  903. }
  904. /*
  905. * isp_save_context - Saves the values of the ISP module registers.
  906. * @isp: OMAP3 ISP device
  907. * @reg_list: Structure containing pairs of register address and value to
  908. * modify on OMAP.
  909. */
  910. static void
  911. isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
  912. {
  913. struct isp_reg *next = reg_list;
  914. for (; next->reg != ISP_TOK_TERM; next++)
  915. next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
  916. }
  917. /*
  918. * isp_restore_context - Restores the values of the ISP module registers.
  919. * @isp: OMAP3 ISP device
  920. * @reg_list: Structure containing pairs of register address and value to
  921. * modify on OMAP.
  922. */
  923. static void
  924. isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
  925. {
  926. struct isp_reg *next = reg_list;
  927. for (; next->reg != ISP_TOK_TERM; next++)
  928. isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
  929. }
  930. /*
  931. * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
  932. * @isp: OMAP3 ISP device
  933. *
  934. * Routine for saving the context of each module in the ISP.
  935. * CCDC, HIST, H3A, PREV, RESZ and MMU.
  936. */
  937. static void isp_save_ctx(struct isp_device *isp)
  938. {
  939. isp_save_context(isp, isp_reg_list);
  940. omap_iommu_save_ctx(isp->dev);
  941. }
  942. /*
  943. * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
  944. * @isp: OMAP3 ISP device
  945. *
  946. * Routine for restoring the context of each module in the ISP.
  947. * CCDC, HIST, H3A, PREV, RESZ and MMU.
  948. */
  949. static void isp_restore_ctx(struct isp_device *isp)
  950. {
  951. isp_restore_context(isp, isp_reg_list);
  952. omap_iommu_restore_ctx(isp->dev);
  953. omap3isp_ccdc_restore_context(isp);
  954. omap3isp_preview_restore_context(isp);
  955. }
  956. /* -----------------------------------------------------------------------------
  957. * SBL resources management
  958. */
  959. #define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
  960. OMAP3_ISP_SBL_CCDC_LSC_READ | \
  961. OMAP3_ISP_SBL_PREVIEW_READ | \
  962. OMAP3_ISP_SBL_RESIZER_READ)
  963. #define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
  964. OMAP3_ISP_SBL_CSI2A_WRITE | \
  965. OMAP3_ISP_SBL_CSI2C_WRITE | \
  966. OMAP3_ISP_SBL_CCDC_WRITE | \
  967. OMAP3_ISP_SBL_PREVIEW_WRITE)
  968. void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
  969. {
  970. u32 sbl = 0;
  971. isp->sbl_resources |= res;
  972. if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
  973. sbl |= ISPCTRL_SBL_SHARED_RPORTA;
  974. if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
  975. sbl |= ISPCTRL_SBL_SHARED_RPORTB;
  976. if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
  977. sbl |= ISPCTRL_SBL_SHARED_WPORTC;
  978. if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
  979. sbl |= ISPCTRL_SBL_WR0_RAM_EN;
  980. if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
  981. sbl |= ISPCTRL_SBL_WR1_RAM_EN;
  982. if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
  983. sbl |= ISPCTRL_SBL_RD_RAM_EN;
  984. isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
  985. }
  986. void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
  987. {
  988. u32 sbl = 0;
  989. isp->sbl_resources &= ~res;
  990. if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
  991. sbl |= ISPCTRL_SBL_SHARED_RPORTA;
  992. if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
  993. sbl |= ISPCTRL_SBL_SHARED_RPORTB;
  994. if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
  995. sbl |= ISPCTRL_SBL_SHARED_WPORTC;
  996. if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
  997. sbl |= ISPCTRL_SBL_WR0_RAM_EN;
  998. if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
  999. sbl |= ISPCTRL_SBL_WR1_RAM_EN;
  1000. if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
  1001. sbl |= ISPCTRL_SBL_RD_RAM_EN;
  1002. isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
  1003. }
  1004. /*
  1005. * isp_module_sync_idle - Helper to sync module with its idle state
  1006. * @me: ISP submodule's media entity
  1007. * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
  1008. * @stopping: flag which tells module wants to stop
  1009. *
  1010. * This function checks if ISP submodule needs to wait for next interrupt. If
  1011. * yes, makes the caller to sleep while waiting for such event.
  1012. */
  1013. int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
  1014. atomic_t *stopping)
  1015. {
  1016. struct isp_pipeline *pipe = to_isp_pipeline(me);
  1017. if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
  1018. (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
  1019. !isp_pipeline_ready(pipe)))
  1020. return 0;
  1021. /*
  1022. * atomic_set() doesn't include memory barrier on ARM platform for SMP
  1023. * scenario. We'll call it here to avoid race conditions.
  1024. */
  1025. atomic_set(stopping, 1);
  1026. smp_mb();
  1027. /*
  1028. * If module is the last one, it's writing to memory. In this case,
  1029. * it's necessary to check if the module is already paused due to
  1030. * DMA queue underrun or if it has to wait for next interrupt to be
  1031. * idle.
  1032. * If it isn't the last one, the function won't sleep but *stopping
  1033. * will still be set to warn next submodule caller's interrupt the
  1034. * module wants to be idle.
  1035. */
  1036. if (isp_pipeline_is_last(me)) {
  1037. struct isp_video *video = pipe->output;
  1038. unsigned long flags;
  1039. spin_lock_irqsave(&video->irqlock, flags);
  1040. if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
  1041. spin_unlock_irqrestore(&video->irqlock, flags);
  1042. atomic_set(stopping, 0);
  1043. smp_mb();
  1044. return 0;
  1045. }
  1046. spin_unlock_irqrestore(&video->irqlock, flags);
  1047. if (!wait_event_timeout(*wait, !atomic_read(stopping),
  1048. msecs_to_jiffies(1000))) {
  1049. atomic_set(stopping, 0);
  1050. smp_mb();
  1051. return -ETIMEDOUT;
  1052. }
  1053. }
  1054. return 0;
  1055. }
  1056. /*
  1057. * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
  1058. * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
  1059. * @stopping: flag which tells module wants to stop
  1060. *
  1061. * This function checks if ISP submodule was stopping. In case of yes, it
  1062. * notices the caller by setting stopping to 0 and waking up the wait queue.
  1063. * Returns 1 if it was stopping or 0 otherwise.
  1064. */
  1065. int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
  1066. atomic_t *stopping)
  1067. {
  1068. if (atomic_cmpxchg(stopping, 1, 0)) {
  1069. wake_up(wait);
  1070. return 1;
  1071. }
  1072. return 0;
  1073. }
  1074. /* --------------------------------------------------------------------------
  1075. * Clock management
  1076. */
  1077. #define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
  1078. ISPCTRL_HIST_CLK_EN | \
  1079. ISPCTRL_RSZ_CLK_EN | \
  1080. (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
  1081. (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
  1082. static void __isp_subclk_update(struct isp_device *isp)
  1083. {
  1084. u32 clk = 0;
  1085. /* AEWB and AF share the same clock. */
  1086. if (isp->subclk_resources &
  1087. (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
  1088. clk |= ISPCTRL_H3A_CLK_EN;
  1089. if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
  1090. clk |= ISPCTRL_HIST_CLK_EN;
  1091. if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
  1092. clk |= ISPCTRL_RSZ_CLK_EN;
  1093. /* NOTE: For CCDC & Preview submodules, we need to affect internal
  1094. * RAM as well.
  1095. */
  1096. if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
  1097. clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
  1098. if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
  1099. clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
  1100. isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
  1101. ISPCTRL_CLKS_MASK, clk);
  1102. }
  1103. void omap3isp_subclk_enable(struct isp_device *isp,
  1104. enum isp_subclk_resource res)
  1105. {
  1106. isp->subclk_resources |= res;
  1107. __isp_subclk_update(isp);
  1108. }
  1109. void omap3isp_subclk_disable(struct isp_device *isp,
  1110. enum isp_subclk_resource res)
  1111. {
  1112. isp->subclk_resources &= ~res;
  1113. __isp_subclk_update(isp);
  1114. }
  1115. /*
  1116. * isp_enable_clocks - Enable ISP clocks
  1117. * @isp: OMAP3 ISP device
  1118. *
  1119. * Return 0 if successful, or clk_prepare_enable return value if any of them
  1120. * fails.
  1121. */
  1122. static int isp_enable_clocks(struct isp_device *isp)
  1123. {
  1124. int r;
  1125. unsigned long rate;
  1126. r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
  1127. if (r) {
  1128. dev_err(isp->dev, "failed to enable cam_ick clock\n");
  1129. goto out_clk_enable_ick;
  1130. }
  1131. r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
  1132. if (r) {
  1133. dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
  1134. goto out_clk_enable_mclk;
  1135. }
  1136. r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
  1137. if (r) {
  1138. dev_err(isp->dev, "failed to enable cam_mclk clock\n");
  1139. goto out_clk_enable_mclk;
  1140. }
  1141. rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
  1142. if (rate != CM_CAM_MCLK_HZ)
  1143. dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
  1144. " expected : %d\n"
  1145. " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
  1146. r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
  1147. if (r) {
  1148. dev_err(isp->dev, "failed to enable csi2_fck clock\n");
  1149. goto out_clk_enable_csi2_fclk;
  1150. }
  1151. return 0;
  1152. out_clk_enable_csi2_fclk:
  1153. clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
  1154. out_clk_enable_mclk:
  1155. clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
  1156. out_clk_enable_ick:
  1157. return r;
  1158. }
  1159. /*
  1160. * isp_disable_clocks - Disable ISP clocks
  1161. * @isp: OMAP3 ISP device
  1162. */
  1163. static void isp_disable_clocks(struct isp_device *isp)
  1164. {
  1165. clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
  1166. clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
  1167. clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
  1168. }
  1169. static const char *isp_clocks[] = {
  1170. "cam_ick",
  1171. "cam_mclk",
  1172. "csi2_96m_fck",
  1173. "l3_ick",
  1174. };
  1175. static int isp_get_clocks(struct isp_device *isp)
  1176. {
  1177. struct clk *clk;
  1178. unsigned int i;
  1179. for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
  1180. clk = devm_clk_get(isp->dev, isp_clocks[i]);
  1181. if (IS_ERR(clk)) {
  1182. dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
  1183. return PTR_ERR(clk);
  1184. }
  1185. isp->clock[i] = clk;
  1186. }
  1187. return 0;
  1188. }
  1189. /*
  1190. * omap3isp_get - Acquire the ISP resource.
  1191. *
  1192. * Initializes the clocks for the first acquire.
  1193. *
  1194. * Increment the reference count on the ISP. If the first reference is taken,
  1195. * enable clocks and power-up all submodules.
  1196. *
  1197. * Return a pointer to the ISP device structure, or NULL if an error occurred.
  1198. */
  1199. static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
  1200. {
  1201. struct isp_device *__isp = isp;
  1202. if (isp == NULL)
  1203. return NULL;
  1204. mutex_lock(&isp->isp_mutex);
  1205. if (isp->ref_count > 0)
  1206. goto out;
  1207. if (isp_enable_clocks(isp) < 0) {
  1208. __isp = NULL;
  1209. goto out;
  1210. }
  1211. /* We don't want to restore context before saving it! */
  1212. if (isp->has_context)
  1213. isp_restore_ctx(isp);
  1214. if (irq)
  1215. isp_enable_interrupts(isp);
  1216. out:
  1217. if (__isp != NULL)
  1218. isp->ref_count++;
  1219. mutex_unlock(&isp->isp_mutex);
  1220. return __isp;
  1221. }
  1222. struct isp_device *omap3isp_get(struct isp_device *isp)
  1223. {
  1224. return __omap3isp_get(isp, true);
  1225. }
  1226. /*
  1227. * omap3isp_put - Release the ISP
  1228. *
  1229. * Decrement the reference count on the ISP. If the last reference is released,
  1230. * power-down all submodules, disable clocks and free temporary buffers.
  1231. */
  1232. static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
  1233. {
  1234. if (isp == NULL)
  1235. return;
  1236. mutex_lock(&isp->isp_mutex);
  1237. BUG_ON(isp->ref_count == 0);
  1238. if (--isp->ref_count == 0) {
  1239. isp_disable_interrupts(isp);
  1240. if (save_ctx) {
  1241. isp_save_ctx(isp);
  1242. isp->has_context = 1;
  1243. }
  1244. /* Reset the ISP if an entity has failed to stop. This is the
  1245. * only way to recover from such conditions.
  1246. */
  1247. if (!media_entity_enum_empty(&isp->crashed) ||
  1248. isp->stop_failure)
  1249. isp_reset(isp);
  1250. isp_disable_clocks(isp);
  1251. }
  1252. mutex_unlock(&isp->isp_mutex);
  1253. }
  1254. void omap3isp_put(struct isp_device *isp)
  1255. {
  1256. __omap3isp_put(isp, true);
  1257. }
  1258. /* --------------------------------------------------------------------------
  1259. * Platform device driver
  1260. */
  1261. /*
  1262. * omap3isp_print_status - Prints the values of the ISP Control Module registers
  1263. * @isp: OMAP3 ISP device
  1264. */
  1265. #define ISP_PRINT_REGISTER(isp, name)\
  1266. dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
  1267. isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
  1268. #define SBL_PRINT_REGISTER(isp, name)\
  1269. dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
  1270. isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
  1271. void omap3isp_print_status(struct isp_device *isp)
  1272. {
  1273. dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
  1274. ISP_PRINT_REGISTER(isp, SYSCONFIG);
  1275. ISP_PRINT_REGISTER(isp, SYSSTATUS);
  1276. ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
  1277. ISP_PRINT_REGISTER(isp, IRQ0STATUS);
  1278. ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
  1279. ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
  1280. ISP_PRINT_REGISTER(isp, CTRL);
  1281. ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
  1282. ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
  1283. ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
  1284. ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
  1285. ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
  1286. ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
  1287. ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
  1288. ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
  1289. SBL_PRINT_REGISTER(isp, PCR);
  1290. SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
  1291. dev_dbg(isp->dev, "--------------------------------------------\n");
  1292. }
  1293. #ifdef CONFIG_PM
  1294. /*
  1295. * Power management support.
  1296. *
  1297. * As the ISP can't properly handle an input video stream interruption on a non
  1298. * frame boundary, the ISP pipelines need to be stopped before sensors get
  1299. * suspended. However, as suspending the sensors can require a running clock,
  1300. * which can be provided by the ISP, the ISP can't be completely suspended
  1301. * before the sensor.
  1302. *
  1303. * To solve this problem power management support is split into prepare/complete
  1304. * and suspend/resume operations. The pipelines are stopped in prepare() and the
  1305. * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
  1306. * resume(), and the the pipelines are restarted in complete().
  1307. *
  1308. * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
  1309. * yet.
  1310. */
  1311. static int isp_pm_prepare(struct device *dev)
  1312. {
  1313. struct isp_device *isp = dev_get_drvdata(dev);
  1314. int reset;
  1315. WARN_ON(mutex_is_locked(&isp->isp_mutex));
  1316. if (isp->ref_count == 0)
  1317. return 0;
  1318. reset = isp_suspend_modules(isp);
  1319. isp_disable_interrupts(isp);
  1320. isp_save_ctx(isp);
  1321. if (reset)
  1322. isp_reset(isp);
  1323. return 0;
  1324. }
  1325. static int isp_pm_suspend(struct device *dev)
  1326. {
  1327. struct isp_device *isp = dev_get_drvdata(dev);
  1328. WARN_ON(mutex_is_locked(&isp->isp_mutex));
  1329. if (isp->ref_count)
  1330. isp_disable_clocks(isp);
  1331. return 0;
  1332. }
  1333. static int isp_pm_resume(struct device *dev)
  1334. {
  1335. struct isp_device *isp = dev_get_drvdata(dev);
  1336. if (isp->ref_count == 0)
  1337. return 0;
  1338. return isp_enable_clocks(isp);
  1339. }
  1340. static void isp_pm_complete(struct device *dev)
  1341. {
  1342. struct isp_device *isp = dev_get_drvdata(dev);
  1343. if (isp->ref_count == 0)
  1344. return;
  1345. isp_restore_ctx(isp);
  1346. isp_enable_interrupts(isp);
  1347. isp_resume_modules(isp);
  1348. }
  1349. #else
  1350. #define isp_pm_prepare NULL
  1351. #define isp_pm_suspend NULL
  1352. #define isp_pm_resume NULL
  1353. #define isp_pm_complete NULL
  1354. #endif /* CONFIG_PM */
  1355. static void isp_unregister_entities(struct isp_device *isp)
  1356. {
  1357. media_device_unregister(&isp->media_dev);
  1358. omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
  1359. omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
  1360. omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
  1361. omap3isp_preview_unregister_entities(&isp->isp_prev);
  1362. omap3isp_resizer_unregister_entities(&isp->isp_res);
  1363. omap3isp_stat_unregister_entities(&isp->isp_aewb);
  1364. omap3isp_stat_unregister_entities(&isp->isp_af);
  1365. omap3isp_stat_unregister_entities(&isp->isp_hist);
  1366. v4l2_device_unregister(&isp->v4l2_dev);
  1367. media_device_cleanup(&isp->media_dev);
  1368. }
  1369. static int isp_link_entity(
  1370. struct isp_device *isp, struct media_entity *entity,
  1371. enum isp_interface_type interface)
  1372. {
  1373. struct media_entity *input;
  1374. unsigned int flags;
  1375. unsigned int pad;
  1376. unsigned int i;
  1377. /* Connect the sensor to the correct interface module.
  1378. * Parallel sensors are connected directly to the CCDC, while
  1379. * serial sensors are connected to the CSI2a, CCP2b or CSI2c
  1380. * receiver through CSIPHY1 or CSIPHY2.
  1381. */
  1382. switch (interface) {
  1383. case ISP_INTERFACE_PARALLEL:
  1384. input = &isp->isp_ccdc.subdev.entity;
  1385. pad = CCDC_PAD_SINK;
  1386. flags = 0;
  1387. break;
  1388. case ISP_INTERFACE_CSI2A_PHY2:
  1389. input = &isp->isp_csi2a.subdev.entity;
  1390. pad = CSI2_PAD_SINK;
  1391. flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
  1392. break;
  1393. case ISP_INTERFACE_CCP2B_PHY1:
  1394. case ISP_INTERFACE_CCP2B_PHY2:
  1395. input = &isp->isp_ccp2.subdev.entity;
  1396. pad = CCP2_PAD_SINK;
  1397. flags = 0;
  1398. break;
  1399. case ISP_INTERFACE_CSI2C_PHY1:
  1400. input = &isp->isp_csi2c.subdev.entity;
  1401. pad = CSI2_PAD_SINK;
  1402. flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
  1403. break;
  1404. default:
  1405. dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
  1406. interface);
  1407. return -EINVAL;
  1408. }
  1409. /*
  1410. * Not all interfaces are available on all revisions of the
  1411. * ISP. The sub-devices of those interfaces aren't initialised
  1412. * in such a case. Check this by ensuring the num_pads is
  1413. * non-zero.
  1414. */
  1415. if (!input->num_pads) {
  1416. dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
  1417. interface);
  1418. return -EINVAL;
  1419. }
  1420. for (i = 0; i < entity->num_pads; i++) {
  1421. if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
  1422. break;
  1423. }
  1424. if (i == entity->num_pads) {
  1425. dev_err(isp->dev, "%s: no source pad in external entity %s\n",
  1426. __func__, entity->name);
  1427. return -EINVAL;
  1428. }
  1429. return media_create_pad_link(entity, i, input, pad, flags);
  1430. }
  1431. static int isp_register_entities(struct isp_device *isp)
  1432. {
  1433. int ret;
  1434. isp->media_dev.dev = isp->dev;
  1435. strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
  1436. sizeof(isp->media_dev.model));
  1437. isp->media_dev.hw_revision = isp->revision;
  1438. isp->media_dev.ops = &isp_media_ops;
  1439. media_device_init(&isp->media_dev);
  1440. isp->v4l2_dev.mdev = &isp->media_dev;
  1441. ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
  1442. if (ret < 0) {
  1443. dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
  1444. __func__, ret);
  1445. goto done;
  1446. }
  1447. /* Register internal entities */
  1448. ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
  1449. if (ret < 0)
  1450. goto done;
  1451. ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
  1452. if (ret < 0)
  1453. goto done;
  1454. ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
  1455. if (ret < 0)
  1456. goto done;
  1457. ret = omap3isp_preview_register_entities(&isp->isp_prev,
  1458. &isp->v4l2_dev);
  1459. if (ret < 0)
  1460. goto done;
  1461. ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
  1462. if (ret < 0)
  1463. goto done;
  1464. ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
  1465. if (ret < 0)
  1466. goto done;
  1467. ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
  1468. if (ret < 0)
  1469. goto done;
  1470. ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
  1471. if (ret < 0)
  1472. goto done;
  1473. done:
  1474. if (ret < 0)
  1475. isp_unregister_entities(isp);
  1476. return ret;
  1477. }
  1478. /*
  1479. * isp_create_links() - Create links for internal and external ISP entities
  1480. * @isp : Pointer to ISP device
  1481. *
  1482. * This function creates all links between ISP internal and external entities.
  1483. *
  1484. * Return: A negative error code on failure or zero on success. Possible error
  1485. * codes are those returned by media_create_pad_link().
  1486. */
  1487. static int isp_create_links(struct isp_device *isp)
  1488. {
  1489. int ret;
  1490. /* Create links between entities and video nodes. */
  1491. ret = media_create_pad_link(
  1492. &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
  1493. &isp->isp_csi2a.video_out.video.entity, 0, 0);
  1494. if (ret < 0)
  1495. return ret;
  1496. ret = media_create_pad_link(
  1497. &isp->isp_ccp2.video_in.video.entity, 0,
  1498. &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
  1499. if (ret < 0)
  1500. return ret;
  1501. ret = media_create_pad_link(
  1502. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
  1503. &isp->isp_ccdc.video_out.video.entity, 0, 0);
  1504. if (ret < 0)
  1505. return ret;
  1506. ret = media_create_pad_link(
  1507. &isp->isp_prev.video_in.video.entity, 0,
  1508. &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
  1509. if (ret < 0)
  1510. return ret;
  1511. ret = media_create_pad_link(
  1512. &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
  1513. &isp->isp_prev.video_out.video.entity, 0, 0);
  1514. if (ret < 0)
  1515. return ret;
  1516. ret = media_create_pad_link(
  1517. &isp->isp_res.video_in.video.entity, 0,
  1518. &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
  1519. if (ret < 0)
  1520. return ret;
  1521. ret = media_create_pad_link(
  1522. &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
  1523. &isp->isp_res.video_out.video.entity, 0, 0);
  1524. if (ret < 0)
  1525. return ret;
  1526. /* Create links between entities. */
  1527. ret = media_create_pad_link(
  1528. &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
  1529. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
  1530. if (ret < 0)
  1531. return ret;
  1532. ret = media_create_pad_link(
  1533. &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
  1534. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
  1535. if (ret < 0)
  1536. return ret;
  1537. ret = media_create_pad_link(
  1538. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
  1539. &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
  1540. if (ret < 0)
  1541. return ret;
  1542. ret = media_create_pad_link(
  1543. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
  1544. &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
  1545. if (ret < 0)
  1546. return ret;
  1547. ret = media_create_pad_link(
  1548. &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
  1549. &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
  1550. if (ret < 0)
  1551. return ret;
  1552. ret = media_create_pad_link(
  1553. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
  1554. &isp->isp_aewb.subdev.entity, 0,
  1555. MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
  1556. if (ret < 0)
  1557. return ret;
  1558. ret = media_create_pad_link(
  1559. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
  1560. &isp->isp_af.subdev.entity, 0,
  1561. MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
  1562. if (ret < 0)
  1563. return ret;
  1564. ret = media_create_pad_link(
  1565. &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
  1566. &isp->isp_hist.subdev.entity, 0,
  1567. MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
  1568. if (ret < 0)
  1569. return ret;
  1570. return 0;
  1571. }
  1572. static void isp_cleanup_modules(struct isp_device *isp)
  1573. {
  1574. omap3isp_h3a_aewb_cleanup(isp);
  1575. omap3isp_h3a_af_cleanup(isp);
  1576. omap3isp_hist_cleanup(isp);
  1577. omap3isp_resizer_cleanup(isp);
  1578. omap3isp_preview_cleanup(isp);
  1579. omap3isp_ccdc_cleanup(isp);
  1580. omap3isp_ccp2_cleanup(isp);
  1581. omap3isp_csi2_cleanup(isp);
  1582. omap3isp_csiphy_cleanup(isp);
  1583. }
  1584. static int isp_initialize_modules(struct isp_device *isp)
  1585. {
  1586. int ret;
  1587. ret = omap3isp_csiphy_init(isp);
  1588. if (ret < 0) {
  1589. dev_err(isp->dev, "CSI PHY initialization failed\n");
  1590. return ret;
  1591. }
  1592. ret = omap3isp_csi2_init(isp);
  1593. if (ret < 0) {
  1594. dev_err(isp->dev, "CSI2 initialization failed\n");
  1595. goto error_csi2;
  1596. }
  1597. ret = omap3isp_ccp2_init(isp);
  1598. if (ret < 0) {
  1599. if (ret != -EPROBE_DEFER)
  1600. dev_err(isp->dev, "CCP2 initialization failed\n");
  1601. goto error_ccp2;
  1602. }
  1603. ret = omap3isp_ccdc_init(isp);
  1604. if (ret < 0) {
  1605. dev_err(isp->dev, "CCDC initialization failed\n");
  1606. goto error_ccdc;
  1607. }
  1608. ret = omap3isp_preview_init(isp);
  1609. if (ret < 0) {
  1610. dev_err(isp->dev, "Preview initialization failed\n");
  1611. goto error_preview;
  1612. }
  1613. ret = omap3isp_resizer_init(isp);
  1614. if (ret < 0) {
  1615. dev_err(isp->dev, "Resizer initialization failed\n");
  1616. goto error_resizer;
  1617. }
  1618. ret = omap3isp_hist_init(isp);
  1619. if (ret < 0) {
  1620. dev_err(isp->dev, "Histogram initialization failed\n");
  1621. goto error_hist;
  1622. }
  1623. ret = omap3isp_h3a_aewb_init(isp);
  1624. if (ret < 0) {
  1625. dev_err(isp->dev, "H3A AEWB initialization failed\n");
  1626. goto error_h3a_aewb;
  1627. }
  1628. ret = omap3isp_h3a_af_init(isp);
  1629. if (ret < 0) {
  1630. dev_err(isp->dev, "H3A AF initialization failed\n");
  1631. goto error_h3a_af;
  1632. }
  1633. return 0;
  1634. error_h3a_af:
  1635. omap3isp_h3a_aewb_cleanup(isp);
  1636. error_h3a_aewb:
  1637. omap3isp_hist_cleanup(isp);
  1638. error_hist:
  1639. omap3isp_resizer_cleanup(isp);
  1640. error_resizer:
  1641. omap3isp_preview_cleanup(isp);
  1642. error_preview:
  1643. omap3isp_ccdc_cleanup(isp);
  1644. error_ccdc:
  1645. omap3isp_ccp2_cleanup(isp);
  1646. error_ccp2:
  1647. omap3isp_csi2_cleanup(isp);
  1648. error_csi2:
  1649. omap3isp_csiphy_cleanup(isp);
  1650. return ret;
  1651. }
  1652. static void isp_detach_iommu(struct isp_device *isp)
  1653. {
  1654. #ifdef CONFIG_ARM_DMA_USE_IOMMU
  1655. arm_iommu_detach_device(isp->dev);
  1656. arm_iommu_release_mapping(isp->mapping);
  1657. isp->mapping = NULL;
  1658. #endif
  1659. }
  1660. static int isp_attach_iommu(struct isp_device *isp)
  1661. {
  1662. #ifdef CONFIG_ARM_DMA_USE_IOMMU
  1663. struct dma_iommu_mapping *mapping;
  1664. int ret;
  1665. /*
  1666. * Create the ARM mapping, used by the ARM DMA mapping core to allocate
  1667. * VAs. This will allocate a corresponding IOMMU domain.
  1668. */
  1669. mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
  1670. if (IS_ERR(mapping)) {
  1671. dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
  1672. return PTR_ERR(mapping);
  1673. }
  1674. isp->mapping = mapping;
  1675. /* Attach the ARM VA mapping to the device. */
  1676. ret = arm_iommu_attach_device(isp->dev, mapping);
  1677. if (ret < 0) {
  1678. dev_err(isp->dev, "failed to attach device to VA mapping\n");
  1679. goto error;
  1680. }
  1681. return 0;
  1682. error:
  1683. arm_iommu_release_mapping(isp->mapping);
  1684. isp->mapping = NULL;
  1685. return ret;
  1686. #else
  1687. return -ENODEV;
  1688. #endif
  1689. }
  1690. /*
  1691. * isp_remove - Remove ISP platform device
  1692. * @pdev: Pointer to ISP platform device
  1693. *
  1694. * Always returns 0.
  1695. */
  1696. static int isp_remove(struct platform_device *pdev)
  1697. {
  1698. struct isp_device *isp = platform_get_drvdata(pdev);
  1699. v4l2_async_notifier_unregister(&isp->notifier);
  1700. isp_unregister_entities(isp);
  1701. isp_cleanup_modules(isp);
  1702. isp_xclk_cleanup(isp);
  1703. __omap3isp_get(isp, false);
  1704. isp_detach_iommu(isp);
  1705. __omap3isp_put(isp, false);
  1706. media_entity_enum_cleanup(&isp->crashed);
  1707. v4l2_async_notifier_cleanup(&isp->notifier);
  1708. return 0;
  1709. }
  1710. enum isp_of_phy {
  1711. ISP_OF_PHY_PARALLEL = 0,
  1712. ISP_OF_PHY_CSIPHY1,
  1713. ISP_OF_PHY_CSIPHY2,
  1714. };
  1715. static int isp_fwnode_parse(struct device *dev,
  1716. struct v4l2_fwnode_endpoint *vep,
  1717. struct v4l2_async_subdev *asd)
  1718. {
  1719. struct isp_async_subdev *isd =
  1720. container_of(asd, struct isp_async_subdev, asd);
  1721. struct isp_bus_cfg *buscfg = &isd->bus;
  1722. bool csi1 = false;
  1723. unsigned int i;
  1724. dev_dbg(dev, "parsing endpoint %pOF, interface %u\n",
  1725. to_of_node(vep->base.local_fwnode), vep->base.port);
  1726. switch (vep->base.port) {
  1727. case ISP_OF_PHY_PARALLEL:
  1728. buscfg->interface = ISP_INTERFACE_PARALLEL;
  1729. buscfg->bus.parallel.data_lane_shift =
  1730. vep->bus.parallel.data_shift;
  1731. buscfg->bus.parallel.clk_pol =
  1732. !!(vep->bus.parallel.flags
  1733. & V4L2_MBUS_PCLK_SAMPLE_FALLING);
  1734. buscfg->bus.parallel.hs_pol =
  1735. !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
  1736. buscfg->bus.parallel.vs_pol =
  1737. !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
  1738. buscfg->bus.parallel.fld_pol =
  1739. !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
  1740. buscfg->bus.parallel.data_pol =
  1741. !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
  1742. buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
  1743. break;
  1744. case ISP_OF_PHY_CSIPHY1:
  1745. case ISP_OF_PHY_CSIPHY2:
  1746. switch (vep->bus_type) {
  1747. case V4L2_MBUS_CCP2:
  1748. case V4L2_MBUS_CSI1:
  1749. dev_dbg(dev, "CSI-1/CCP-2 configuration\n");
  1750. csi1 = true;
  1751. break;
  1752. case V4L2_MBUS_CSI2:
  1753. dev_dbg(dev, "CSI-2 configuration\n");
  1754. csi1 = false;
  1755. break;
  1756. default:
  1757. dev_err(dev, "unsupported bus type %u\n",
  1758. vep->bus_type);
  1759. return -EINVAL;
  1760. }
  1761. switch (vep->base.port) {
  1762. case ISP_OF_PHY_CSIPHY1:
  1763. if (csi1)
  1764. buscfg->interface = ISP_INTERFACE_CCP2B_PHY1;
  1765. else
  1766. buscfg->interface = ISP_INTERFACE_CSI2C_PHY1;
  1767. break;
  1768. case ISP_OF_PHY_CSIPHY2:
  1769. if (csi1)
  1770. buscfg->interface = ISP_INTERFACE_CCP2B_PHY2;
  1771. else
  1772. buscfg->interface = ISP_INTERFACE_CSI2A_PHY2;
  1773. break;
  1774. }
  1775. if (csi1) {
  1776. buscfg->bus.ccp2.lanecfg.clk.pos =
  1777. vep->bus.mipi_csi1.clock_lane;
  1778. buscfg->bus.ccp2.lanecfg.clk.pol =
  1779. vep->bus.mipi_csi1.lane_polarity[0];
  1780. dev_dbg(dev, "clock lane polarity %u, pos %u\n",
  1781. buscfg->bus.ccp2.lanecfg.clk.pol,
  1782. buscfg->bus.ccp2.lanecfg.clk.pos);
  1783. buscfg->bus.ccp2.lanecfg.data[0].pos =
  1784. vep->bus.mipi_csi1.data_lane;
  1785. buscfg->bus.ccp2.lanecfg.data[0].pol =
  1786. vep->bus.mipi_csi1.lane_polarity[1];
  1787. dev_dbg(dev, "data lane polarity %u, pos %u\n",
  1788. buscfg->bus.ccp2.lanecfg.data[0].pol,
  1789. buscfg->bus.ccp2.lanecfg.data[0].pos);
  1790. buscfg->bus.ccp2.strobe_clk_pol =
  1791. vep->bus.mipi_csi1.clock_inv;
  1792. buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
  1793. buscfg->bus.ccp2.ccp2_mode =
  1794. vep->bus_type == V4L2_MBUS_CCP2;
  1795. buscfg->bus.ccp2.vp_clk_pol = 1;
  1796. buscfg->bus.ccp2.crc = 1;
  1797. } else {
  1798. buscfg->bus.csi2.lanecfg.clk.pos =
  1799. vep->bus.mipi_csi2.clock_lane;
  1800. buscfg->bus.csi2.lanecfg.clk.pol =
  1801. vep->bus.mipi_csi2.lane_polarities[0];
  1802. dev_dbg(dev, "clock lane polarity %u, pos %u\n",
  1803. buscfg->bus.csi2.lanecfg.clk.pol,
  1804. buscfg->bus.csi2.lanecfg.clk.pos);
  1805. buscfg->bus.csi2.num_data_lanes =
  1806. vep->bus.mipi_csi2.num_data_lanes;
  1807. for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
  1808. buscfg->bus.csi2.lanecfg.data[i].pos =
  1809. vep->bus.mipi_csi2.data_lanes[i];
  1810. buscfg->bus.csi2.lanecfg.data[i].pol =
  1811. vep->bus.mipi_csi2.lane_polarities[i + 1];
  1812. dev_dbg(dev,
  1813. "data lane %u polarity %u, pos %u\n", i,
  1814. buscfg->bus.csi2.lanecfg.data[i].pol,
  1815. buscfg->bus.csi2.lanecfg.data[i].pos);
  1816. }
  1817. /*
  1818. * FIXME: now we assume the CRC is always there.
  1819. * Implement a way to obtain this information from the
  1820. * sensor. Frame descriptors, perhaps?
  1821. */
  1822. buscfg->bus.csi2.crc = 1;
  1823. }
  1824. break;
  1825. default:
  1826. dev_warn(dev, "%pOF: invalid interface %u\n",
  1827. to_of_node(vep->base.local_fwnode), vep->base.port);
  1828. return -EINVAL;
  1829. }
  1830. return 0;
  1831. }
  1832. static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
  1833. {
  1834. struct isp_device *isp = container_of(async, struct isp_device,
  1835. notifier);
  1836. struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
  1837. struct v4l2_subdev *sd;
  1838. int ret;
  1839. ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
  1840. if (ret)
  1841. return ret;
  1842. list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
  1843. if (sd->notifier != &isp->notifier)
  1844. continue;
  1845. ret = isp_link_entity(isp, &sd->entity,
  1846. v4l2_subdev_to_bus_cfg(sd)->interface);
  1847. if (ret < 0)
  1848. return ret;
  1849. }
  1850. ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
  1851. if (ret < 0)
  1852. return ret;
  1853. return media_device_register(&isp->media_dev);
  1854. }
  1855. static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
  1856. .complete = isp_subdev_notifier_complete,
  1857. };
  1858. /*
  1859. * isp_probe - Probe ISP platform device
  1860. * @pdev: Pointer to ISP platform device
  1861. *
  1862. * Returns 0 if successful,
  1863. * -ENOMEM if no memory available,
  1864. * -ENODEV if no platform device resources found
  1865. * or no space for remapping registers,
  1866. * -EINVAL if couldn't install ISR,
  1867. * or clk_get return error value.
  1868. */
  1869. static int isp_probe(struct platform_device *pdev)
  1870. {
  1871. struct isp_device *isp;
  1872. struct resource *mem;
  1873. int ret;
  1874. int i, m;
  1875. isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
  1876. if (!isp) {
  1877. dev_err(&pdev->dev, "could not allocate memory\n");
  1878. return -ENOMEM;
  1879. }
  1880. ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
  1881. "ti,phy-type", &isp->phy_type);
  1882. if (ret)
  1883. return ret;
  1884. isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  1885. "syscon");
  1886. if (IS_ERR(isp->syscon))
  1887. return PTR_ERR(isp->syscon);
  1888. ret = of_property_read_u32_index(pdev->dev.of_node,
  1889. "syscon", 1, &isp->syscon_offset);
  1890. if (ret)
  1891. return ret;
  1892. isp->autoidle = autoidle;
  1893. mutex_init(&isp->isp_mutex);
  1894. spin_lock_init(&isp->stat_lock);
  1895. ret = v4l2_async_notifier_parse_fwnode_endpoints(
  1896. &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev),
  1897. isp_fwnode_parse);
  1898. if (ret < 0)
  1899. goto error;
  1900. isp->dev = &pdev->dev;
  1901. isp->ref_count = 0;
  1902. ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
  1903. if (ret)
  1904. goto error;
  1905. platform_set_drvdata(pdev, isp);
  1906. /* Regulators */
  1907. isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
  1908. isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
  1909. /* Clocks
  1910. *
  1911. * The ISP clock tree is revision-dependent. We thus need to enable ICLK
  1912. * manually to read the revision before calling __omap3isp_get().
  1913. *
  1914. * Start by mapping the ISP MMIO area, which is in two pieces.
  1915. * The ISP IOMMU is in between. Map both now, and fill in the
  1916. * ISP revision specific portions a little later in the
  1917. * function.
  1918. */
  1919. for (i = 0; i < 2; i++) {
  1920. unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
  1921. mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
  1922. isp->mmio_base[map_idx] =
  1923. devm_ioremap_resource(isp->dev, mem);
  1924. if (IS_ERR(isp->mmio_base[map_idx])) {
  1925. ret = PTR_ERR(isp->mmio_base[map_idx]);
  1926. goto error;
  1927. }
  1928. }
  1929. ret = isp_get_clocks(isp);
  1930. if (ret < 0)
  1931. goto error;
  1932. ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
  1933. if (ret < 0)
  1934. goto error;
  1935. isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
  1936. dev_info(isp->dev, "Revision %d.%d found\n",
  1937. (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
  1938. clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
  1939. if (__omap3isp_get(isp, false) == NULL) {
  1940. ret = -ENODEV;
  1941. goto error;
  1942. }
  1943. ret = isp_reset(isp);
  1944. if (ret < 0)
  1945. goto error_isp;
  1946. ret = isp_xclk_init(isp);
  1947. if (ret < 0)
  1948. goto error_isp;
  1949. /* Memory resources */
  1950. for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
  1951. if (isp->revision == isp_res_maps[m].isp_rev)
  1952. break;
  1953. if (m == ARRAY_SIZE(isp_res_maps)) {
  1954. dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
  1955. (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
  1956. ret = -ENODEV;
  1957. goto error_isp;
  1958. }
  1959. for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
  1960. isp->mmio_base[i] =
  1961. isp->mmio_base[0] + isp_res_maps[m].offset[i];
  1962. for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
  1963. isp->mmio_base[i] =
  1964. isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
  1965. + isp_res_maps[m].offset[i];
  1966. isp->mmio_hist_base_phys =
  1967. mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
  1968. /* IOMMU */
  1969. ret = isp_attach_iommu(isp);
  1970. if (ret < 0) {
  1971. dev_err(&pdev->dev, "unable to attach to IOMMU\n");
  1972. goto error_isp;
  1973. }
  1974. /* Interrupt */
  1975. ret = platform_get_irq(pdev, 0);
  1976. if (ret <= 0) {
  1977. dev_err(isp->dev, "No IRQ resource\n");
  1978. ret = -ENODEV;
  1979. goto error_iommu;
  1980. }
  1981. isp->irq_num = ret;
  1982. if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
  1983. "OMAP3 ISP", isp)) {
  1984. dev_err(isp->dev, "Unable to request IRQ\n");
  1985. ret = -EINVAL;
  1986. goto error_iommu;
  1987. }
  1988. /* Entities */
  1989. ret = isp_initialize_modules(isp);
  1990. if (ret < 0)
  1991. goto error_iommu;
  1992. ret = isp_register_entities(isp);
  1993. if (ret < 0)
  1994. goto error_modules;
  1995. ret = isp_create_links(isp);
  1996. if (ret < 0)
  1997. goto error_register_entities;
  1998. isp->notifier.ops = &isp_subdev_notifier_ops;
  1999. ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
  2000. if (ret)
  2001. goto error_register_entities;
  2002. isp_core_init(isp, 1);
  2003. omap3isp_put(isp);
  2004. return 0;
  2005. error_register_entities:
  2006. isp_unregister_entities(isp);
  2007. error_modules:
  2008. isp_cleanup_modules(isp);
  2009. error_iommu:
  2010. isp_detach_iommu(isp);
  2011. error_isp:
  2012. isp_xclk_cleanup(isp);
  2013. __omap3isp_put(isp, false);
  2014. error:
  2015. v4l2_async_notifier_cleanup(&isp->notifier);
  2016. mutex_destroy(&isp->isp_mutex);
  2017. return ret;
  2018. }
  2019. static const struct dev_pm_ops omap3isp_pm_ops = {
  2020. .prepare = isp_pm_prepare,
  2021. .suspend = isp_pm_suspend,
  2022. .resume = isp_pm_resume,
  2023. .complete = isp_pm_complete,
  2024. };
  2025. static struct platform_device_id omap3isp_id_table[] = {
  2026. { "omap3isp", 0 },
  2027. { },
  2028. };
  2029. MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
  2030. static const struct of_device_id omap3isp_of_table[] = {
  2031. { .compatible = "ti,omap3-isp" },
  2032. { },
  2033. };
  2034. MODULE_DEVICE_TABLE(of, omap3isp_of_table);
  2035. static struct platform_driver omap3isp_driver = {
  2036. .probe = isp_probe,
  2037. .remove = isp_remove,
  2038. .id_table = omap3isp_id_table,
  2039. .driver = {
  2040. .name = "omap3isp",
  2041. .pm = &omap3isp_pm_ops,
  2042. .of_match_table = omap3isp_of_table,
  2043. },
  2044. };
  2045. module_platform_driver(omap3isp_driver);
  2046. MODULE_AUTHOR("Nokia Corporation");
  2047. MODULE_DESCRIPTION("TI OMAP3 ISP driver");
  2048. MODULE_LICENSE("GPL");
  2049. MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);