ispcsi2.c 36 KB

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  1. /*
  2. * ispcsi2.c
  3. *
  4. * TI OMAP3 ISP - CSI2 module
  5. *
  6. * Copyright (C) 2010 Nokia Corporation
  7. * Copyright (C) 2009 Texas Instruments, Inc.
  8. *
  9. * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10. * Sakari Ailus <sakari.ailus@iki.fi>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/delay.h>
  17. #include <media/v4l2-common.h>
  18. #include <linux/v4l2-mediabus.h>
  19. #include <linux/mm.h>
  20. #include "isp.h"
  21. #include "ispreg.h"
  22. #include "ispcsi2.h"
  23. /*
  24. * csi2_if_enable - Enable CSI2 Receiver interface.
  25. * @enable: enable flag
  26. *
  27. */
  28. static void csi2_if_enable(struct isp_device *isp,
  29. struct isp_csi2_device *csi2, u8 enable)
  30. {
  31. struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
  32. isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN,
  33. enable ? ISPCSI2_CTRL_IF_EN : 0);
  34. currctrl->if_enable = enable;
  35. }
  36. /*
  37. * csi2_recv_config - CSI2 receiver module configuration.
  38. * @currctrl: isp_csi2_ctrl_cfg structure
  39. *
  40. */
  41. static void csi2_recv_config(struct isp_device *isp,
  42. struct isp_csi2_device *csi2,
  43. struct isp_csi2_ctrl_cfg *currctrl)
  44. {
  45. u32 reg;
  46. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
  47. if (currctrl->frame_mode)
  48. reg |= ISPCSI2_CTRL_FRAME;
  49. else
  50. reg &= ~ISPCSI2_CTRL_FRAME;
  51. if (currctrl->vp_clk_enable)
  52. reg |= ISPCSI2_CTRL_VP_CLK_EN;
  53. else
  54. reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
  55. if (currctrl->vp_only_enable)
  56. reg |= ISPCSI2_CTRL_VP_ONLY_EN;
  57. else
  58. reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
  59. reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
  60. reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
  61. if (currctrl->ecc_enable)
  62. reg |= ISPCSI2_CTRL_ECC_EN;
  63. else
  64. reg &= ~ISPCSI2_CTRL_ECC_EN;
  65. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
  66. }
  67. static const unsigned int csi2_input_fmts[] = {
  68. MEDIA_BUS_FMT_SGRBG10_1X10,
  69. MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  70. MEDIA_BUS_FMT_SRGGB10_1X10,
  71. MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
  72. MEDIA_BUS_FMT_SBGGR10_1X10,
  73. MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
  74. MEDIA_BUS_FMT_SGBRG10_1X10,
  75. MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
  76. MEDIA_BUS_FMT_YUYV8_2X8,
  77. };
  78. /* To set the format on the CSI2 requires a mapping function that takes
  79. * the following inputs:
  80. * - 3 different formats (at this time)
  81. * - 2 destinations (mem, vp+mem) (vp only handled separately)
  82. * - 2 decompression options (on, off)
  83. * - 2 isp revisions (certain format must be handled differently on OMAP3630)
  84. * Output should be CSI2 frame format code
  85. * Array indices as follows: [format][dest][decompr][is_3630]
  86. * Not all combinations are valid. 0 means invalid.
  87. */
  88. static const u16 __csi2_fmt_map[3][2][2][2] = {
  89. /* RAW10 formats */
  90. {
  91. /* Output to memory */
  92. {
  93. /* No DPCM decompression */
  94. { CSI2_PIX_FMT_RAW10_EXP16, CSI2_PIX_FMT_RAW10_EXP16 },
  95. /* DPCM decompression */
  96. { 0, 0 },
  97. },
  98. /* Output to both */
  99. {
  100. /* No DPCM decompression */
  101. { CSI2_PIX_FMT_RAW10_EXP16_VP,
  102. CSI2_PIX_FMT_RAW10_EXP16_VP },
  103. /* DPCM decompression */
  104. { 0, 0 },
  105. },
  106. },
  107. /* RAW10 DPCM8 formats */
  108. {
  109. /* Output to memory */
  110. {
  111. /* No DPCM decompression */
  112. { CSI2_PIX_FMT_RAW8, CSI2_USERDEF_8BIT_DATA1 },
  113. /* DPCM decompression */
  114. { CSI2_PIX_FMT_RAW8_DPCM10_EXP16,
  115. CSI2_USERDEF_8BIT_DATA1_DPCM10 },
  116. },
  117. /* Output to both */
  118. {
  119. /* No DPCM decompression */
  120. { CSI2_PIX_FMT_RAW8_VP,
  121. CSI2_PIX_FMT_RAW8_VP },
  122. /* DPCM decompression */
  123. { CSI2_PIX_FMT_RAW8_DPCM10_VP,
  124. CSI2_USERDEF_8BIT_DATA1_DPCM10_VP },
  125. },
  126. },
  127. /* YUYV8 2X8 formats */
  128. {
  129. /* Output to memory */
  130. {
  131. /* No DPCM decompression */
  132. { CSI2_PIX_FMT_YUV422_8BIT,
  133. CSI2_PIX_FMT_YUV422_8BIT },
  134. /* DPCM decompression */
  135. { 0, 0 },
  136. },
  137. /* Output to both */
  138. {
  139. /* No DPCM decompression */
  140. { CSI2_PIX_FMT_YUV422_8BIT_VP,
  141. CSI2_PIX_FMT_YUV422_8BIT_VP },
  142. /* DPCM decompression */
  143. { 0, 0 },
  144. },
  145. },
  146. };
  147. /*
  148. * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
  149. * @csi2: ISP CSI2 device
  150. *
  151. * Returns CSI2 physical format id
  152. */
  153. static u16 csi2_ctx_map_format(struct isp_csi2_device *csi2)
  154. {
  155. const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
  156. int fmtidx, destidx, is_3630;
  157. switch (fmt->code) {
  158. case MEDIA_BUS_FMT_SGRBG10_1X10:
  159. case MEDIA_BUS_FMT_SRGGB10_1X10:
  160. case MEDIA_BUS_FMT_SBGGR10_1X10:
  161. case MEDIA_BUS_FMT_SGBRG10_1X10:
  162. fmtidx = 0;
  163. break;
  164. case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
  165. case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
  166. case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
  167. case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
  168. fmtidx = 1;
  169. break;
  170. case MEDIA_BUS_FMT_YUYV8_2X8:
  171. fmtidx = 2;
  172. break;
  173. default:
  174. WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
  175. fmt->code);
  176. return 0;
  177. }
  178. if (!(csi2->output & CSI2_OUTPUT_CCDC) &&
  179. !(csi2->output & CSI2_OUTPUT_MEMORY)) {
  180. /* Neither output enabled is a valid combination */
  181. return CSI2_PIX_FMT_OTHERS;
  182. }
  183. /* If we need to skip frames at the beginning of the stream disable the
  184. * video port to avoid sending the skipped frames to the CCDC.
  185. */
  186. destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_CCDC);
  187. is_3630 = csi2->isp->revision == ISP_REVISION_15_0;
  188. return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress][is_3630];
  189. }
  190. /*
  191. * csi2_set_outaddr - Set memory address to save output image
  192. * @csi2: Pointer to ISP CSI2a device.
  193. * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
  194. *
  195. * Sets the memory address where the output will be saved.
  196. *
  197. * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
  198. * boundary.
  199. */
  200. static void csi2_set_outaddr(struct isp_csi2_device *csi2, u32 addr)
  201. {
  202. struct isp_device *isp = csi2->isp;
  203. struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0];
  204. ctx->ping_addr = addr;
  205. ctx->pong_addr = addr;
  206. isp_reg_writel(isp, ctx->ping_addr,
  207. csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
  208. isp_reg_writel(isp, ctx->pong_addr,
  209. csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
  210. }
  211. /*
  212. * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
  213. * be enabled by CSI2.
  214. * @format_id: mapped format id
  215. *
  216. */
  217. static inline int is_usr_def_mapping(u32 format_id)
  218. {
  219. return (format_id & 0x40) ? 1 : 0;
  220. }
  221. /*
  222. * csi2_ctx_enable - Enable specified CSI2 context
  223. * @ctxnum: Context number, valid between 0 and 7 values.
  224. * @enable: enable
  225. *
  226. */
  227. static void csi2_ctx_enable(struct isp_device *isp,
  228. struct isp_csi2_device *csi2, u8 ctxnum, u8 enable)
  229. {
  230. struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
  231. unsigned int skip = 0;
  232. u32 reg;
  233. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
  234. if (enable) {
  235. if (csi2->frame_skip)
  236. skip = csi2->frame_skip;
  237. else if (csi2->output & CSI2_OUTPUT_MEMORY)
  238. skip = 1;
  239. reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
  240. reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
  241. | (skip << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
  242. | ISPCSI2_CTX_CTRL1_CTX_EN;
  243. } else {
  244. reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
  245. }
  246. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
  247. ctx->enabled = enable;
  248. }
  249. /*
  250. * csi2_ctx_config - CSI2 context configuration.
  251. * @ctx: context configuration
  252. *
  253. */
  254. static void csi2_ctx_config(struct isp_device *isp,
  255. struct isp_csi2_device *csi2,
  256. struct isp_csi2_ctx_cfg *ctx)
  257. {
  258. u32 reg;
  259. /* Set up CSI2_CTx_CTRL1 */
  260. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
  261. if (ctx->eof_enabled)
  262. reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
  263. else
  264. reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
  265. if (ctx->eol_enabled)
  266. reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
  267. else
  268. reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
  269. if (ctx->checksum_enabled)
  270. reg |= ISPCSI2_CTX_CTRL1_CS_EN;
  271. else
  272. reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
  273. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
  274. /* Set up CSI2_CTx_CTRL2 */
  275. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
  276. reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
  277. reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
  278. reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
  279. reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
  280. if (ctx->dpcm_decompress) {
  281. if (ctx->dpcm_predictor)
  282. reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
  283. else
  284. reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
  285. }
  286. if (is_usr_def_mapping(ctx->format_id)) {
  287. reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
  288. reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
  289. }
  290. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
  291. /* Set up CSI2_CTx_CTRL3 */
  292. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
  293. reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
  294. reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
  295. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
  296. /* Set up CSI2_CTx_DAT_OFST */
  297. reg = isp_reg_readl(isp, csi2->regs1,
  298. ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
  299. reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
  300. reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
  301. isp_reg_writel(isp, reg, csi2->regs1,
  302. ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
  303. isp_reg_writel(isp, ctx->ping_addr,
  304. csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
  305. isp_reg_writel(isp, ctx->pong_addr,
  306. csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
  307. }
  308. /*
  309. * csi2_timing_config - CSI2 timing configuration.
  310. * @timing: csi2_timing_cfg structure
  311. */
  312. static void csi2_timing_config(struct isp_device *isp,
  313. struct isp_csi2_device *csi2,
  314. struct isp_csi2_timing_cfg *timing)
  315. {
  316. u32 reg;
  317. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
  318. if (timing->force_rx_mode)
  319. reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
  320. else
  321. reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
  322. if (timing->stop_state_16x)
  323. reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
  324. else
  325. reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
  326. if (timing->stop_state_4x)
  327. reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
  328. else
  329. reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
  330. reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
  331. reg |= timing->stop_state_counter <<
  332. ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
  333. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
  334. }
  335. /*
  336. * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
  337. * @enable: Enable/disable CSI2 Context interrupts
  338. */
  339. static void csi2_irq_ctx_set(struct isp_device *isp,
  340. struct isp_csi2_device *csi2, int enable)
  341. {
  342. int i;
  343. for (i = 0; i < 8; i++) {
  344. isp_reg_writel(isp, ISPCSI2_CTX_IRQSTATUS_FE_IRQ, csi2->regs1,
  345. ISPCSI2_CTX_IRQSTATUS(i));
  346. if (enable)
  347. isp_reg_set(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
  348. ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
  349. else
  350. isp_reg_clr(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
  351. ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
  352. }
  353. }
  354. /*
  355. * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
  356. * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
  357. */
  358. static void csi2_irq_complexio1_set(struct isp_device *isp,
  359. struct isp_csi2_device *csi2, int enable)
  360. {
  361. u32 reg;
  362. reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
  363. ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER |
  364. ISPCSI2_PHY_IRQENABLE_STATEULPM5 |
  365. ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 |
  366. ISPCSI2_PHY_IRQENABLE_ERRESC5 |
  367. ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 |
  368. ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 |
  369. ISPCSI2_PHY_IRQENABLE_STATEULPM4 |
  370. ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 |
  371. ISPCSI2_PHY_IRQENABLE_ERRESC4 |
  372. ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 |
  373. ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 |
  374. ISPCSI2_PHY_IRQENABLE_STATEULPM3 |
  375. ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 |
  376. ISPCSI2_PHY_IRQENABLE_ERRESC3 |
  377. ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 |
  378. ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 |
  379. ISPCSI2_PHY_IRQENABLE_STATEULPM2 |
  380. ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 |
  381. ISPCSI2_PHY_IRQENABLE_ERRESC2 |
  382. ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 |
  383. ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 |
  384. ISPCSI2_PHY_IRQENABLE_STATEULPM1 |
  385. ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 |
  386. ISPCSI2_PHY_IRQENABLE_ERRESC1 |
  387. ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 |
  388. ISPCSI2_PHY_IRQENABLE_ERRSOTHS1;
  389. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
  390. if (enable)
  391. reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
  392. else
  393. reg = 0;
  394. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
  395. }
  396. /*
  397. * csi2_irq_status_set - Enables CSI2 Status IRQs.
  398. * @enable: Enable/disable CSI2 Status interrupts
  399. */
  400. static void csi2_irq_status_set(struct isp_device *isp,
  401. struct isp_csi2_device *csi2, int enable)
  402. {
  403. u32 reg;
  404. reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
  405. ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
  406. ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
  407. ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
  408. ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
  409. ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
  410. ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
  411. ISPCSI2_IRQSTATUS_CONTEXT(0);
  412. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
  413. if (enable)
  414. reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
  415. else
  416. reg = 0;
  417. isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
  418. }
  419. /*
  420. * omap3isp_csi2_reset - Resets the CSI2 module.
  421. *
  422. * Must be called with the phy lock held.
  423. *
  424. * Returns 0 if successful, or -EBUSY if power command didn't respond.
  425. */
  426. int omap3isp_csi2_reset(struct isp_csi2_device *csi2)
  427. {
  428. struct isp_device *isp = csi2->isp;
  429. u8 soft_reset_retries = 0;
  430. u32 reg;
  431. int i;
  432. if (!csi2->available)
  433. return -ENODEV;
  434. if (csi2->phy->entity)
  435. return -EBUSY;
  436. isp_reg_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
  437. ISPCSI2_SYSCONFIG_SOFT_RESET);
  438. do {
  439. reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
  440. ISPCSI2_SYSSTATUS_RESET_DONE;
  441. if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
  442. break;
  443. soft_reset_retries++;
  444. if (soft_reset_retries < 5)
  445. udelay(100);
  446. } while (soft_reset_retries < 5);
  447. if (soft_reset_retries == 5) {
  448. dev_err(isp->dev, "CSI2: Soft reset try count exceeded!\n");
  449. return -EBUSY;
  450. }
  451. if (isp->revision == ISP_REVISION_15_0)
  452. isp_reg_set(isp, csi2->regs1, ISPCSI2_PHY_CFG,
  453. ISPCSI2_PHY_CFG_RESET_CTRL);
  454. i = 100;
  455. do {
  456. reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
  457. & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK;
  458. if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)
  459. break;
  460. udelay(100);
  461. } while (--i > 0);
  462. if (i == 0) {
  463. dev_err(isp->dev,
  464. "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
  465. return -EBUSY;
  466. }
  467. if (isp->autoidle)
  468. isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
  469. ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
  470. ISPCSI2_SYSCONFIG_AUTO_IDLE,
  471. ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART |
  472. ((isp->revision == ISP_REVISION_15_0) ?
  473. ISPCSI2_SYSCONFIG_AUTO_IDLE : 0));
  474. else
  475. isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
  476. ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
  477. ISPCSI2_SYSCONFIG_AUTO_IDLE,
  478. ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO);
  479. return 0;
  480. }
  481. static int csi2_configure(struct isp_csi2_device *csi2)
  482. {
  483. struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
  484. const struct isp_bus_cfg *buscfg;
  485. struct isp_device *isp = csi2->isp;
  486. struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
  487. struct v4l2_subdev *sensor;
  488. struct media_pad *pad;
  489. /*
  490. * CSI2 fields that can be updated while the context has
  491. * been enabled or the interface has been enabled are not
  492. * updated dynamically currently. So we do not allow to
  493. * reconfigure if either has been enabled
  494. */
  495. if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
  496. return -EBUSY;
  497. pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
  498. sensor = media_entity_to_v4l2_subdev(pad->entity);
  499. buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
  500. csi2->frame_skip = 0;
  501. v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
  502. csi2->ctrl.vp_out_ctrl =
  503. clamp_t(unsigned int, pipe->l3_ick / pipe->external_rate - 1,
  504. 1, 3);
  505. dev_dbg(isp->dev, "%s: l3_ick %lu, external_rate %u, vp_out_ctrl %u\n",
  506. __func__, pipe->l3_ick, pipe->external_rate,
  507. csi2->ctrl.vp_out_ctrl);
  508. csi2->ctrl.frame_mode = ISP_CSI2_FRAME_IMMEDIATE;
  509. csi2->ctrl.ecc_enable = buscfg->bus.csi2.crc;
  510. timing->ionum = 1;
  511. timing->force_rx_mode = 1;
  512. timing->stop_state_16x = 1;
  513. timing->stop_state_4x = 1;
  514. timing->stop_state_counter = 0x1FF;
  515. /*
  516. * The CSI2 receiver can't do any format conversion except DPCM
  517. * decompression, so every set_format call configures both pads
  518. * and enables DPCM decompression as a special case:
  519. */
  520. if (csi2->formats[CSI2_PAD_SINK].code !=
  521. csi2->formats[CSI2_PAD_SOURCE].code)
  522. csi2->dpcm_decompress = true;
  523. else
  524. csi2->dpcm_decompress = false;
  525. csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
  526. if (csi2->video_out.bpl_padding == 0)
  527. csi2->contexts[0].data_offset = 0;
  528. else
  529. csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
  530. /*
  531. * Enable end of frame and end of line signals generation for
  532. * context 0. These signals are generated from CSI2 receiver to
  533. * qualify the last pixel of a frame and the last pixel of a line.
  534. * Without enabling the signals CSI2 receiver writes data to memory
  535. * beyond buffer size and/or data line offset is not handled correctly.
  536. */
  537. csi2->contexts[0].eof_enabled = 1;
  538. csi2->contexts[0].eol_enabled = 1;
  539. csi2_irq_complexio1_set(isp, csi2, 1);
  540. csi2_irq_ctx_set(isp, csi2, 1);
  541. csi2_irq_status_set(isp, csi2, 1);
  542. /* Set configuration (timings, format and links) */
  543. csi2_timing_config(isp, csi2, timing);
  544. csi2_recv_config(isp, csi2, &csi2->ctrl);
  545. csi2_ctx_config(isp, csi2, &csi2->contexts[0]);
  546. return 0;
  547. }
  548. /*
  549. * csi2_print_status - Prints CSI2 debug information.
  550. */
  551. #define CSI2_PRINT_REGISTER(isp, regs, name)\
  552. dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
  553. isp_reg_readl(isp, regs, ISPCSI2_##name))
  554. static void csi2_print_status(struct isp_csi2_device *csi2)
  555. {
  556. struct isp_device *isp = csi2->isp;
  557. if (!csi2->available)
  558. return;
  559. dev_dbg(isp->dev, "-------------CSI2 Register dump-------------\n");
  560. CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSCONFIG);
  561. CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSSTATUS);
  562. CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQENABLE);
  563. CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQSTATUS);
  564. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTRL);
  565. CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_H);
  566. CSI2_PRINT_REGISTER(isp, csi2->regs1, GNQ);
  567. CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_CFG);
  568. CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQSTATUS);
  569. CSI2_PRINT_REGISTER(isp, csi2->regs1, SHORT_PACKET);
  570. CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQENABLE);
  571. CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_P);
  572. CSI2_PRINT_REGISTER(isp, csi2->regs1, TIMING);
  573. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL1(0));
  574. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL2(0));
  575. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_OFST(0));
  576. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PING_ADDR(0));
  577. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PONG_ADDR(0));
  578. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQENABLE(0));
  579. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQSTATUS(0));
  580. CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL3(0));
  581. dev_dbg(isp->dev, "--------------------------------------------\n");
  582. }
  583. /* -----------------------------------------------------------------------------
  584. * Interrupt handling
  585. */
  586. /*
  587. * csi2_isr_buffer - Does buffer handling at end-of-frame
  588. * when writing to memory.
  589. */
  590. static void csi2_isr_buffer(struct isp_csi2_device *csi2)
  591. {
  592. struct isp_device *isp = csi2->isp;
  593. struct isp_buffer *buffer;
  594. csi2_ctx_enable(isp, csi2, 0, 0);
  595. buffer = omap3isp_video_buffer_next(&csi2->video_out);
  596. /*
  597. * Let video queue operation restart engine if there is an underrun
  598. * condition.
  599. */
  600. if (buffer == NULL)
  601. return;
  602. csi2_set_outaddr(csi2, buffer->dma);
  603. csi2_ctx_enable(isp, csi2, 0, 1);
  604. }
  605. static void csi2_isr_ctx(struct isp_csi2_device *csi2,
  606. struct isp_csi2_ctx_cfg *ctx)
  607. {
  608. struct isp_device *isp = csi2->isp;
  609. unsigned int n = ctx->ctxnum;
  610. u32 status;
  611. status = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
  612. isp_reg_writel(isp, status, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
  613. if (!(status & ISPCSI2_CTX_IRQSTATUS_FE_IRQ))
  614. return;
  615. /* Skip interrupts until we reach the frame skip count. The CSI2 will be
  616. * automatically disabled, as the frame skip count has been programmed
  617. * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
  618. *
  619. * It would have been nice to rely on the FRAME_NUMBER interrupt instead
  620. * but it turned out that the interrupt is only generated when the CSI2
  621. * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
  622. * correctly and reaches 0 when data is forwarded to the video port only
  623. * but no interrupt arrives). Maybe a CSI2 hardware bug.
  624. */
  625. if (csi2->frame_skip) {
  626. csi2->frame_skip--;
  627. if (csi2->frame_skip == 0) {
  628. ctx->format_id = csi2_ctx_map_format(csi2);
  629. csi2_ctx_config(isp, csi2, ctx);
  630. csi2_ctx_enable(isp, csi2, n, 1);
  631. }
  632. return;
  633. }
  634. if (csi2->output & CSI2_OUTPUT_MEMORY)
  635. csi2_isr_buffer(csi2);
  636. }
  637. /*
  638. * omap3isp_csi2_isr - CSI2 interrupt handling.
  639. */
  640. void omap3isp_csi2_isr(struct isp_csi2_device *csi2)
  641. {
  642. struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
  643. u32 csi2_irqstatus, cpxio1_irqstatus;
  644. struct isp_device *isp = csi2->isp;
  645. if (!csi2->available)
  646. return;
  647. csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS);
  648. isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS);
  649. /* Failure Cases */
  650. if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
  651. cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1,
  652. ISPCSI2_PHY_IRQSTATUS);
  653. isp_reg_writel(isp, cpxio1_irqstatus,
  654. csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
  655. dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ %x\n",
  656. cpxio1_irqstatus);
  657. pipe->error = true;
  658. }
  659. if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
  660. ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
  661. ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
  662. ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
  663. ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) {
  664. dev_dbg(isp->dev,
  665. "CSI2 Err: OCP:%d, Short_pack:%d, ECC:%d, CPXIO2:%d, FIFO_OVF:%d,\n",
  666. (csi2_irqstatus &
  667. ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0,
  668. (csi2_irqstatus &
  669. ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0,
  670. (csi2_irqstatus &
  671. ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0,
  672. (csi2_irqstatus &
  673. ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0,
  674. (csi2_irqstatus &
  675. ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0);
  676. pipe->error = true;
  677. }
  678. if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
  679. return;
  680. /* Successful cases */
  681. if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0))
  682. csi2_isr_ctx(csi2, &csi2->contexts[0]);
  683. if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
  684. dev_dbg(isp->dev, "CSI2: ECC correction done\n");
  685. }
  686. /* -----------------------------------------------------------------------------
  687. * ISP video operations
  688. */
  689. /*
  690. * csi2_queue - Queues the first buffer when using memory output
  691. * @video: The video node
  692. * @buffer: buffer to queue
  693. */
  694. static int csi2_queue(struct isp_video *video, struct isp_buffer *buffer)
  695. {
  696. struct isp_device *isp = video->isp;
  697. struct isp_csi2_device *csi2 = &isp->isp_csi2a;
  698. csi2_set_outaddr(csi2, buffer->dma);
  699. /*
  700. * If streaming was enabled before there was a buffer queued
  701. * or underrun happened in the ISR, the hardware was not enabled
  702. * and DMA queue flag ISP_VIDEO_DMAQUEUE_UNDERRUN is still set.
  703. * Enable it now.
  704. */
  705. if (csi2->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
  706. /* Enable / disable context 0 and IRQs */
  707. csi2_if_enable(isp, csi2, 1);
  708. csi2_ctx_enable(isp, csi2, 0, 1);
  709. isp_video_dmaqueue_flags_clr(&csi2->video_out);
  710. }
  711. return 0;
  712. }
  713. static const struct isp_video_operations csi2_ispvideo_ops = {
  714. .queue = csi2_queue,
  715. };
  716. /* -----------------------------------------------------------------------------
  717. * V4L2 subdev operations
  718. */
  719. static struct v4l2_mbus_framefmt *
  720. __csi2_get_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
  721. unsigned int pad, enum v4l2_subdev_format_whence which)
  722. {
  723. if (which == V4L2_SUBDEV_FORMAT_TRY)
  724. return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
  725. else
  726. return &csi2->formats[pad];
  727. }
  728. static void
  729. csi2_try_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
  730. unsigned int pad, struct v4l2_mbus_framefmt *fmt,
  731. enum v4l2_subdev_format_whence which)
  732. {
  733. u32 pixelcode;
  734. struct v4l2_mbus_framefmt *format;
  735. const struct isp_format_info *info;
  736. unsigned int i;
  737. switch (pad) {
  738. case CSI2_PAD_SINK:
  739. /* Clamp the width and height to valid range (1-8191). */
  740. for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
  741. if (fmt->code == csi2_input_fmts[i])
  742. break;
  743. }
  744. /* If not found, use SGRBG10 as default */
  745. if (i >= ARRAY_SIZE(csi2_input_fmts))
  746. fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  747. fmt->width = clamp_t(u32, fmt->width, 1, 8191);
  748. fmt->height = clamp_t(u32, fmt->height, 1, 8191);
  749. break;
  750. case CSI2_PAD_SOURCE:
  751. /* Source format same as sink format, except for DPCM
  752. * compression.
  753. */
  754. pixelcode = fmt->code;
  755. format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
  756. memcpy(fmt, format, sizeof(*fmt));
  757. /*
  758. * Only Allow DPCM decompression, and check that the
  759. * pattern is preserved
  760. */
  761. info = omap3isp_video_format_info(fmt->code);
  762. if (info->uncompressed == pixelcode)
  763. fmt->code = pixelcode;
  764. break;
  765. }
  766. /* RGB, non-interlaced */
  767. fmt->colorspace = V4L2_COLORSPACE_SRGB;
  768. fmt->field = V4L2_FIELD_NONE;
  769. }
  770. /*
  771. * csi2_enum_mbus_code - Handle pixel format enumeration
  772. * @sd : pointer to v4l2 subdev structure
  773. * @cfg: V4L2 subdev pad configuration
  774. * @code : pointer to v4l2_subdev_mbus_code_enum structure
  775. * return -EINVAL or zero on success
  776. */
  777. static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
  778. struct v4l2_subdev_pad_config *cfg,
  779. struct v4l2_subdev_mbus_code_enum *code)
  780. {
  781. struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
  782. struct v4l2_mbus_framefmt *format;
  783. const struct isp_format_info *info;
  784. if (code->pad == CSI2_PAD_SINK) {
  785. if (code->index >= ARRAY_SIZE(csi2_input_fmts))
  786. return -EINVAL;
  787. code->code = csi2_input_fmts[code->index];
  788. } else {
  789. format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
  790. code->which);
  791. switch (code->index) {
  792. case 0:
  793. /* Passthrough sink pad code */
  794. code->code = format->code;
  795. break;
  796. case 1:
  797. /* Uncompressed code */
  798. info = omap3isp_video_format_info(format->code);
  799. if (info->uncompressed == format->code)
  800. return -EINVAL;
  801. code->code = info->uncompressed;
  802. break;
  803. default:
  804. return -EINVAL;
  805. }
  806. }
  807. return 0;
  808. }
  809. static int csi2_enum_frame_size(struct v4l2_subdev *sd,
  810. struct v4l2_subdev_pad_config *cfg,
  811. struct v4l2_subdev_frame_size_enum *fse)
  812. {
  813. struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
  814. struct v4l2_mbus_framefmt format;
  815. if (fse->index != 0)
  816. return -EINVAL;
  817. format.code = fse->code;
  818. format.width = 1;
  819. format.height = 1;
  820. csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
  821. fse->min_width = format.width;
  822. fse->min_height = format.height;
  823. if (format.code != fse->code)
  824. return -EINVAL;
  825. format.code = fse->code;
  826. format.width = -1;
  827. format.height = -1;
  828. csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
  829. fse->max_width = format.width;
  830. fse->max_height = format.height;
  831. return 0;
  832. }
  833. /*
  834. * csi2_get_format - Handle get format by pads subdev method
  835. * @sd : pointer to v4l2 subdev structure
  836. * @cfg: V4L2 subdev pad configuration
  837. * @fmt: pointer to v4l2 subdev format structure
  838. * return -EINVAL or zero on success
  839. */
  840. static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
  841. struct v4l2_subdev_format *fmt)
  842. {
  843. struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
  844. struct v4l2_mbus_framefmt *format;
  845. format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
  846. if (format == NULL)
  847. return -EINVAL;
  848. fmt->format = *format;
  849. return 0;
  850. }
  851. /*
  852. * csi2_set_format - Handle set format by pads subdev method
  853. * @sd : pointer to v4l2 subdev structure
  854. * @cfg: V4L2 subdev pad configuration
  855. * @fmt: pointer to v4l2 subdev format structure
  856. * return -EINVAL or zero on success
  857. */
  858. static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
  859. struct v4l2_subdev_format *fmt)
  860. {
  861. struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
  862. struct v4l2_mbus_framefmt *format;
  863. format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
  864. if (format == NULL)
  865. return -EINVAL;
  866. csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
  867. *format = fmt->format;
  868. /* Propagate the format from sink to source */
  869. if (fmt->pad == CSI2_PAD_SINK) {
  870. format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
  871. fmt->which);
  872. *format = fmt->format;
  873. csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
  874. }
  875. return 0;
  876. }
  877. /*
  878. * csi2_init_formats - Initialize formats on all pads
  879. * @sd: ISP CSI2 V4L2 subdevice
  880. * @fh: V4L2 subdev file handle
  881. *
  882. * Initialize all pad formats with default values. If fh is not NULL, try
  883. * formats are initialized on the file handle. Otherwise active formats are
  884. * initialized on the device.
  885. */
  886. static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  887. {
  888. struct v4l2_subdev_format format;
  889. memset(&format, 0, sizeof(format));
  890. format.pad = CSI2_PAD_SINK;
  891. format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
  892. format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  893. format.format.width = 4096;
  894. format.format.height = 4096;
  895. csi2_set_format(sd, fh ? fh->pad : NULL, &format);
  896. return 0;
  897. }
  898. /*
  899. * csi2_set_stream - Enable/Disable streaming on the CSI2 module
  900. * @sd: ISP CSI2 V4L2 subdevice
  901. * @enable: ISP pipeline stream state
  902. *
  903. * Return 0 on success or a negative error code otherwise.
  904. */
  905. static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
  906. {
  907. struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
  908. struct isp_device *isp = csi2->isp;
  909. struct isp_video *video_out = &csi2->video_out;
  910. switch (enable) {
  911. case ISP_PIPELINE_STREAM_CONTINUOUS:
  912. if (omap3isp_csiphy_acquire(csi2->phy, &sd->entity) < 0)
  913. return -ENODEV;
  914. if (csi2->output & CSI2_OUTPUT_MEMORY)
  915. omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
  916. csi2_configure(csi2);
  917. csi2_print_status(csi2);
  918. /*
  919. * When outputting to memory with no buffer available, let the
  920. * buffer queue handler start the hardware. A DMA queue flag
  921. * ISP_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
  922. * a buffer available.
  923. */
  924. if (csi2->output & CSI2_OUTPUT_MEMORY &&
  925. !(video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED))
  926. break;
  927. /* Enable context 0 and IRQs */
  928. atomic_set(&csi2->stopping, 0);
  929. csi2_ctx_enable(isp, csi2, 0, 1);
  930. csi2_if_enable(isp, csi2, 1);
  931. isp_video_dmaqueue_flags_clr(video_out);
  932. break;
  933. case ISP_PIPELINE_STREAM_STOPPED:
  934. if (csi2->state == ISP_PIPELINE_STREAM_STOPPED)
  935. return 0;
  936. if (omap3isp_module_sync_idle(&sd->entity, &csi2->wait,
  937. &csi2->stopping))
  938. dev_dbg(isp->dev, "%s: module stop timeout.\n",
  939. sd->name);
  940. csi2_ctx_enable(isp, csi2, 0, 0);
  941. csi2_if_enable(isp, csi2, 0);
  942. csi2_irq_ctx_set(isp, csi2, 0);
  943. omap3isp_csiphy_release(csi2->phy);
  944. isp_video_dmaqueue_flags_clr(video_out);
  945. omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
  946. break;
  947. }
  948. csi2->state = enable;
  949. return 0;
  950. }
  951. /* subdev video operations */
  952. static const struct v4l2_subdev_video_ops csi2_video_ops = {
  953. .s_stream = csi2_set_stream,
  954. };
  955. /* subdev pad operations */
  956. static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
  957. .enum_mbus_code = csi2_enum_mbus_code,
  958. .enum_frame_size = csi2_enum_frame_size,
  959. .get_fmt = csi2_get_format,
  960. .set_fmt = csi2_set_format,
  961. };
  962. /* subdev operations */
  963. static const struct v4l2_subdev_ops csi2_ops = {
  964. .video = &csi2_video_ops,
  965. .pad = &csi2_pad_ops,
  966. };
  967. /* subdev internal operations */
  968. static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
  969. .open = csi2_init_formats,
  970. };
  971. /* -----------------------------------------------------------------------------
  972. * Media entity operations
  973. */
  974. /*
  975. * csi2_link_setup - Setup CSI2 connections.
  976. * @entity : Pointer to media entity structure
  977. * @local : Pointer to local pad array
  978. * @remote : Pointer to remote pad array
  979. * @flags : Link flags
  980. * return -EINVAL or zero on success
  981. */
  982. static int csi2_link_setup(struct media_entity *entity,
  983. const struct media_pad *local,
  984. const struct media_pad *remote, u32 flags)
  985. {
  986. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  987. struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
  988. struct isp_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
  989. unsigned int index = local->index;
  990. /*
  991. * The ISP core doesn't support pipelines with multiple video outputs.
  992. * Revisit this when it will be implemented, and return -EBUSY for now.
  993. */
  994. /* FIXME: this is actually a hack! */
  995. if (is_media_entity_v4l2_subdev(remote->entity))
  996. index |= 2 << 16;
  997. switch (index) {
  998. case CSI2_PAD_SOURCE:
  999. if (flags & MEDIA_LNK_FL_ENABLED) {
  1000. if (csi2->output & ~CSI2_OUTPUT_MEMORY)
  1001. return -EBUSY;
  1002. csi2->output |= CSI2_OUTPUT_MEMORY;
  1003. } else {
  1004. csi2->output &= ~CSI2_OUTPUT_MEMORY;
  1005. }
  1006. break;
  1007. case CSI2_PAD_SOURCE | 2 << 16:
  1008. if (flags & MEDIA_LNK_FL_ENABLED) {
  1009. if (csi2->output & ~CSI2_OUTPUT_CCDC)
  1010. return -EBUSY;
  1011. csi2->output |= CSI2_OUTPUT_CCDC;
  1012. } else {
  1013. csi2->output &= ~CSI2_OUTPUT_CCDC;
  1014. }
  1015. break;
  1016. default:
  1017. /* Link from camera to CSI2 is fixed... */
  1018. return -EINVAL;
  1019. }
  1020. ctrl->vp_only_enable =
  1021. (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
  1022. ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_CCDC);
  1023. return 0;
  1024. }
  1025. /* media operations */
  1026. static const struct media_entity_operations csi2_media_ops = {
  1027. .link_setup = csi2_link_setup,
  1028. .link_validate = v4l2_subdev_link_validate,
  1029. };
  1030. void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2)
  1031. {
  1032. v4l2_device_unregister_subdev(&csi2->subdev);
  1033. omap3isp_video_unregister(&csi2->video_out);
  1034. }
  1035. int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
  1036. struct v4l2_device *vdev)
  1037. {
  1038. int ret;
  1039. /* Register the subdev and video nodes. */
  1040. csi2->subdev.dev = vdev->mdev->dev;
  1041. ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
  1042. if (ret < 0)
  1043. goto error;
  1044. ret = omap3isp_video_register(&csi2->video_out, vdev);
  1045. if (ret < 0)
  1046. goto error;
  1047. return 0;
  1048. error:
  1049. omap3isp_csi2_unregister_entities(csi2);
  1050. return ret;
  1051. }
  1052. /* -----------------------------------------------------------------------------
  1053. * ISP CSI2 initialisation and cleanup
  1054. */
  1055. /*
  1056. * csi2_init_entities - Initialize subdev and media entity.
  1057. * @csi2: Pointer to csi2 structure.
  1058. * return -ENOMEM or zero on success
  1059. */
  1060. static int csi2_init_entities(struct isp_csi2_device *csi2)
  1061. {
  1062. struct v4l2_subdev *sd = &csi2->subdev;
  1063. struct media_pad *pads = csi2->pads;
  1064. struct media_entity *me = &sd->entity;
  1065. int ret;
  1066. v4l2_subdev_init(sd, &csi2_ops);
  1067. sd->internal_ops = &csi2_internal_ops;
  1068. strlcpy(sd->name, "OMAP3 ISP CSI2a", sizeof(sd->name));
  1069. sd->grp_id = 1 << 16; /* group ID for isp subdevs */
  1070. v4l2_set_subdevdata(sd, csi2);
  1071. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1072. pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
  1073. pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
  1074. | MEDIA_PAD_FL_MUST_CONNECT;
  1075. me->ops = &csi2_media_ops;
  1076. ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
  1077. if (ret < 0)
  1078. return ret;
  1079. csi2_init_formats(sd, NULL);
  1080. /* Video device node */
  1081. csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1082. csi2->video_out.ops = &csi2_ispvideo_ops;
  1083. csi2->video_out.bpl_alignment = 32;
  1084. csi2->video_out.bpl_zero_padding = 1;
  1085. csi2->video_out.bpl_max = 0x1ffe0;
  1086. csi2->video_out.isp = csi2->isp;
  1087. csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
  1088. ret = omap3isp_video_init(&csi2->video_out, "CSI2a");
  1089. if (ret < 0)
  1090. goto error_video;
  1091. return 0;
  1092. error_video:
  1093. media_entity_cleanup(&csi2->subdev.entity);
  1094. return ret;
  1095. }
  1096. /*
  1097. * omap3isp_csi2_init - Routine for module driver init
  1098. */
  1099. int omap3isp_csi2_init(struct isp_device *isp)
  1100. {
  1101. struct isp_csi2_device *csi2a = &isp->isp_csi2a;
  1102. struct isp_csi2_device *csi2c = &isp->isp_csi2c;
  1103. int ret;
  1104. csi2a->isp = isp;
  1105. csi2a->available = 1;
  1106. csi2a->regs1 = OMAP3_ISP_IOMEM_CSI2A_REGS1;
  1107. csi2a->regs2 = OMAP3_ISP_IOMEM_CSI2A_REGS2;
  1108. csi2a->phy = &isp->isp_csiphy2;
  1109. csi2a->state = ISP_PIPELINE_STREAM_STOPPED;
  1110. init_waitqueue_head(&csi2a->wait);
  1111. ret = csi2_init_entities(csi2a);
  1112. if (ret < 0)
  1113. return ret;
  1114. if (isp->revision == ISP_REVISION_15_0) {
  1115. csi2c->isp = isp;
  1116. csi2c->available = 1;
  1117. csi2c->regs1 = OMAP3_ISP_IOMEM_CSI2C_REGS1;
  1118. csi2c->regs2 = OMAP3_ISP_IOMEM_CSI2C_REGS2;
  1119. csi2c->phy = &isp->isp_csiphy1;
  1120. csi2c->state = ISP_PIPELINE_STREAM_STOPPED;
  1121. init_waitqueue_head(&csi2c->wait);
  1122. }
  1123. return 0;
  1124. }
  1125. /*
  1126. * omap3isp_csi2_cleanup - Routine for module driver cleanup
  1127. */
  1128. void omap3isp_csi2_cleanup(struct isp_device *isp)
  1129. {
  1130. struct isp_csi2_device *csi2a = &isp->isp_csi2a;
  1131. omap3isp_video_cleanup(&csi2a->video_out);
  1132. media_entity_cleanup(&csi2a->subdev.entity);
  1133. }