ispreg.h 54 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521
  1. /*
  2. * ispreg.h
  3. *
  4. * TI OMAP3 ISP - Registers definitions
  5. *
  6. * Copyright (C) 2010 Nokia Corporation
  7. * Copyright (C) 2009 Texas Instruments, Inc
  8. *
  9. * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10. * Sakari Ailus <sakari.ailus@iki.fi>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #ifndef OMAP3_ISP_REG_H
  17. #define OMAP3_ISP_REG_H
  18. #define CM_CAM_MCLK_HZ 172800000 /* Hz */
  19. /* ISP module register offset */
  20. #define ISP_REVISION (0x000)
  21. #define ISP_SYSCONFIG (0x004)
  22. #define ISP_SYSSTATUS (0x008)
  23. #define ISP_IRQ0ENABLE (0x00C)
  24. #define ISP_IRQ0STATUS (0x010)
  25. #define ISP_IRQ1ENABLE (0x014)
  26. #define ISP_IRQ1STATUS (0x018)
  27. #define ISP_TCTRL_GRESET_LENGTH (0x030)
  28. #define ISP_TCTRL_PSTRB_REPLAY (0x034)
  29. #define ISP_CTRL (0x040)
  30. #define ISP_SECURE (0x044)
  31. #define ISP_TCTRL_CTRL (0x050)
  32. #define ISP_TCTRL_FRAME (0x054)
  33. #define ISP_TCTRL_PSTRB_DELAY (0x058)
  34. #define ISP_TCTRL_STRB_DELAY (0x05C)
  35. #define ISP_TCTRL_SHUT_DELAY (0x060)
  36. #define ISP_TCTRL_PSTRB_LENGTH (0x064)
  37. #define ISP_TCTRL_STRB_LENGTH (0x068)
  38. #define ISP_TCTRL_SHUT_LENGTH (0x06C)
  39. #define ISP_PING_PONG_ADDR (0x070)
  40. #define ISP_PING_PONG_MEM_RANGE (0x074)
  41. #define ISP_PING_PONG_BUF_SIZE (0x078)
  42. /* CCP2 receiver registers */
  43. #define ISPCCP2_REVISION (0x000)
  44. #define ISPCCP2_SYSCONFIG (0x004)
  45. #define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1)
  46. #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
  47. #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
  48. #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \
  49. (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  50. #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO \
  51. (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  52. #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \
  53. (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  54. #define ISPCCP2_SYSSTATUS (0x008)
  55. #define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0)
  56. #define ISPCCP2_LC01_IRQENABLE (0x00C)
  57. #define ISPCCP2_LC01_IRQSTATUS (0x010)
  58. #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11)
  59. #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10)
  60. #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9)
  61. #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8)
  62. #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7)
  63. #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5)
  64. #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4)
  65. #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3)
  66. #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2)
  67. #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1)
  68. #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0)
  69. #define ISPCCP2_LC23_IRQENABLE (0x014)
  70. #define ISPCCP2_LC23_IRQSTATUS (0x018)
  71. #define ISPCCP2_LCM_IRQENABLE (0x02C)
  72. #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0)
  73. #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1)
  74. #define ISPCCP2_LCM_IRQSTATUS (0x030)
  75. #define ISPCCP2_CTRL (0x040)
  76. #define ISPCCP2_CTRL_IF_EN (1 << 0)
  77. #define ISPCCP2_CTRL_PHY_SEL (1 << 1)
  78. #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
  79. #define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1)
  80. #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
  81. #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
  82. #define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2)
  83. #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
  84. #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2
  85. #define ISPCCP2_CTRL_MODE (1 << 4)
  86. #define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9)
  87. #define ISPCCP2_CTRL_INV (1 << 10)
  88. #define ISPCCP2_CTRL_INV_MASK 0x1
  89. #define ISPCCP2_CTRL_INV_SHIFT 10
  90. #define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11)
  91. #define ISPCCP2_CTRL_VP_CLK_POL (1 << 12)
  92. #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
  93. #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12
  94. #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
  95. #define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
  96. #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */
  97. #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */
  98. #define ISPCCP2_DBG (0x044)
  99. #define ISPCCP2_GNQ (0x048)
  100. #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
  101. #define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0)
  102. #define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19)
  103. #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
  104. #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2
  105. #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19
  106. #define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1)
  107. #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
  108. #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1
  109. #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
  110. #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 0x2
  111. #define ISPCCP2_LCx_CTRL_FORMAT_MASK 0x1f
  112. #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT 0x3
  113. #define ISPCCP2_LCx_CODE(x) ((0x054)+0x30*(x))
  114. #define ISPCCP2_LCx_STAT_START(x) ((0x058)+0x30*(x))
  115. #define ISPCCP2_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x))
  116. #define ISPCCP2_LCx_SOF_ADDR(x) ((0x060)+0x30*(x))
  117. #define ISPCCP2_LCx_EOF_ADDR(x) ((0x064)+0x30*(x))
  118. #define ISPCCP2_LCx_DAT_START(x) ((0x068)+0x30*(x))
  119. #define ISPCCP2_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x))
  120. #define ISPCCP2_LCx_DAT_MASK 0xFFF
  121. #define ISPCCP2_LCx_DAT_SHIFT 16
  122. #define ISPCCP2_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x))
  123. #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
  124. #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
  125. #define ISPCCP2_LCM_CTRL (0x1D0)
  126. #define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0)
  127. #define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2)
  128. #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2
  129. #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3
  130. #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
  131. #define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT 5
  132. #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK 0x7
  133. #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT 16
  134. #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
  135. #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20
  136. #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
  137. #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22)
  138. #define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23)
  139. #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24
  140. #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
  141. #define ISPCCP2_LCM_VSIZE (0x1D4)
  142. #define ISPCCP2_LCM_VSIZE_SHIFT 16
  143. #define ISPCCP2_LCM_HSIZE (0x1D8)
  144. #define ISPCCP2_LCM_HSIZE_SHIFT 16
  145. #define ISPCCP2_LCM_PREFETCH (0x1DC)
  146. #define ISPCCP2_LCM_PREFETCH_SHIFT 3
  147. #define ISPCCP2_LCM_SRC_ADDR (0x1E0)
  148. #define ISPCCP2_LCM_SRC_OFST (0x1E4)
  149. #define ISPCCP2_LCM_DST_ADDR (0x1E8)
  150. #define ISPCCP2_LCM_DST_OFST (0x1EC)
  151. /* CCDC module register offset */
  152. #define ISPCCDC_PID (0x000)
  153. #define ISPCCDC_PCR (0x004)
  154. #define ISPCCDC_SYN_MODE (0x008)
  155. #define ISPCCDC_HD_VD_WID (0x00C)
  156. #define ISPCCDC_PIX_LINES (0x010)
  157. #define ISPCCDC_HORZ_INFO (0x014)
  158. #define ISPCCDC_VERT_START (0x018)
  159. #define ISPCCDC_VERT_LINES (0x01C)
  160. #define ISPCCDC_CULLING (0x020)
  161. #define ISPCCDC_HSIZE_OFF (0x024)
  162. #define ISPCCDC_SDOFST (0x028)
  163. #define ISPCCDC_SDR_ADDR (0x02C)
  164. #define ISPCCDC_CLAMP (0x030)
  165. #define ISPCCDC_DCSUB (0x034)
  166. #define ISPCCDC_COLPTN (0x038)
  167. #define ISPCCDC_BLKCMP (0x03C)
  168. #define ISPCCDC_FPC (0x040)
  169. #define ISPCCDC_FPC_ADDR (0x044)
  170. #define ISPCCDC_VDINT (0x048)
  171. #define ISPCCDC_ALAW (0x04C)
  172. #define ISPCCDC_REC656IF (0x050)
  173. #define ISPCCDC_CFG (0x054)
  174. #define ISPCCDC_FMTCFG (0x058)
  175. #define ISPCCDC_FMT_HORZ (0x05C)
  176. #define ISPCCDC_FMT_VERT (0x060)
  177. #define ISPCCDC_FMT_ADDR0 (0x064)
  178. #define ISPCCDC_FMT_ADDR1 (0x068)
  179. #define ISPCCDC_FMT_ADDR2 (0x06C)
  180. #define ISPCCDC_FMT_ADDR3 (0x070)
  181. #define ISPCCDC_FMT_ADDR4 (0x074)
  182. #define ISPCCDC_FMT_ADDR5 (0x078)
  183. #define ISPCCDC_FMT_ADDR6 (0x07C)
  184. #define ISPCCDC_FMT_ADDR7 (0x080)
  185. #define ISPCCDC_PRGEVEN0 (0x084)
  186. #define ISPCCDC_PRGEVEN1 (0x088)
  187. #define ISPCCDC_PRGODD0 (0x08C)
  188. #define ISPCCDC_PRGODD1 (0x090)
  189. #define ISPCCDC_VP_OUT (0x094)
  190. #define ISPCCDC_LSC_CONFIG (0x098)
  191. #define ISPCCDC_LSC_INITIAL (0x09C)
  192. #define ISPCCDC_LSC_TABLE_BASE (0x0A0)
  193. #define ISPCCDC_LSC_TABLE_OFFSET (0x0A4)
  194. /* SBL */
  195. #define ISPSBL_PCR 0x4
  196. #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16)
  197. #define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17)
  198. #define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18)
  199. #define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19)
  200. #define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20)
  201. #define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21)
  202. #define ISPSBL_PCR_PRV_WBL_OVF (1 << 22)
  203. #define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23)
  204. #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24)
  205. #define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25)
  206. #define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26)
  207. #define ISPSBL_CCDC_WR_0 (0x028)
  208. #define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21)
  209. #define ISPSBL_CCDC_WR_1 (0x02C)
  210. #define ISPSBL_CCDC_WR_2 (0x030)
  211. #define ISPSBL_CCDC_WR_3 (0x034)
  212. #define ISPSBL_SDR_REQ_EXP 0xF8
  213. #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT 0
  214. #define ISPSBL_SDR_REQ_HIST_EXP_MASK (0x3FF)
  215. #define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT 10
  216. #define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
  217. #define ISPSBL_SDR_REQ_PRV_EXP_SHIFT 20
  218. #define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
  219. /* Histogram registers */
  220. #define ISPHIST_PID (0x000)
  221. #define ISPHIST_PCR (0x004)
  222. #define ISPHIST_CNT (0x008)
  223. #define ISPHIST_WB_GAIN (0x00C)
  224. #define ISPHIST_R0_HORZ (0x010)
  225. #define ISPHIST_R0_VERT (0x014)
  226. #define ISPHIST_R1_HORZ (0x018)
  227. #define ISPHIST_R1_VERT (0x01C)
  228. #define ISPHIST_R2_HORZ (0x020)
  229. #define ISPHIST_R2_VERT (0x024)
  230. #define ISPHIST_R3_HORZ (0x028)
  231. #define ISPHIST_R3_VERT (0x02C)
  232. #define ISPHIST_ADDR (0x030)
  233. #define ISPHIST_DATA (0x034)
  234. #define ISPHIST_RADD (0x038)
  235. #define ISPHIST_RADD_OFF (0x03C)
  236. #define ISPHIST_H_V_INFO (0x040)
  237. /* H3A module registers */
  238. #define ISPH3A_PID (0x000)
  239. #define ISPH3A_PCR (0x004)
  240. #define ISPH3A_AEWWIN1 (0x04C)
  241. #define ISPH3A_AEWINSTART (0x050)
  242. #define ISPH3A_AEWINBLK (0x054)
  243. #define ISPH3A_AEWSUBWIN (0x058)
  244. #define ISPH3A_AEWBUFST (0x05C)
  245. #define ISPH3A_AFPAX1 (0x008)
  246. #define ISPH3A_AFPAX2 (0x00C)
  247. #define ISPH3A_AFPAXSTART (0x010)
  248. #define ISPH3A_AFIIRSH (0x014)
  249. #define ISPH3A_AFBUFST (0x018)
  250. #define ISPH3A_AFCOEF010 (0x01C)
  251. #define ISPH3A_AFCOEF032 (0x020)
  252. #define ISPH3A_AFCOEF054 (0x024)
  253. #define ISPH3A_AFCOEF076 (0x028)
  254. #define ISPH3A_AFCOEF098 (0x02C)
  255. #define ISPH3A_AFCOEF0010 (0x030)
  256. #define ISPH3A_AFCOEF110 (0x034)
  257. #define ISPH3A_AFCOEF132 (0x038)
  258. #define ISPH3A_AFCOEF154 (0x03C)
  259. #define ISPH3A_AFCOEF176 (0x040)
  260. #define ISPH3A_AFCOEF198 (0x044)
  261. #define ISPH3A_AFCOEF1010 (0x048)
  262. #define ISPPRV_PCR (0x004)
  263. #define ISPPRV_HORZ_INFO (0x008)
  264. #define ISPPRV_VERT_INFO (0x00C)
  265. #define ISPPRV_RSDR_ADDR (0x010)
  266. #define ISPPRV_RADR_OFFSET (0x014)
  267. #define ISPPRV_DSDR_ADDR (0x018)
  268. #define ISPPRV_DRKF_OFFSET (0x01C)
  269. #define ISPPRV_WSDR_ADDR (0x020)
  270. #define ISPPRV_WADD_OFFSET (0x024)
  271. #define ISPPRV_AVE (0x028)
  272. #define ISPPRV_HMED (0x02C)
  273. #define ISPPRV_NF (0x030)
  274. #define ISPPRV_WB_DGAIN (0x034)
  275. #define ISPPRV_WBGAIN (0x038)
  276. #define ISPPRV_WBSEL (0x03C)
  277. #define ISPPRV_CFA (0x040)
  278. #define ISPPRV_BLKADJOFF (0x044)
  279. #define ISPPRV_RGB_MAT1 (0x048)
  280. #define ISPPRV_RGB_MAT2 (0x04C)
  281. #define ISPPRV_RGB_MAT3 (0x050)
  282. #define ISPPRV_RGB_MAT4 (0x054)
  283. #define ISPPRV_RGB_MAT5 (0x058)
  284. #define ISPPRV_RGB_OFF1 (0x05C)
  285. #define ISPPRV_RGB_OFF2 (0x060)
  286. #define ISPPRV_CSC0 (0x064)
  287. #define ISPPRV_CSC1 (0x068)
  288. #define ISPPRV_CSC2 (0x06C)
  289. #define ISPPRV_CSC_OFFSET (0x070)
  290. #define ISPPRV_CNT_BRT (0x074)
  291. #define ISPPRV_CSUP (0x078)
  292. #define ISPPRV_SETUP_YC (0x07C)
  293. #define ISPPRV_SET_TBL_ADDR (0x080)
  294. #define ISPPRV_SET_TBL_DATA (0x084)
  295. #define ISPPRV_CDC_THR0 (0x090)
  296. #define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4))
  297. #define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2)
  298. #define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3)
  299. #define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000
  300. #define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400
  301. #define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800
  302. #define ISPPRV_NF_TABLE_ADDR 0x0C00
  303. #define ISPPRV_YENH_TABLE_ADDR 0x1000
  304. #define ISPPRV_CFA_TABLE_ADDR 0x1400
  305. #define ISPRSZ_MIN_OUTPUT 64
  306. #define ISPRSZ_MAX_OUTPUT 3312
  307. /* Resizer module register offset */
  308. #define ISPRSZ_PID (0x000)
  309. #define ISPRSZ_PCR (0x004)
  310. #define ISPRSZ_CNT (0x008)
  311. #define ISPRSZ_OUT_SIZE (0x00C)
  312. #define ISPRSZ_IN_START (0x010)
  313. #define ISPRSZ_IN_SIZE (0x014)
  314. #define ISPRSZ_SDR_INADD (0x018)
  315. #define ISPRSZ_SDR_INOFF (0x01C)
  316. #define ISPRSZ_SDR_OUTADD (0x020)
  317. #define ISPRSZ_SDR_OUTOFF (0x024)
  318. #define ISPRSZ_HFILT10 (0x028)
  319. #define ISPRSZ_HFILT32 (0x02C)
  320. #define ISPRSZ_HFILT54 (0x030)
  321. #define ISPRSZ_HFILT76 (0x034)
  322. #define ISPRSZ_HFILT98 (0x038)
  323. #define ISPRSZ_HFILT1110 (0x03C)
  324. #define ISPRSZ_HFILT1312 (0x040)
  325. #define ISPRSZ_HFILT1514 (0x044)
  326. #define ISPRSZ_HFILT1716 (0x048)
  327. #define ISPRSZ_HFILT1918 (0x04C)
  328. #define ISPRSZ_HFILT2120 (0x050)
  329. #define ISPRSZ_HFILT2322 (0x054)
  330. #define ISPRSZ_HFILT2524 (0x058)
  331. #define ISPRSZ_HFILT2726 (0x05C)
  332. #define ISPRSZ_HFILT2928 (0x060)
  333. #define ISPRSZ_HFILT3130 (0x064)
  334. #define ISPRSZ_VFILT10 (0x068)
  335. #define ISPRSZ_VFILT32 (0x06C)
  336. #define ISPRSZ_VFILT54 (0x070)
  337. #define ISPRSZ_VFILT76 (0x074)
  338. #define ISPRSZ_VFILT98 (0x078)
  339. #define ISPRSZ_VFILT1110 (0x07C)
  340. #define ISPRSZ_VFILT1312 (0x080)
  341. #define ISPRSZ_VFILT1514 (0x084)
  342. #define ISPRSZ_VFILT1716 (0x088)
  343. #define ISPRSZ_VFILT1918 (0x08C)
  344. #define ISPRSZ_VFILT2120 (0x090)
  345. #define ISPRSZ_VFILT2322 (0x094)
  346. #define ISPRSZ_VFILT2524 (0x098)
  347. #define ISPRSZ_VFILT2726 (0x09C)
  348. #define ISPRSZ_VFILT2928 (0x0A0)
  349. #define ISPRSZ_VFILT3130 (0x0A4)
  350. #define ISPRSZ_YENH (0x0A8)
  351. #define ISP_INT_CLR 0xFF113F11
  352. #define ISPPRV_PCR_EN 1
  353. #define ISPPRV_PCR_BUSY (1 << 1)
  354. #define ISPPRV_PCR_SOURCE (1 << 2)
  355. #define ISPPRV_PCR_ONESHOT (1 << 3)
  356. #define ISPPRV_PCR_WIDTH (1 << 4)
  357. #define ISPPRV_PCR_INVALAW (1 << 5)
  358. #define ISPPRV_PCR_DRKFEN (1 << 6)
  359. #define ISPPRV_PCR_DRKFCAP (1 << 7)
  360. #define ISPPRV_PCR_HMEDEN (1 << 8)
  361. #define ISPPRV_PCR_NFEN (1 << 9)
  362. #define ISPPRV_PCR_CFAEN (1 << 10)
  363. #define ISPPRV_PCR_CFAFMT_SHIFT 11
  364. #define ISPPRV_PCR_CFAFMT_MASK 0x7800
  365. #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
  366. #define ISPPRV_PCR_CFAFMT_SONYVGA (1 << 11)
  367. #define ISPPRV_PCR_CFAFMT_RGBFOVEON (2 << 11)
  368. #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11)
  369. #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11)
  370. #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11)
  371. #define ISPPRV_PCR_YNENHEN (1 << 15)
  372. #define ISPPRV_PCR_SUPEN (1 << 16)
  373. #define ISPPRV_PCR_YCPOS_SHIFT 17
  374. #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
  375. #define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17)
  376. #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17)
  377. #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17)
  378. #define ISPPRV_PCR_RSZPORT (1 << 19)
  379. #define ISPPRV_PCR_SDRPORT (1 << 20)
  380. #define ISPPRV_PCR_SCOMP_EN (1 << 21)
  381. #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22)
  382. #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22)
  383. #define ISPPRV_PCR_GAMMA_BYPASS (1 << 26)
  384. #define ISPPRV_PCR_DCOREN (1 << 27)
  385. #define ISPPRV_PCR_DCCOUP (1 << 28)
  386. #define ISPPRV_PCR_DRK_FAIL (1 << 31)
  387. #define ISPPRV_HORZ_INFO_EPH_SHIFT 0
  388. #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
  389. #define ISPPRV_HORZ_INFO_SPH_SHIFT 16
  390. #define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0
  391. #define ISPPRV_VERT_INFO_ELV_SHIFT 0
  392. #define ISPPRV_VERT_INFO_ELV_MASK 0x3fff
  393. #define ISPPRV_VERT_INFO_SLV_SHIFT 16
  394. #define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0
  395. #define ISPPRV_AVE_EVENDIST_SHIFT 2
  396. #define ISPPRV_AVE_EVENDIST_1 0x0
  397. #define ISPPRV_AVE_EVENDIST_2 0x1
  398. #define ISPPRV_AVE_EVENDIST_3 0x2
  399. #define ISPPRV_AVE_EVENDIST_4 0x3
  400. #define ISPPRV_AVE_ODDDIST_SHIFT 4
  401. #define ISPPRV_AVE_ODDDIST_1 0x0
  402. #define ISPPRV_AVE_ODDDIST_2 0x1
  403. #define ISPPRV_AVE_ODDDIST_3 0x2
  404. #define ISPPRV_AVE_ODDDIST_4 0x3
  405. #define ISPPRV_HMED_THRESHOLD_SHIFT 0
  406. #define ISPPRV_HMED_EVENDIST (1 << 8)
  407. #define ISPPRV_HMED_ODDDIST (1 << 9)
  408. #define ISPPRV_WBGAIN_COEF0_SHIFT 0
  409. #define ISPPRV_WBGAIN_COEF1_SHIFT 8
  410. #define ISPPRV_WBGAIN_COEF2_SHIFT 16
  411. #define ISPPRV_WBGAIN_COEF3_SHIFT 24
  412. #define ISPPRV_WBSEL_COEF0 0x0
  413. #define ISPPRV_WBSEL_COEF1 0x1
  414. #define ISPPRV_WBSEL_COEF2 0x2
  415. #define ISPPRV_WBSEL_COEF3 0x3
  416. #define ISPPRV_WBSEL_N0_0_SHIFT 0
  417. #define ISPPRV_WBSEL_N0_1_SHIFT 2
  418. #define ISPPRV_WBSEL_N0_2_SHIFT 4
  419. #define ISPPRV_WBSEL_N0_3_SHIFT 6
  420. #define ISPPRV_WBSEL_N1_0_SHIFT 8
  421. #define ISPPRV_WBSEL_N1_1_SHIFT 10
  422. #define ISPPRV_WBSEL_N1_2_SHIFT 12
  423. #define ISPPRV_WBSEL_N1_3_SHIFT 14
  424. #define ISPPRV_WBSEL_N2_0_SHIFT 16
  425. #define ISPPRV_WBSEL_N2_1_SHIFT 18
  426. #define ISPPRV_WBSEL_N2_2_SHIFT 20
  427. #define ISPPRV_WBSEL_N2_3_SHIFT 22
  428. #define ISPPRV_WBSEL_N3_0_SHIFT 24
  429. #define ISPPRV_WBSEL_N3_1_SHIFT 26
  430. #define ISPPRV_WBSEL_N3_2_SHIFT 28
  431. #define ISPPRV_WBSEL_N3_3_SHIFT 30
  432. #define ISPPRV_CFA_GRADTH_HOR_SHIFT 0
  433. #define ISPPRV_CFA_GRADTH_VER_SHIFT 8
  434. #define ISPPRV_BLKADJOFF_B_SHIFT 0
  435. #define ISPPRV_BLKADJOFF_G_SHIFT 8
  436. #define ISPPRV_BLKADJOFF_R_SHIFT 16
  437. #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0
  438. #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT 16
  439. #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0
  440. #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT 16
  441. #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0
  442. #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT 16
  443. #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0
  444. #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT 16
  445. #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0
  446. #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0
  447. #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT 16
  448. #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0
  449. #define ISPPRV_CSC0_RY_SHIFT 0
  450. #define ISPPRV_CSC0_GY_SHIFT 10
  451. #define ISPPRV_CSC0_BY_SHIFT 20
  452. #define ISPPRV_CSC1_RCB_SHIFT 0
  453. #define ISPPRV_CSC1_GCB_SHIFT 10
  454. #define ISPPRV_CSC1_BCB_SHIFT 20
  455. #define ISPPRV_CSC2_RCR_SHIFT 0
  456. #define ISPPRV_CSC2_GCR_SHIFT 10
  457. #define ISPPRV_CSC2_BCR_SHIFT 20
  458. #define ISPPRV_CSC_OFFSET_CR_SHIFT 0
  459. #define ISPPRV_CSC_OFFSET_CB_SHIFT 8
  460. #define ISPPRV_CSC_OFFSET_Y_SHIFT 16
  461. #define ISPPRV_CNT_BRT_BRT_SHIFT 0
  462. #define ISPPRV_CNT_BRT_CNT_SHIFT 8
  463. #define ISPPRV_CONTRAST_MAX 0x10
  464. #define ISPPRV_CONTRAST_MIN 0xFF
  465. #define ISPPRV_BRIGHT_MIN 0x00
  466. #define ISPPRV_BRIGHT_MAX 0xFF
  467. #define ISPPRV_CSUP_CSUPG_SHIFT 0
  468. #define ISPPRV_CSUP_THRES_SHIFT 8
  469. #define ISPPRV_CSUP_HPYF_SHIFT 16
  470. #define ISPPRV_SETUP_YC_MINC_SHIFT 0
  471. #define ISPPRV_SETUP_YC_MAXC_SHIFT 8
  472. #define ISPPRV_SETUP_YC_MINY_SHIFT 16
  473. #define ISPPRV_SETUP_YC_MAXY_SHIFT 24
  474. #define ISPPRV_YC_MAX 0xFF
  475. #define ISPPRV_YC_MIN 0x0
  476. /* Define bit fields within selected registers */
  477. #define ISP_REVISION_SHIFT 0
  478. #define ISP_SYSCONFIG_AUTOIDLE (1 << 0)
  479. #define ISP_SYSCONFIG_SOFTRESET (1 << 1)
  480. #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12
  481. #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
  482. #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
  483. #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2
  484. #define ISP_SYSSTATUS_RESETDONE 0
  485. #define IRQ0ENABLE_CSIA_IRQ (1 << 0)
  486. #define IRQ0ENABLE_CSIC_IRQ (1 << 1)
  487. #define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3)
  488. #define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4)
  489. #define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5)
  490. #define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6)
  491. #define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7)
  492. #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \
  493. IRQ0ENABLE_CCP2_LC0_IRQ | \
  494. IRQ0ENABLE_CCP2_LC1_IRQ | \
  495. IRQ0ENABLE_CCP2_LC2_IRQ | \
  496. IRQ0ENABLE_CCP2_LC3_IRQ)
  497. #define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8)
  498. #define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9)
  499. #define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10)
  500. #define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11)
  501. #define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12)
  502. #define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13)
  503. #define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16)
  504. #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17)
  505. #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
  506. #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
  507. #define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20)
  508. #define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24)
  509. #define IRQ0ENABLE_OVF_IRQ (1 << 25)
  510. #define IRQ0ENABLE_PING_IRQ (1 << 26)
  511. #define IRQ0ENABLE_PONG_IRQ (1 << 27)
  512. #define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28)
  513. #define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29)
  514. #define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30)
  515. #define IRQ0ENABLE_HS_VS_IRQ (1 << 31)
  516. #define IRQ0STATUS_CSIA_IRQ (1 << 0)
  517. #define IRQ0STATUS_CSI2C_IRQ (1 << 1)
  518. #define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3)
  519. #define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4)
  520. #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \
  521. IRQ0STATUS_CCP2_LC0_IRQ)
  522. #define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5)
  523. #define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6)
  524. #define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7)
  525. #define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8)
  526. #define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9)
  527. #define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10)
  528. #define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11)
  529. #define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12)
  530. #define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13)
  531. #define IRQ0STATUS_HIST_DONE_IRQ (1 << 16)
  532. #define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17)
  533. #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
  534. #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
  535. #define IRQ0STATUS_PRV_DONE_IRQ (1 << 20)
  536. #define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24)
  537. #define IRQ0STATUS_OVF_IRQ (1 << 25)
  538. #define IRQ0STATUS_PING_IRQ (1 << 26)
  539. #define IRQ0STATUS_PONG_IRQ (1 << 27)
  540. #define IRQ0STATUS_MMU_ERR_IRQ (1 << 28)
  541. #define IRQ0STATUS_OCP_ERR_IRQ (1 << 29)
  542. #define IRQ0STATUS_SEC_ERR_IRQ (1 << 30)
  543. #define IRQ0STATUS_HS_VS_IRQ (1 << 31)
  544. #define TCTRL_GRESET_LEN 0
  545. #define TCTRL_PSTRB_REPLAY_DELAY 0
  546. #define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT 25
  547. #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0
  548. #define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1
  549. #define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2
  550. #define ISPCTRL_PAR_SER_CLK_SEL_CSIC 0x3
  551. #define ISPCTRL_PAR_SER_CLK_SEL_MASK 0x3
  552. #define ISPCTRL_PAR_BRIDGE_SHIFT 2
  553. #define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2)
  554. #define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2)
  555. #define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2)
  556. #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
  557. #define ISPCTRL_PAR_CLK_POL_SHIFT 4
  558. #define ISPCTRL_PAR_CLK_POL_INV (1 << 4)
  559. #define ISPCTRL_PING_PONG_EN (1 << 5)
  560. #define ISPCTRL_SHIFT_SHIFT 6
  561. #define ISPCTRL_SHIFT_0 (0x0 << 6)
  562. #define ISPCTRL_SHIFT_2 (0x1 << 6)
  563. #define ISPCTRL_SHIFT_4 (0x2 << 6)
  564. #define ISPCTRL_SHIFT_MASK (0x3 << 6)
  565. #define ISPCTRL_CCDC_CLK_EN (1 << 8)
  566. #define ISPCTRL_SCMP_CLK_EN (1 << 9)
  567. #define ISPCTRL_H3A_CLK_EN (1 << 10)
  568. #define ISPCTRL_HIST_CLK_EN (1 << 11)
  569. #define ISPCTRL_PREV_CLK_EN (1 << 12)
  570. #define ISPCTRL_RSZ_CLK_EN (1 << 13)
  571. #define ISPCTRL_SYNC_DETECT_SHIFT 14
  572. #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
  573. #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
  574. #define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
  575. #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
  576. #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
  577. #define ISPCTRL_CCDC_RAM_EN (1 << 16)
  578. #define ISPCTRL_PREV_RAM_EN (1 << 17)
  579. #define ISPCTRL_SBL_RD_RAM_EN (1 << 18)
  580. #define ISPCTRL_SBL_WR1_RAM_EN (1 << 19)
  581. #define ISPCTRL_SBL_WR0_RAM_EN (1 << 20)
  582. #define ISPCTRL_SBL_AUTOIDLE (1 << 21)
  583. #define ISPCTRL_SBL_SHARED_WPORTC (1 << 26)
  584. #define ISPCTRL_SBL_SHARED_RPORTA (1 << 27)
  585. #define ISPCTRL_SBL_SHARED_RPORTB (1 << 28)
  586. #define ISPCTRL_JPEG_FLUSH (1 << 30)
  587. #define ISPCTRL_CCDC_FLUSH (1 << 31)
  588. #define ISPSECURE_SECUREMODE 0
  589. #define ISPTCTRL_CTRL_DIV_LOW 0x0
  590. #define ISPTCTRL_CTRL_DIV_HIGH 0x1
  591. #define ISPTCTRL_CTRL_DIV_BYPASS 0x1F
  592. #define ISPTCTRL_CTRL_DIVA_SHIFT 0
  593. #define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
  594. #define ISPTCTRL_CTRL_DIVB_SHIFT 5
  595. #define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
  596. #define ISPTCTRL_CTRL_DIVC_SHIFT 10
  597. #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
  598. #define ISPTCTRL_CTRL_SHUTEN (1 << 21)
  599. #define ISPTCTRL_CTRL_PSTRBEN (1 << 22)
  600. #define ISPTCTRL_CTRL_STRBEN (1 << 23)
  601. #define ISPTCTRL_CTRL_SHUTPOL (1 << 24)
  602. #define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26)
  603. #define ISPTCTRL_CTRL_INSEL_SHIFT 27
  604. #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
  605. #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
  606. #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
  607. #define ISPTCTRL_CTRL_GRESETEn (1 << 29)
  608. #define ISPTCTRL_CTRL_GRESETPOL (1 << 30)
  609. #define ISPTCTRL_CTRL_GRESETDIR (1 << 31)
  610. #define ISPTCTRL_FRAME_SHUT_SHIFT 0
  611. #define ISPTCTRL_FRAME_PSTRB_SHIFT 6
  612. #define ISPTCTRL_FRAME_STRB_SHIFT 12
  613. #define ISPCCDC_PID_PREV_SHIFT 0
  614. #define ISPCCDC_PID_CID_SHIFT 8
  615. #define ISPCCDC_PID_TID_SHIFT 16
  616. #define ISPCCDC_PCR_EN 1
  617. #define ISPCCDC_PCR_BUSY (1 << 1)
  618. #define ISPCCDC_SYN_MODE_VDHDOUT 0x1
  619. #define ISPCCDC_SYN_MODE_FLDOUT (1 << 1)
  620. #define ISPCCDC_SYN_MODE_VDPOL (1 << 2)
  621. #define ISPCCDC_SYN_MODE_HDPOL (1 << 3)
  622. #define ISPCCDC_SYN_MODE_FLDPOL (1 << 4)
  623. #define ISPCCDC_SYN_MODE_EXWEN (1 << 5)
  624. #define ISPCCDC_SYN_MODE_DATAPOL (1 << 6)
  625. #define ISPCCDC_SYN_MODE_FLDMODE (1 << 7)
  626. #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
  627. #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
  628. #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
  629. #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
  630. #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
  631. #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
  632. #define ISPCCDC_SYN_MODE_PACK8 (1 << 11)
  633. #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12)
  634. #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
  635. #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12)
  636. #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12)
  637. #define ISPCCDC_SYN_MODE_LPF (1 << 14)
  638. #define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15)
  639. #define ISPCCDC_SYN_MODE_VDHDEN (1 << 16)
  640. #define ISPCCDC_SYN_MODE_WEN (1 << 17)
  641. #define ISPCCDC_SYN_MODE_VP2SDR (1 << 18)
  642. #define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19)
  643. #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
  644. #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
  645. #define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0
  646. #define ISPCCDC_PIX_LINES_PPLN_SHIFT 16
  647. #define ISPCCDC_HORZ_INFO_NPH_SHIFT 0
  648. #define ISPCCDC_HORZ_INFO_NPH_MASK 0x00007fff
  649. #define ISPCCDC_HORZ_INFO_SPH_SHIFT 16
  650. #define ISPCCDC_HORZ_INFO_SPH_MASK 0x7fff0000
  651. #define ISPCCDC_VERT_START_SLV1_SHIFT 0
  652. #define ISPCCDC_VERT_START_SLV0_SHIFT 16
  653. #define ISPCCDC_VERT_START_SLV0_MASK 0x7fff0000
  654. #define ISPCCDC_VERT_LINES_NLV_SHIFT 0
  655. #define ISPCCDC_VERT_LINES_NLV_MASK 0x00007fff
  656. #define ISPCCDC_CULLING_CULV_SHIFT 0
  657. #define ISPCCDC_CULLING_CULHODD_SHIFT 16
  658. #define ISPCCDC_CULLING_CULHEVN_SHIFT 24
  659. #define ISPCCDC_HSIZE_OFF_SHIFT 0
  660. #define ISPCCDC_SDOFST_FIINV (1 << 14)
  661. #define ISPCCDC_SDOFST_FOFST_SHIFT 12
  662. #define ISPCCDC_SDOFST_FOFST_MASK (3 << 12)
  663. #define ISPCCDC_SDOFST_LOFST3_SHIFT 0
  664. #define ISPCCDC_SDOFST_LOFST2_SHIFT 3
  665. #define ISPCCDC_SDOFST_LOFST1_SHIFT 6
  666. #define ISPCCDC_SDOFST_LOFST0_SHIFT 9
  667. #define ISPCCDC_CLAMP_OBGAIN_SHIFT 0
  668. #define ISPCCDC_CLAMP_OBST_SHIFT 10
  669. #define ISPCCDC_CLAMP_OBSLN_SHIFT 25
  670. #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28
  671. #define ISPCCDC_CLAMP_CLAMPEN (1 << 31)
  672. #define ISPCCDC_COLPTN_R_Ye 0x0
  673. #define ISPCCDC_COLPTN_Gr_Cy 0x1
  674. #define ISPCCDC_COLPTN_Gb_G 0x2
  675. #define ISPCCDC_COLPTN_B_Mg 0x3
  676. #define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0
  677. #define ISPCCDC_COLPTN_CP0PLC1_SHIFT 2
  678. #define ISPCCDC_COLPTN_CP0PLC2_SHIFT 4
  679. #define ISPCCDC_COLPTN_CP0PLC3_SHIFT 6
  680. #define ISPCCDC_COLPTN_CP1PLC0_SHIFT 8
  681. #define ISPCCDC_COLPTN_CP1PLC1_SHIFT 10
  682. #define ISPCCDC_COLPTN_CP1PLC2_SHIFT 12
  683. #define ISPCCDC_COLPTN_CP1PLC3_SHIFT 14
  684. #define ISPCCDC_COLPTN_CP2PLC0_SHIFT 16
  685. #define ISPCCDC_COLPTN_CP2PLC1_SHIFT 18
  686. #define ISPCCDC_COLPTN_CP2PLC2_SHIFT 20
  687. #define ISPCCDC_COLPTN_CP2PLC3_SHIFT 22
  688. #define ISPCCDC_COLPTN_CP3PLC0_SHIFT 24
  689. #define ISPCCDC_COLPTN_CP3PLC1_SHIFT 26
  690. #define ISPCCDC_COLPTN_CP3PLC2_SHIFT 28
  691. #define ISPCCDC_COLPTN_CP3PLC3_SHIFT 30
  692. #define ISPCCDC_BLKCMP_B_MG_SHIFT 0
  693. #define ISPCCDC_BLKCMP_GB_G_SHIFT 8
  694. #define ISPCCDC_BLKCMP_GR_CY_SHIFT 16
  695. #define ISPCCDC_BLKCMP_R_YE_SHIFT 24
  696. #define ISPCCDC_FPC_FPNUM_SHIFT 0
  697. #define ISPCCDC_FPC_FPCEN (1 << 15)
  698. #define ISPCCDC_FPC_FPERR (1 << 16)
  699. #define ISPCCDC_VDINT_1_SHIFT 0
  700. #define ISPCCDC_VDINT_1_MASK 0x00007fff
  701. #define ISPCCDC_VDINT_0_SHIFT 16
  702. #define ISPCCDC_VDINT_0_MASK 0x7fff0000
  703. #define ISPCCDC_ALAW_GWDI_12_3 (0x3 << 0)
  704. #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
  705. #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
  706. #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
  707. #define ISPCCDC_ALAW_CCDTBL (1 << 3)
  708. #define ISPCCDC_REC656IF_R656ON 1
  709. #define ISPCCDC_REC656IF_ECCFVH (1 << 1)
  710. #define ISPCCDC_CFG_BW656 (1 << 5)
  711. #define ISPCCDC_CFG_FIDMD_SHIFT 6
  712. #define ISPCCDC_CFG_WENLOG (1 << 8)
  713. #define ISPCCDC_CFG_WENLOG_AND (0 << 8)
  714. #define ISPCCDC_CFG_WENLOG_OR (1 << 8)
  715. #define ISPCCDC_CFG_Y8POS (1 << 11)
  716. #define ISPCCDC_CFG_BSWD (1 << 12)
  717. #define ISPCCDC_CFG_MSBINVI (1 << 13)
  718. #define ISPCCDC_CFG_VDLC (1 << 15)
  719. #define ISPCCDC_FMTCFG_FMTEN 0x1
  720. #define ISPCCDC_FMTCFG_LNALT (1 << 1)
  721. #define ISPCCDC_FMTCFG_LNUM_SHIFT 2
  722. #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4
  723. #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8
  724. #define ISPCCDC_FMTCFG_VPIN_MASK 0x00007000
  725. #define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12)
  726. #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
  727. #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
  728. #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
  729. #define ISPCCDC_FMTCFG_VPEN (1 << 15)
  730. #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
  731. #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16
  732. #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
  733. #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
  734. #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
  735. #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
  736. #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
  737. #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0
  738. #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT 16
  739. #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0
  740. #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT 16
  741. #define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1fff0000
  742. #define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x00001fff
  743. #define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1fff0000
  744. #define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x00001fff
  745. #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0
  746. #define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT 4
  747. #define ISPCCDC_VP_OUT_VERT_NUM_SHIFT 17
  748. #define ISPRSZ_PID_PREV_SHIFT 0
  749. #define ISPRSZ_PID_CID_SHIFT 8
  750. #define ISPRSZ_PID_TID_SHIFT 16
  751. #define ISPRSZ_PCR_ENABLE (1 << 0)
  752. #define ISPRSZ_PCR_BUSY (1 << 1)
  753. #define ISPRSZ_PCR_ONESHOT (1 << 2)
  754. #define ISPRSZ_CNT_HRSZ_SHIFT 0
  755. #define ISPRSZ_CNT_HRSZ_MASK \
  756. (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
  757. #define ISPRSZ_CNT_VRSZ_SHIFT 10
  758. #define ISPRSZ_CNT_VRSZ_MASK \
  759. (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
  760. #define ISPRSZ_CNT_HSTPH_SHIFT 20
  761. #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
  762. #define ISPRSZ_CNT_VSTPH_SHIFT 23
  763. #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
  764. #define ISPRSZ_CNT_YCPOS (1 << 26)
  765. #define ISPRSZ_CNT_INPTYP (1 << 27)
  766. #define ISPRSZ_CNT_INPSRC (1 << 28)
  767. #define ISPRSZ_CNT_CBILIN (1 << 29)
  768. #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
  769. #define ISPRSZ_OUT_SIZE_HORZ_MASK \
  770. (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
  771. #define ISPRSZ_OUT_SIZE_VERT_SHIFT 16
  772. #define ISPRSZ_OUT_SIZE_VERT_MASK \
  773. (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
  774. #define ISPRSZ_IN_START_HORZ_ST_SHIFT 0
  775. #define ISPRSZ_IN_START_HORZ_ST_MASK \
  776. (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
  777. #define ISPRSZ_IN_START_VERT_ST_SHIFT 16
  778. #define ISPRSZ_IN_START_VERT_ST_MASK \
  779. (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
  780. #define ISPRSZ_IN_SIZE_HORZ_SHIFT 0
  781. #define ISPRSZ_IN_SIZE_HORZ_MASK \
  782. (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
  783. #define ISPRSZ_IN_SIZE_VERT_SHIFT 16
  784. #define ISPRSZ_IN_SIZE_VERT_MASK \
  785. (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
  786. #define ISPRSZ_SDR_INADD_ADDR_SHIFT 0
  787. #define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF
  788. #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0
  789. #define ISPRSZ_SDR_INOFF_OFFSET_MASK \
  790. (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
  791. #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0
  792. #define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF
  793. #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0
  794. #define ISPRSZ_SDR_OUTOFF_OFFSET_MASK \
  795. (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
  796. #define ISPRSZ_HFILT_COEF0_SHIFT 0
  797. #define ISPRSZ_HFILT_COEF0_MASK \
  798. (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
  799. #define ISPRSZ_HFILT_COEF1_SHIFT 16
  800. #define ISPRSZ_HFILT_COEF1_MASK \
  801. (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
  802. #define ISPRSZ_HFILT32_COEF2_SHIFT 0
  803. #define ISPRSZ_HFILT32_COEF2_MASK 0x3FF
  804. #define ISPRSZ_HFILT32_COEF3_SHIFT 16
  805. #define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000
  806. #define ISPRSZ_HFILT54_COEF4_SHIFT 0
  807. #define ISPRSZ_HFILT54_COEF4_MASK 0x3FF
  808. #define ISPRSZ_HFILT54_COEF5_SHIFT 16
  809. #define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000
  810. #define ISPRSZ_HFILT76_COEFF6_SHIFT 0
  811. #define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF
  812. #define ISPRSZ_HFILT76_COEFF7_SHIFT 16
  813. #define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000
  814. #define ISPRSZ_HFILT98_COEFF8_SHIFT 0
  815. #define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF
  816. #define ISPRSZ_HFILT98_COEFF9_SHIFT 16
  817. #define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000
  818. #define ISPRSZ_HFILT1110_COEF10_SHIFT 0
  819. #define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF
  820. #define ISPRSZ_HFILT1110_COEF11_SHIFT 16
  821. #define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000
  822. #define ISPRSZ_HFILT1312_COEFF12_SHIFT 0
  823. #define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF
  824. #define ISPRSZ_HFILT1312_COEFF13_SHIFT 16
  825. #define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000
  826. #define ISPRSZ_HFILT1514_COEFF14_SHIFT 0
  827. #define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF
  828. #define ISPRSZ_HFILT1514_COEFF15_SHIFT 16
  829. #define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000
  830. #define ISPRSZ_HFILT1716_COEF16_SHIFT 0
  831. #define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF
  832. #define ISPRSZ_HFILT1716_COEF17_SHIFT 16
  833. #define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000
  834. #define ISPRSZ_HFILT1918_COEF18_SHIFT 0
  835. #define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF
  836. #define ISPRSZ_HFILT1918_COEF19_SHIFT 16
  837. #define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000
  838. #define ISPRSZ_HFILT2120_COEF20_SHIFT 0
  839. #define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF
  840. #define ISPRSZ_HFILT2120_COEF21_SHIFT 16
  841. #define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000
  842. #define ISPRSZ_HFILT2322_COEF22_SHIFT 0
  843. #define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF
  844. #define ISPRSZ_HFILT2322_COEF23_SHIFT 16
  845. #define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000
  846. #define ISPRSZ_HFILT2524_COEF24_SHIFT 0
  847. #define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF
  848. #define ISPRSZ_HFILT2524_COEF25_SHIFT 16
  849. #define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000
  850. #define ISPRSZ_HFILT2726_COEF26_SHIFT 0
  851. #define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF
  852. #define ISPRSZ_HFILT2726_COEF27_SHIFT 16
  853. #define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000
  854. #define ISPRSZ_HFILT2928_COEF28_SHIFT 0
  855. #define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF
  856. #define ISPRSZ_HFILT2928_COEF29_SHIFT 16
  857. #define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000
  858. #define ISPRSZ_HFILT3130_COEF30_SHIFT 0
  859. #define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF
  860. #define ISPRSZ_HFILT3130_COEF31_SHIFT 16
  861. #define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000
  862. #define ISPRSZ_VFILT_COEF0_SHIFT 0
  863. #define ISPRSZ_VFILT_COEF0_MASK \
  864. (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
  865. #define ISPRSZ_VFILT_COEF1_SHIFT 16
  866. #define ISPRSZ_VFILT_COEF1_MASK \
  867. (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
  868. #define ISPRSZ_VFILT10_COEF0_SHIFT 0
  869. #define ISPRSZ_VFILT10_COEF0_MASK 0x3FF
  870. #define ISPRSZ_VFILT10_COEF1_SHIFT 16
  871. #define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000
  872. #define ISPRSZ_VFILT32_COEF2_SHIFT 0
  873. #define ISPRSZ_VFILT32_COEF2_MASK 0x3FF
  874. #define ISPRSZ_VFILT32_COEF3_SHIFT 16
  875. #define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000
  876. #define ISPRSZ_VFILT54_COEF4_SHIFT 0
  877. #define ISPRSZ_VFILT54_COEF4_MASK 0x3FF
  878. #define ISPRSZ_VFILT54_COEF5_SHIFT 16
  879. #define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000
  880. #define ISPRSZ_VFILT76_COEFF6_SHIFT 0
  881. #define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF
  882. #define ISPRSZ_VFILT76_COEFF7_SHIFT 16
  883. #define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000
  884. #define ISPRSZ_VFILT98_COEFF8_SHIFT 0
  885. #define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF
  886. #define ISPRSZ_VFILT98_COEFF9_SHIFT 16
  887. #define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000
  888. #define ISPRSZ_VFILT1110_COEF10_SHIFT 0
  889. #define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF
  890. #define ISPRSZ_VFILT1110_COEF11_SHIFT 16
  891. #define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000
  892. #define ISPRSZ_VFILT1312_COEFF12_SHIFT 0
  893. #define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF
  894. #define ISPRSZ_VFILT1312_COEFF13_SHIFT 16
  895. #define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000
  896. #define ISPRSZ_VFILT1514_COEFF14_SHIFT 0
  897. #define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF
  898. #define ISPRSZ_VFILT1514_COEFF15_SHIFT 16
  899. #define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000
  900. #define ISPRSZ_VFILT1716_COEF16_SHIFT 0
  901. #define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF
  902. #define ISPRSZ_VFILT1716_COEF17_SHIFT 16
  903. #define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000
  904. #define ISPRSZ_VFILT1918_COEF18_SHIFT 0
  905. #define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF
  906. #define ISPRSZ_VFILT1918_COEF19_SHIFT 16
  907. #define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000
  908. #define ISPRSZ_VFILT2120_COEF20_SHIFT 0
  909. #define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF
  910. #define ISPRSZ_VFILT2120_COEF21_SHIFT 16
  911. #define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000
  912. #define ISPRSZ_VFILT2322_COEF22_SHIFT 0
  913. #define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF
  914. #define ISPRSZ_VFILT2322_COEF23_SHIFT 16
  915. #define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000
  916. #define ISPRSZ_VFILT2524_COEF24_SHIFT 0
  917. #define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF
  918. #define ISPRSZ_VFILT2524_COEF25_SHIFT 16
  919. #define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000
  920. #define ISPRSZ_VFILT2726_COEF26_SHIFT 0
  921. #define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF
  922. #define ISPRSZ_VFILT2726_COEF27_SHIFT 16
  923. #define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000
  924. #define ISPRSZ_VFILT2928_COEF28_SHIFT 0
  925. #define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF
  926. #define ISPRSZ_VFILT2928_COEF29_SHIFT 16
  927. #define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000
  928. #define ISPRSZ_VFILT3130_COEF30_SHIFT 0
  929. #define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF
  930. #define ISPRSZ_VFILT3130_COEF31_SHIFT 16
  931. #define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000
  932. #define ISPRSZ_YENH_CORE_SHIFT 0
  933. #define ISPRSZ_YENH_CORE_MASK \
  934. (0xFF << ISPRSZ_YENH_CORE_SHIFT)
  935. #define ISPRSZ_YENH_SLOP_SHIFT 8
  936. #define ISPRSZ_YENH_SLOP_MASK \
  937. (0xF << ISPRSZ_YENH_SLOP_SHIFT)
  938. #define ISPRSZ_YENH_GAIN_SHIFT 12
  939. #define ISPRSZ_YENH_GAIN_MASK \
  940. (0xF << ISPRSZ_YENH_GAIN_SHIFT)
  941. #define ISPRSZ_YENH_ALGO_SHIFT 16
  942. #define ISPRSZ_YENH_ALGO_MASK \
  943. (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
  944. #define ISPH3A_PCR_AEW_ALAW_EN_SHIFT 1
  945. #define ISPH3A_PCR_AF_MED_TH_SHIFT 3
  946. #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11
  947. #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22
  948. #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
  949. #define ISPH3A_PCR_BUSYAF (1 << 15)
  950. #define ISPH3A_PCR_BUSYAEAWB (1 << 18)
  951. #define ISPH3A_AEWWIN1_WINHC_SHIFT 0
  952. #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
  953. #define ISPH3A_AEWWIN1_WINVC_SHIFT 6
  954. #define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0
  955. #define ISPH3A_AEWWIN1_WINW_SHIFT 13
  956. #define ISPH3A_AEWWIN1_WINW_MASK 0xFE000
  957. #define ISPH3A_AEWWIN1_WINH_SHIFT 24
  958. #define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000
  959. #define ISPH3A_AEWINSTART_WINSH_SHIFT 0
  960. #define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF
  961. #define ISPH3A_AEWINSTART_WINSV_SHIFT 16
  962. #define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000
  963. #define ISPH3A_AEWINBLK_WINH_SHIFT 0
  964. #define ISPH3A_AEWINBLK_WINH_MASK 0x7F
  965. #define ISPH3A_AEWINBLK_WINSV_SHIFT 16
  966. #define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000
  967. #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0
  968. #define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F
  969. #define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT 8
  970. #define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00
  971. #define ISPHIST_PCR_ENABLE_SHIFT 0
  972. #define ISPHIST_PCR_ENABLE_MASK 0x01
  973. #define ISPHIST_PCR_ENABLE (1 << ISPHIST_PCR_ENABLE_SHIFT)
  974. #define ISPHIST_PCR_BUSY 0x02
  975. #define ISPHIST_CNT_DATASIZE_SHIFT 8
  976. #define ISPHIST_CNT_DATASIZE_MASK 0x0100
  977. #define ISPHIST_CNT_CLEAR_SHIFT 7
  978. #define ISPHIST_CNT_CLEAR_MASK 0x080
  979. #define ISPHIST_CNT_CLEAR (1 << ISPHIST_CNT_CLEAR_SHIFT)
  980. #define ISPHIST_CNT_CFA_SHIFT 6
  981. #define ISPHIST_CNT_CFA_MASK 0x040
  982. #define ISPHIST_CNT_BINS_SHIFT 4
  983. #define ISPHIST_CNT_BINS_MASK 0x030
  984. #define ISPHIST_CNT_SOURCE_SHIFT 3
  985. #define ISPHIST_CNT_SOURCE_MASK 0x08
  986. #define ISPHIST_CNT_SHIFT_SHIFT 0
  987. #define ISPHIST_CNT_SHIFT_MASK 0x07
  988. #define ISPHIST_WB_GAIN_WG00_SHIFT 24
  989. #define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000
  990. #define ISPHIST_WB_GAIN_WG01_SHIFT 16
  991. #define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000
  992. #define ISPHIST_WB_GAIN_WG02_SHIFT 8
  993. #define ISPHIST_WB_GAIN_WG02_MASK 0xFF00
  994. #define ISPHIST_WB_GAIN_WG03_SHIFT 0
  995. #define ISPHIST_WB_GAIN_WG03_MASK 0xFF
  996. #define ISPHIST_REG_START_END_MASK 0x3FFF
  997. #define ISPHIST_REG_START_SHIFT 16
  998. #define ISPHIST_REG_END_SHIFT 0
  999. #define ISPHIST_REG_START_MASK (ISPHIST_REG_START_END_MASK << \
  1000. ISPHIST_REG_START_SHIFT)
  1001. #define ISPHIST_REG_END_MASK (ISPHIST_REG_START_END_MASK << \
  1002. ISPHIST_REG_END_SHIFT)
  1003. #define ISPHIST_REG_MASK (ISPHIST_REG_START_MASK | \
  1004. ISPHIST_REG_END_MASK)
  1005. #define ISPHIST_ADDR_SHIFT 0
  1006. #define ISPHIST_ADDR_MASK 0x3FF
  1007. #define ISPHIST_DATA_SHIFT 0
  1008. #define ISPHIST_DATA_MASK 0xFFFFF
  1009. #define ISPHIST_RADD_SHIFT 0
  1010. #define ISPHIST_RADD_MASK 0xFFFFFFFF
  1011. #define ISPHIST_RADD_OFF_SHIFT 0
  1012. #define ISPHIST_RADD_OFF_MASK 0xFFFF
  1013. #define ISPHIST_HV_INFO_HSIZE_SHIFT 16
  1014. #define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000
  1015. #define ISPHIST_HV_INFO_VSIZE_SHIFT 0
  1016. #define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF
  1017. #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
  1018. #define ISPCCDC_LSC_ENABLE 1
  1019. #define ISPCCDC_LSC_BUSY (1 << 7)
  1020. #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
  1021. #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8
  1022. #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
  1023. #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12
  1024. #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
  1025. #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1
  1026. #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6)
  1027. #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
  1028. #define ISPCCDC_LSC_INITIAL_X_SHIFT 0
  1029. #define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000
  1030. #define ISPCCDC_LSC_INITIAL_Y_SHIFT 16
  1031. /* -----------------------------------------------------------------------------
  1032. * CSI2 receiver registers (ES2.0)
  1033. */
  1034. #define ISPCSI2_REVISION (0x000)
  1035. #define ISPCSI2_SYSCONFIG (0x010)
  1036. #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
  1037. #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK \
  1038. (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  1039. #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE \
  1040. (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  1041. #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO \
  1042. (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  1043. #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \
  1044. (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
  1045. #define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1)
  1046. #define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0)
  1047. #define ISPCSI2_SYSSTATUS (0x014)
  1048. #define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0)
  1049. #define ISPCSI2_IRQSTATUS (0x018)
  1050. #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14)
  1051. #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13)
  1052. #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12)
  1053. #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
  1054. #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10)
  1055. #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9)
  1056. #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8)
  1057. #define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n))
  1058. #define ISPCSI2_IRQENABLE (0x01c)
  1059. #define ISPCSI2_CTRL (0x040)
  1060. #define ISPCSI2_CTRL_VP_CLK_EN (1 << 15)
  1061. #define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11)
  1062. #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8
  1063. #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \
  1064. (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
  1065. #define ISPCSI2_CTRL_DBG_EN (1 << 7)
  1066. #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5
  1067. #define ISPCSI2_CTRL_BURST_SIZE_MASK \
  1068. (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
  1069. #define ISPCSI2_CTRL_FRAME (1 << 3)
  1070. #define ISPCSI2_CTRL_ECC_EN (1 << 2)
  1071. #define ISPCSI2_CTRL_SECURE (1 << 1)
  1072. #define ISPCSI2_CTRL_IF_EN (1 << 0)
  1073. #define ISPCSI2_DBG_H (0x044)
  1074. #define ISPCSI2_GNQ (0x048)
  1075. #define ISPCSI2_PHY_CFG (0x050)
  1076. #define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30)
  1077. #define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29)
  1078. #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27
  1079. #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \
  1080. (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
  1081. #define ISPCSI2_PHY_CFG_PWR_CMD_OFF \
  1082. (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
  1083. #define ISPCSI2_PHY_CFG_PWR_CMD_ON \
  1084. (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
  1085. #define ISPCSI2_PHY_CFG_PWR_CMD_ULPW \
  1086. (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
  1087. #define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT 25
  1088. #define ISPCSI2_PHY_CFG_PWR_STATUS_MASK \
  1089. (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
  1090. #define ISPCSI2_PHY_CFG_PWR_STATUS_OFF \
  1091. (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
  1092. #define ISPCSI2_PHY_CFG_PWR_STATUS_ON \
  1093. (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
  1094. #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \
  1095. (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
  1096. #define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24)
  1097. #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4))
  1098. #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \
  1099. (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
  1100. #define ISPCSI2_PHY_CFG_DATA_POL_PN(n) \
  1101. (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
  1102. #define ISPCSI2_PHY_CFG_DATA_POL_NP(n) \
  1103. (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
  1104. #define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n) ((n) * 4)
  1105. #define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n) \
  1106. (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1107. #define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n) \
  1108. (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1109. #define ISPCSI2_PHY_CFG_DATA_POSITION_1(n) \
  1110. (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1111. #define ISPCSI2_PHY_CFG_DATA_POSITION_2(n) \
  1112. (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1113. #define ISPCSI2_PHY_CFG_DATA_POSITION_3(n) \
  1114. (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1115. #define ISPCSI2_PHY_CFG_DATA_POSITION_4(n) \
  1116. (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1117. #define ISPCSI2_PHY_CFG_DATA_POSITION_5(n) \
  1118. (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
  1119. #define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT 3
  1120. #define ISPCSI2_PHY_CFG_CLOCK_POL_MASK \
  1121. (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
  1122. #define ISPCSI2_PHY_CFG_CLOCK_POL_PN \
  1123. (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
  1124. #define ISPCSI2_PHY_CFG_CLOCK_POL_NP \
  1125. (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
  1126. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT 0
  1127. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK \
  1128. (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
  1129. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_1 \
  1130. (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
  1131. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_2 \
  1132. (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
  1133. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_3 \
  1134. (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
  1135. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_4 \
  1136. (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
  1137. #define ISPCSI2_PHY_CFG_CLOCK_POSITION_5 \
  1138. (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
  1139. #define ISPCSI2_PHY_IRQSTATUS (0x054)
  1140. #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26)
  1141. #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25)
  1142. #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24)
  1143. #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23)
  1144. #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22)
  1145. #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21)
  1146. #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20)
  1147. #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19)
  1148. #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18)
  1149. #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17)
  1150. #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16)
  1151. #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15)
  1152. #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14)
  1153. #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13)
  1154. #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12)
  1155. #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11)
  1156. #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10)
  1157. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9)
  1158. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8)
  1159. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7)
  1160. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6)
  1161. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5)
  1162. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4)
  1163. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3)
  1164. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2)
  1165. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1)
  1166. #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1
  1167. #define ISPCSI2_SHORT_PACKET (0x05c)
  1168. #define ISPCSI2_PHY_IRQENABLE (0x060)
  1169. #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26)
  1170. #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25)
  1171. #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24)
  1172. #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23)
  1173. #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22)
  1174. #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21)
  1175. #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20)
  1176. #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19)
  1177. #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18)
  1178. #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17)
  1179. #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16)
  1180. #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15)
  1181. #define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14)
  1182. #define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13)
  1183. #define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12)
  1184. #define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11)
  1185. #define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10)
  1186. #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9)
  1187. #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8)
  1188. #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7)
  1189. #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6)
  1190. #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5)
  1191. #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4)
  1192. #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3)
  1193. #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2)
  1194. #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1)
  1195. #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0)
  1196. #define ISPCSI2_DBG_P (0x068)
  1197. #define ISPCSI2_TIMING (0x06c)
  1198. #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n) (1 << ((16 * ((n) - 1)) + 15))
  1199. #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n) (1 << ((16 * ((n) - 1)) + 14))
  1200. #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n) (1 << ((16 * ((n) - 1)) + 13))
  1201. #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) (16 * ((n) - 1))
  1202. #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) \
  1203. (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
  1204. #define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n))
  1205. #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8
  1206. #define ISPCSI2_CTX_CTRL1_COUNT_MASK \
  1207. (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
  1208. #define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7)
  1209. #define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6)
  1210. #define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5)
  1211. #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4)
  1212. #define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3)
  1213. #define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0)
  1214. #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
  1215. #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13
  1216. #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK \
  1217. (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
  1218. #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11
  1219. #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
  1220. (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
  1221. #define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10)
  1222. #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
  1223. #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \
  1224. (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
  1225. #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT 16
  1226. #define ISPCSI2_CTX_CTRL2_FRAME_MASK \
  1227. (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
  1228. #define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n))
  1229. #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 0
  1230. #define ISPCSI2_CTX_DAT_OFST_OFST_MASK \
  1231. (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
  1232. #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
  1233. #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
  1234. #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
  1235. #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8)
  1236. #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7)
  1237. #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6)
  1238. #define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5)
  1239. #define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3)
  1240. #define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2)
  1241. #define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1)
  1242. #define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0)
  1243. #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
  1244. #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8)
  1245. #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7)
  1246. #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6)
  1247. #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5)
  1248. #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3)
  1249. #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2)
  1250. #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1)
  1251. #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0)
  1252. #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
  1253. #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5
  1254. #define ISPCSI2_CTX_CTRL3_ALPHA_MASK \
  1255. (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
  1256. /* This instance is for OMAP3630 only */
  1257. #define ISPCSI2_CTX_TRANSCODEH(n) (0x000 + 0x8 * (n))
  1258. #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT 16
  1259. #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK \
  1260. (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
  1261. #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT 0
  1262. #define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK \
  1263. (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
  1264. #define ISPCSI2_CTX_TRANSCODEV(n) (0x004 + 0x8 * (n))
  1265. #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT 16
  1266. #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK \
  1267. (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
  1268. #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT 0
  1269. #define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK \
  1270. (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
  1271. /* -----------------------------------------------------------------------------
  1272. * CSI PHY registers
  1273. */
  1274. #define ISPCSIPHY_REG0 (0x000)
  1275. #define ISPCSIPHY_REG0_THS_TERM_SHIFT 8
  1276. #define ISPCSIPHY_REG0_THS_TERM_MASK \
  1277. (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
  1278. #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT 0
  1279. #define ISPCSIPHY_REG0_THS_SETTLE_MASK \
  1280. (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
  1281. #define ISPCSIPHY_REG1 (0x004)
  1282. #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29)
  1283. /* This field is for OMAP3630 only */
  1284. #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25)
  1285. #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18
  1286. #define ISPCSIPHY_REG1_TCLK_TERM_MASK \
  1287. (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
  1288. #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT 10
  1289. #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK \
  1290. (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
  1291. /* This field is for OMAP3430 only */
  1292. #define ISPCSIPHY_REG1_TCLK_MISS_SHIFT 8
  1293. #define ISPCSIPHY_REG1_TCLK_MISS_MASK \
  1294. (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
  1295. /* This field is for OMAP3630 only */
  1296. #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT 8
  1297. #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK \
  1298. (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
  1299. #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT 0
  1300. #define ISPCSIPHY_REG1_TCLK_SETTLE_MASK \
  1301. (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
  1302. /* This register is for OMAP3630 only */
  1303. #define ISPCSIPHY_REG2 (0x008)
  1304. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT 30
  1305. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK \
  1306. (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
  1307. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT 28
  1308. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK \
  1309. (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
  1310. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT 26
  1311. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK \
  1312. (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
  1313. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT 24
  1314. #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK \
  1315. (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
  1316. #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT 0
  1317. #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK \
  1318. (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
  1319. /* -----------------------------------------------------------------------------
  1320. * CONTROL registers for CSI-2 phy routing
  1321. */
  1322. /* OMAP343X_CONTROL_CSIRXFE */
  1323. #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV (1 << 7)
  1324. #define OMAP343X_CONTROL_CSIRXFE_RESENABLE (1 << 8)
  1325. #define OMAP343X_CONTROL_CSIRXFE_SELFORM (1 << 10)
  1326. #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ (1 << 12)
  1327. #define OMAP343X_CONTROL_CSIRXFE_RESET (1 << 13)
  1328. /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */
  1329. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2
  1330. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT 0
  1331. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY 0x0
  1332. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE 0x1
  1333. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK 0x2
  1334. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3
  1335. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3
  1336. /* CCP2B: set to receive data from PHY2 instead of PHY1 */
  1337. #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 (1 << 4)
  1338. #endif /* OMAP3_ISP_REG_H */