vsp1_hgo.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * vsp1_hgo.c -- R-Car VSP1 Histogram Generator 1D
  4. *
  5. * Copyright (C) 2016 Renesas Electronics Corporation
  6. *
  7. * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
  8. */
  9. #include <linux/device.h>
  10. #include <linux/gfp.h>
  11. #include <media/v4l2-subdev.h>
  12. #include <media/videobuf2-vmalloc.h>
  13. #include "vsp1.h"
  14. #include "vsp1_dl.h"
  15. #include "vsp1_hgo.h"
  16. #define HGO_DATA_SIZE ((2 + 256) * 4)
  17. /* -----------------------------------------------------------------------------
  18. * Device Access
  19. */
  20. static inline u32 vsp1_hgo_read(struct vsp1_hgo *hgo, u32 reg)
  21. {
  22. return vsp1_read(hgo->histo.entity.vsp1, reg);
  23. }
  24. static inline void vsp1_hgo_write(struct vsp1_hgo *hgo,
  25. struct vsp1_dl_body *dlb, u32 reg, u32 data)
  26. {
  27. vsp1_dl_body_write(dlb, reg, data);
  28. }
  29. /* -----------------------------------------------------------------------------
  30. * Frame End Handler
  31. */
  32. void vsp1_hgo_frame_end(struct vsp1_entity *entity)
  33. {
  34. struct vsp1_hgo *hgo = to_hgo(&entity->subdev);
  35. struct vsp1_histogram_buffer *buf;
  36. unsigned int i;
  37. size_t size;
  38. u32 *data;
  39. buf = vsp1_histogram_buffer_get(&hgo->histo);
  40. if (!buf)
  41. return;
  42. data = buf->addr;
  43. if (hgo->num_bins == 256) {
  44. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN);
  45. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM);
  46. for (i = 0; i < 256; ++i) {
  47. vsp1_write(hgo->histo.entity.vsp1,
  48. VI6_HGO_EXT_HIST_ADDR, i);
  49. *data++ = vsp1_hgo_read(hgo, VI6_HGO_EXT_HIST_DATA);
  50. }
  51. size = (2 + 256) * sizeof(u32);
  52. } else if (hgo->max_rgb) {
  53. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN);
  54. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM);
  55. for (i = 0; i < 64; ++i)
  56. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_HISTO(i));
  57. size = (2 + 64) * sizeof(u32);
  58. } else {
  59. *data++ = vsp1_hgo_read(hgo, VI6_HGO_R_MAXMIN);
  60. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN);
  61. *data++ = vsp1_hgo_read(hgo, VI6_HGO_B_MAXMIN);
  62. *data++ = vsp1_hgo_read(hgo, VI6_HGO_R_SUM);
  63. *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM);
  64. *data++ = vsp1_hgo_read(hgo, VI6_HGO_B_SUM);
  65. for (i = 0; i < 64; ++i) {
  66. data[i] = vsp1_hgo_read(hgo, VI6_HGO_R_HISTO(i));
  67. data[i+64] = vsp1_hgo_read(hgo, VI6_HGO_G_HISTO(i));
  68. data[i+128] = vsp1_hgo_read(hgo, VI6_HGO_B_HISTO(i));
  69. }
  70. size = (6 + 64 * 3) * sizeof(u32);
  71. }
  72. vsp1_histogram_buffer_complete(&hgo->histo, buf, size);
  73. }
  74. /* -----------------------------------------------------------------------------
  75. * Controls
  76. */
  77. #define V4L2_CID_VSP1_HGO_MAX_RGB (V4L2_CID_USER_BASE | 0x1001)
  78. #define V4L2_CID_VSP1_HGO_NUM_BINS (V4L2_CID_USER_BASE | 0x1002)
  79. static const struct v4l2_ctrl_config hgo_max_rgb_control = {
  80. .id = V4L2_CID_VSP1_HGO_MAX_RGB,
  81. .name = "Maximum RGB Mode",
  82. .type = V4L2_CTRL_TYPE_BOOLEAN,
  83. .min = 0,
  84. .max = 1,
  85. .def = 0,
  86. .step = 1,
  87. .flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT,
  88. };
  89. static const s64 hgo_num_bins[] = {
  90. 64, 256,
  91. };
  92. static const struct v4l2_ctrl_config hgo_num_bins_control = {
  93. .id = V4L2_CID_VSP1_HGO_NUM_BINS,
  94. .name = "Number of Bins",
  95. .type = V4L2_CTRL_TYPE_INTEGER_MENU,
  96. .min = 0,
  97. .max = 1,
  98. .def = 0,
  99. .qmenu_int = hgo_num_bins,
  100. .flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT,
  101. };
  102. /* -----------------------------------------------------------------------------
  103. * VSP1 Entity Operations
  104. */
  105. static void hgo_configure_stream(struct vsp1_entity *entity,
  106. struct vsp1_pipeline *pipe,
  107. struct vsp1_dl_body *dlb)
  108. {
  109. struct vsp1_hgo *hgo = to_hgo(&entity->subdev);
  110. struct v4l2_rect *compose;
  111. struct v4l2_rect *crop;
  112. unsigned int hratio;
  113. unsigned int vratio;
  114. crop = vsp1_entity_get_pad_selection(entity, entity->config,
  115. HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);
  116. compose = vsp1_entity_get_pad_selection(entity, entity->config,
  117. HISTO_PAD_SINK,
  118. V4L2_SEL_TGT_COMPOSE);
  119. vsp1_hgo_write(hgo, dlb, VI6_HGO_REGRST, VI6_HGO_REGRST_RCLEA);
  120. vsp1_hgo_write(hgo, dlb, VI6_HGO_OFFSET,
  121. (crop->left << VI6_HGO_OFFSET_HOFFSET_SHIFT) |
  122. (crop->top << VI6_HGO_OFFSET_VOFFSET_SHIFT));
  123. vsp1_hgo_write(hgo, dlb, VI6_HGO_SIZE,
  124. (crop->width << VI6_HGO_SIZE_HSIZE_SHIFT) |
  125. (crop->height << VI6_HGO_SIZE_VSIZE_SHIFT));
  126. mutex_lock(hgo->ctrls.handler.lock);
  127. hgo->max_rgb = hgo->ctrls.max_rgb->cur.val;
  128. if (hgo->ctrls.num_bins)
  129. hgo->num_bins = hgo_num_bins[hgo->ctrls.num_bins->cur.val];
  130. mutex_unlock(hgo->ctrls.handler.lock);
  131. hratio = crop->width * 2 / compose->width / 3;
  132. vratio = crop->height * 2 / compose->height / 3;
  133. vsp1_hgo_write(hgo, dlb, VI6_HGO_MODE,
  134. (hgo->num_bins == 256 ? VI6_HGO_MODE_STEP : 0) |
  135. (hgo->max_rgb ? VI6_HGO_MODE_MAXRGB : 0) |
  136. (hratio << VI6_HGO_MODE_HRATIO_SHIFT) |
  137. (vratio << VI6_HGO_MODE_VRATIO_SHIFT));
  138. }
  139. static const struct vsp1_entity_operations hgo_entity_ops = {
  140. .configure_stream = hgo_configure_stream,
  141. .destroy = vsp1_histogram_destroy,
  142. };
  143. /* -----------------------------------------------------------------------------
  144. * Initialization and Cleanup
  145. */
  146. static const unsigned int hgo_mbus_formats[] = {
  147. MEDIA_BUS_FMT_AYUV8_1X32,
  148. MEDIA_BUS_FMT_ARGB8888_1X32,
  149. MEDIA_BUS_FMT_AHSV8888_1X32,
  150. };
  151. struct vsp1_hgo *vsp1_hgo_create(struct vsp1_device *vsp1)
  152. {
  153. struct vsp1_hgo *hgo;
  154. int ret;
  155. hgo = devm_kzalloc(vsp1->dev, sizeof(*hgo), GFP_KERNEL);
  156. if (hgo == NULL)
  157. return ERR_PTR(-ENOMEM);
  158. /* Initialize the control handler. */
  159. v4l2_ctrl_handler_init(&hgo->ctrls.handler,
  160. vsp1->info->gen == 3 ? 2 : 1);
  161. hgo->ctrls.max_rgb = v4l2_ctrl_new_custom(&hgo->ctrls.handler,
  162. &hgo_max_rgb_control, NULL);
  163. if (vsp1->info->gen == 3)
  164. hgo->ctrls.num_bins =
  165. v4l2_ctrl_new_custom(&hgo->ctrls.handler,
  166. &hgo_num_bins_control, NULL);
  167. hgo->max_rgb = false;
  168. hgo->num_bins = 64;
  169. hgo->histo.entity.subdev.ctrl_handler = &hgo->ctrls.handler;
  170. /* Initialize the video device and queue for statistics data. */
  171. ret = vsp1_histogram_init(vsp1, &hgo->histo, VSP1_ENTITY_HGO, "hgo",
  172. &hgo_entity_ops, hgo_mbus_formats,
  173. ARRAY_SIZE(hgo_mbus_formats),
  174. HGO_DATA_SIZE, V4L2_META_FMT_VSP1_HGO);
  175. if (ret < 0) {
  176. vsp1_entity_destroy(&hgo->histo.entity);
  177. return ERR_PTR(ret);
  178. }
  179. return hgo;
  180. }