mc.c 16 KB

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  1. /*
  2. * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/sort.h>
  17. #include <soc/tegra/fuse.h>
  18. #include "mc.h"
  19. #define MC_INTSTATUS 0x000
  20. #define MC_INTMASK 0x004
  21. #define MC_ERR_STATUS 0x08
  22. #define MC_ERR_STATUS_TYPE_SHIFT 28
  23. #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
  24. #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
  25. #define MC_ERR_STATUS_READABLE (1 << 27)
  26. #define MC_ERR_STATUS_WRITABLE (1 << 26)
  27. #define MC_ERR_STATUS_NONSECURE (1 << 25)
  28. #define MC_ERR_STATUS_ADR_HI_SHIFT 20
  29. #define MC_ERR_STATUS_ADR_HI_MASK 0x3
  30. #define MC_ERR_STATUS_SECURITY (1 << 17)
  31. #define MC_ERR_STATUS_RW (1 << 16)
  32. #define MC_ERR_ADR 0x0c
  33. #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
  34. #define MC_SECURITY_VIOLATION_STATUS 0x74
  35. #define MC_EMEM_ARB_CFG 0x90
  36. #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
  37. #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
  38. #define MC_EMEM_ARB_MISC0 0xd8
  39. #define MC_EMEM_ADR_CFG 0x54
  40. #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
  41. static const struct of_device_id tegra_mc_of_match[] = {
  42. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  43. { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
  44. #endif
  45. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  46. { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
  47. #endif
  48. #ifdef CONFIG_ARCH_TEGRA_114_SOC
  49. { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
  50. #endif
  51. #ifdef CONFIG_ARCH_TEGRA_124_SOC
  52. { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
  53. #endif
  54. #ifdef CONFIG_ARCH_TEGRA_132_SOC
  55. { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
  56. #endif
  57. #ifdef CONFIG_ARCH_TEGRA_210_SOC
  58. { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
  59. #endif
  60. { }
  61. };
  62. MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
  63. static int terga_mc_block_dma_common(struct tegra_mc *mc,
  64. const struct tegra_mc_reset *rst)
  65. {
  66. unsigned long flags;
  67. u32 value;
  68. spin_lock_irqsave(&mc->lock, flags);
  69. value = mc_readl(mc, rst->control) | BIT(rst->bit);
  70. mc_writel(mc, value, rst->control);
  71. spin_unlock_irqrestore(&mc->lock, flags);
  72. return 0;
  73. }
  74. static bool terga_mc_dma_idling_common(struct tegra_mc *mc,
  75. const struct tegra_mc_reset *rst)
  76. {
  77. return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
  78. }
  79. static int terga_mc_unblock_dma_common(struct tegra_mc *mc,
  80. const struct tegra_mc_reset *rst)
  81. {
  82. unsigned long flags;
  83. u32 value;
  84. spin_lock_irqsave(&mc->lock, flags);
  85. value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
  86. mc_writel(mc, value, rst->control);
  87. spin_unlock_irqrestore(&mc->lock, flags);
  88. return 0;
  89. }
  90. static int terga_mc_reset_status_common(struct tegra_mc *mc,
  91. const struct tegra_mc_reset *rst)
  92. {
  93. return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
  94. }
  95. const struct tegra_mc_reset_ops terga_mc_reset_ops_common = {
  96. .block_dma = terga_mc_block_dma_common,
  97. .dma_idling = terga_mc_dma_idling_common,
  98. .unblock_dma = terga_mc_unblock_dma_common,
  99. .reset_status = terga_mc_reset_status_common,
  100. };
  101. static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
  102. {
  103. return container_of(rcdev, struct tegra_mc, reset);
  104. }
  105. static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
  106. unsigned long id)
  107. {
  108. unsigned int i;
  109. for (i = 0; i < mc->soc->num_resets; i++)
  110. if (mc->soc->resets[i].id == id)
  111. return &mc->soc->resets[i];
  112. return NULL;
  113. }
  114. static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
  115. unsigned long id)
  116. {
  117. struct tegra_mc *mc = reset_to_mc(rcdev);
  118. const struct tegra_mc_reset_ops *rst_ops;
  119. const struct tegra_mc_reset *rst;
  120. int retries = 500;
  121. int err;
  122. rst = tegra_mc_reset_find(mc, id);
  123. if (!rst)
  124. return -ENODEV;
  125. rst_ops = mc->soc->reset_ops;
  126. if (!rst_ops)
  127. return -ENODEV;
  128. if (rst_ops->block_dma) {
  129. /* block clients DMA requests */
  130. err = rst_ops->block_dma(mc, rst);
  131. if (err) {
  132. dev_err(mc->dev, "Failed to block %s DMA: %d\n",
  133. rst->name, err);
  134. return err;
  135. }
  136. }
  137. if (rst_ops->dma_idling) {
  138. /* wait for completion of the outstanding DMA requests */
  139. while (!rst_ops->dma_idling(mc, rst)) {
  140. if (!retries--) {
  141. dev_err(mc->dev, "Failed to flush %s DMA\n",
  142. rst->name);
  143. return -EBUSY;
  144. }
  145. usleep_range(10, 100);
  146. }
  147. }
  148. if (rst_ops->hotreset_assert) {
  149. /* clear clients DMA requests sitting before arbitration */
  150. err = rst_ops->hotreset_assert(mc, rst);
  151. if (err) {
  152. dev_err(mc->dev, "Failed to hot reset %s: %d\n",
  153. rst->name, err);
  154. return err;
  155. }
  156. }
  157. return 0;
  158. }
  159. static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
  160. unsigned long id)
  161. {
  162. struct tegra_mc *mc = reset_to_mc(rcdev);
  163. const struct tegra_mc_reset_ops *rst_ops;
  164. const struct tegra_mc_reset *rst;
  165. int err;
  166. rst = tegra_mc_reset_find(mc, id);
  167. if (!rst)
  168. return -ENODEV;
  169. rst_ops = mc->soc->reset_ops;
  170. if (!rst_ops)
  171. return -ENODEV;
  172. if (rst_ops->hotreset_deassert) {
  173. /* take out client from hot reset */
  174. err = rst_ops->hotreset_deassert(mc, rst);
  175. if (err) {
  176. dev_err(mc->dev, "Failed to deassert hot reset %s: %d\n",
  177. rst->name, err);
  178. return err;
  179. }
  180. }
  181. if (rst_ops->unblock_dma) {
  182. /* allow new DMA requests to proceed to arbitration */
  183. err = rst_ops->unblock_dma(mc, rst);
  184. if (err) {
  185. dev_err(mc->dev, "Failed to unblock %s DMA : %d\n",
  186. rst->name, err);
  187. return err;
  188. }
  189. }
  190. return 0;
  191. }
  192. static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
  193. unsigned long id)
  194. {
  195. struct tegra_mc *mc = reset_to_mc(rcdev);
  196. const struct tegra_mc_reset_ops *rst_ops;
  197. const struct tegra_mc_reset *rst;
  198. rst = tegra_mc_reset_find(mc, id);
  199. if (!rst)
  200. return -ENODEV;
  201. rst_ops = mc->soc->reset_ops;
  202. if (!rst_ops)
  203. return -ENODEV;
  204. return rst_ops->reset_status(mc, rst);
  205. }
  206. static const struct reset_control_ops tegra_mc_reset_ops = {
  207. .assert = tegra_mc_hotreset_assert,
  208. .deassert = tegra_mc_hotreset_deassert,
  209. .status = tegra_mc_hotreset_status,
  210. };
  211. static int tegra_mc_reset_setup(struct tegra_mc *mc)
  212. {
  213. int err;
  214. mc->reset.ops = &tegra_mc_reset_ops;
  215. mc->reset.owner = THIS_MODULE;
  216. mc->reset.of_node = mc->dev->of_node;
  217. mc->reset.of_reset_n_cells = 1;
  218. mc->reset.nr_resets = mc->soc->num_resets;
  219. err = reset_controller_register(&mc->reset);
  220. if (err < 0)
  221. return err;
  222. return 0;
  223. }
  224. static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
  225. {
  226. unsigned long long tick;
  227. unsigned int i;
  228. u32 value;
  229. /* compute the number of MC clock cycles per tick */
  230. tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
  231. do_div(tick, NSEC_PER_SEC);
  232. value = readl(mc->regs + MC_EMEM_ARB_CFG);
  233. value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
  234. value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
  235. writel(value, mc->regs + MC_EMEM_ARB_CFG);
  236. /* write latency allowance defaults */
  237. for (i = 0; i < mc->soc->num_clients; i++) {
  238. const struct tegra_mc_la *la = &mc->soc->clients[i].la;
  239. u32 value;
  240. value = readl(mc->regs + la->reg);
  241. value &= ~(la->mask << la->shift);
  242. value |= (la->def & la->mask) << la->shift;
  243. writel(value, mc->regs + la->reg);
  244. }
  245. return 0;
  246. }
  247. void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
  248. {
  249. unsigned int i;
  250. struct tegra_mc_timing *timing = NULL;
  251. for (i = 0; i < mc->num_timings; i++) {
  252. if (mc->timings[i].rate == rate) {
  253. timing = &mc->timings[i];
  254. break;
  255. }
  256. }
  257. if (!timing) {
  258. dev_err(mc->dev, "no memory timing registered for rate %lu\n",
  259. rate);
  260. return;
  261. }
  262. for (i = 0; i < mc->soc->num_emem_regs; ++i)
  263. mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
  264. }
  265. unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
  266. {
  267. u8 dram_count;
  268. dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
  269. dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
  270. dram_count++;
  271. return dram_count;
  272. }
  273. static int load_one_timing(struct tegra_mc *mc,
  274. struct tegra_mc_timing *timing,
  275. struct device_node *node)
  276. {
  277. int err;
  278. u32 tmp;
  279. err = of_property_read_u32(node, "clock-frequency", &tmp);
  280. if (err) {
  281. dev_err(mc->dev,
  282. "timing %s: failed to read rate\n", node->name);
  283. return err;
  284. }
  285. timing->rate = tmp;
  286. timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
  287. sizeof(u32), GFP_KERNEL);
  288. if (!timing->emem_data)
  289. return -ENOMEM;
  290. err = of_property_read_u32_array(node, "nvidia,emem-configuration",
  291. timing->emem_data,
  292. mc->soc->num_emem_regs);
  293. if (err) {
  294. dev_err(mc->dev,
  295. "timing %s: failed to read EMEM configuration\n",
  296. node->name);
  297. return err;
  298. }
  299. return 0;
  300. }
  301. static int load_timings(struct tegra_mc *mc, struct device_node *node)
  302. {
  303. struct device_node *child;
  304. struct tegra_mc_timing *timing;
  305. int child_count = of_get_child_count(node);
  306. int i = 0, err;
  307. mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
  308. GFP_KERNEL);
  309. if (!mc->timings)
  310. return -ENOMEM;
  311. mc->num_timings = child_count;
  312. for_each_child_of_node(node, child) {
  313. timing = &mc->timings[i++];
  314. err = load_one_timing(mc, timing, child);
  315. if (err) {
  316. of_node_put(child);
  317. return err;
  318. }
  319. }
  320. return 0;
  321. }
  322. static int tegra_mc_setup_timings(struct tegra_mc *mc)
  323. {
  324. struct device_node *node;
  325. u32 ram_code, node_ram_code;
  326. int err;
  327. ram_code = tegra_read_ram_code();
  328. mc->num_timings = 0;
  329. for_each_child_of_node(mc->dev->of_node, node) {
  330. err = of_property_read_u32(node, "nvidia,ram-code",
  331. &node_ram_code);
  332. if (err || (node_ram_code != ram_code))
  333. continue;
  334. err = load_timings(mc, node);
  335. of_node_put(node);
  336. if (err)
  337. return err;
  338. break;
  339. }
  340. if (mc->num_timings == 0)
  341. dev_warn(mc->dev,
  342. "no memory timings for RAM code %u registered\n",
  343. ram_code);
  344. return 0;
  345. }
  346. static const char *const status_names[32] = {
  347. [ 1] = "External interrupt",
  348. [ 6] = "EMEM address decode error",
  349. [ 7] = "GART page fault",
  350. [ 8] = "Security violation",
  351. [ 9] = "EMEM arbitration error",
  352. [10] = "Page fault",
  353. [11] = "Invalid APB ASID update",
  354. [12] = "VPR violation",
  355. [13] = "Secure carveout violation",
  356. [16] = "MTS carveout violation",
  357. };
  358. static const char *const error_names[8] = {
  359. [2] = "EMEM decode error",
  360. [3] = "TrustZone violation",
  361. [4] = "Carveout violation",
  362. [6] = "SMMU translation error",
  363. };
  364. static irqreturn_t tegra_mc_irq(int irq, void *data)
  365. {
  366. struct tegra_mc *mc = data;
  367. unsigned long status;
  368. unsigned int bit;
  369. /* mask all interrupts to avoid flooding */
  370. status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
  371. if (!status)
  372. return IRQ_NONE;
  373. for_each_set_bit(bit, &status, 32) {
  374. const char *error = status_names[bit] ?: "unknown";
  375. const char *client = "unknown", *desc;
  376. const char *direction, *secure;
  377. phys_addr_t addr = 0;
  378. unsigned int i;
  379. char perm[7];
  380. u8 id, type;
  381. u32 value;
  382. value = mc_readl(mc, MC_ERR_STATUS);
  383. #ifdef CONFIG_PHYS_ADDR_T_64BIT
  384. if (mc->soc->num_address_bits > 32) {
  385. addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
  386. MC_ERR_STATUS_ADR_HI_MASK);
  387. addr <<= 32;
  388. }
  389. #endif
  390. if (value & MC_ERR_STATUS_RW)
  391. direction = "write";
  392. else
  393. direction = "read";
  394. if (value & MC_ERR_STATUS_SECURITY)
  395. secure = "secure ";
  396. else
  397. secure = "";
  398. id = value & mc->soc->client_id_mask;
  399. for (i = 0; i < mc->soc->num_clients; i++) {
  400. if (mc->soc->clients[i].id == id) {
  401. client = mc->soc->clients[i].name;
  402. break;
  403. }
  404. }
  405. type = (value & MC_ERR_STATUS_TYPE_MASK) >>
  406. MC_ERR_STATUS_TYPE_SHIFT;
  407. desc = error_names[type];
  408. switch (value & MC_ERR_STATUS_TYPE_MASK) {
  409. case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
  410. perm[0] = ' ';
  411. perm[1] = '[';
  412. if (value & MC_ERR_STATUS_READABLE)
  413. perm[2] = 'R';
  414. else
  415. perm[2] = '-';
  416. if (value & MC_ERR_STATUS_WRITABLE)
  417. perm[3] = 'W';
  418. else
  419. perm[3] = '-';
  420. if (value & MC_ERR_STATUS_NONSECURE)
  421. perm[4] = '-';
  422. else
  423. perm[4] = 'S';
  424. perm[5] = ']';
  425. perm[6] = '\0';
  426. break;
  427. default:
  428. perm[0] = '\0';
  429. break;
  430. }
  431. value = mc_readl(mc, MC_ERR_ADR);
  432. addr |= value;
  433. dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
  434. client, secure, direction, &addr, error,
  435. desc, perm);
  436. }
  437. /* clear interrupts */
  438. mc_writel(mc, status, MC_INTSTATUS);
  439. return IRQ_HANDLED;
  440. }
  441. static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
  442. {
  443. struct tegra_mc *mc = data;
  444. unsigned long status;
  445. unsigned int bit;
  446. /* mask all interrupts to avoid flooding */
  447. status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
  448. if (!status)
  449. return IRQ_NONE;
  450. for_each_set_bit(bit, &status, 32) {
  451. const char *direction = "read", *secure = "";
  452. const char *error = status_names[bit];
  453. const char *client, *desc;
  454. phys_addr_t addr;
  455. u32 value, reg;
  456. u8 id, type;
  457. switch (BIT(bit)) {
  458. case MC_INT_DECERR_EMEM:
  459. reg = MC_DECERR_EMEM_OTHERS_STATUS;
  460. value = mc_readl(mc, reg);
  461. id = value & mc->soc->client_id_mask;
  462. desc = error_names[2];
  463. if (value & BIT(31))
  464. direction = "write";
  465. break;
  466. case MC_INT_INVALID_GART_PAGE:
  467. dev_err_ratelimited(mc->dev, "%s\n", error);
  468. continue;
  469. case MC_INT_SECURITY_VIOLATION:
  470. reg = MC_SECURITY_VIOLATION_STATUS;
  471. value = mc_readl(mc, reg);
  472. id = value & mc->soc->client_id_mask;
  473. type = (value & BIT(30)) ? 4 : 3;
  474. desc = error_names[type];
  475. secure = "secure ";
  476. if (value & BIT(31))
  477. direction = "write";
  478. break;
  479. default:
  480. continue;
  481. }
  482. client = mc->soc->clients[id].name;
  483. addr = mc_readl(mc, reg + sizeof(u32));
  484. dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
  485. client, secure, direction, &addr, error,
  486. desc);
  487. }
  488. /* clear interrupts */
  489. mc_writel(mc, status, MC_INTSTATUS);
  490. return IRQ_HANDLED;
  491. }
  492. static int tegra_mc_probe(struct platform_device *pdev)
  493. {
  494. const struct of_device_id *match;
  495. struct resource *res;
  496. struct tegra_mc *mc;
  497. void *isr;
  498. int err;
  499. match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
  500. if (!match)
  501. return -ENODEV;
  502. mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
  503. if (!mc)
  504. return -ENOMEM;
  505. platform_set_drvdata(pdev, mc);
  506. spin_lock_init(&mc->lock);
  507. mc->soc = match->data;
  508. mc->dev = &pdev->dev;
  509. /* length of MC tick in nanoseconds */
  510. mc->tick = 30;
  511. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  512. mc->regs = devm_ioremap_resource(&pdev->dev, res);
  513. if (IS_ERR(mc->regs))
  514. return PTR_ERR(mc->regs);
  515. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  516. if (mc->soc == &tegra20_mc_soc) {
  517. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  518. mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
  519. if (IS_ERR(mc->regs2))
  520. return PTR_ERR(mc->regs2);
  521. isr = tegra20_mc_irq;
  522. } else
  523. #endif
  524. {
  525. mc->clk = devm_clk_get(&pdev->dev, "mc");
  526. if (IS_ERR(mc->clk)) {
  527. dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
  528. PTR_ERR(mc->clk));
  529. return PTR_ERR(mc->clk);
  530. }
  531. err = tegra_mc_setup_latency_allowance(mc);
  532. if (err < 0) {
  533. dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
  534. err);
  535. return err;
  536. }
  537. isr = tegra_mc_irq;
  538. err = tegra_mc_setup_timings(mc);
  539. if (err < 0) {
  540. dev_err(&pdev->dev, "failed to setup timings: %d\n",
  541. err);
  542. return err;
  543. }
  544. }
  545. mc->irq = platform_get_irq(pdev, 0);
  546. if (mc->irq < 0) {
  547. dev_err(&pdev->dev, "interrupt not specified\n");
  548. return mc->irq;
  549. }
  550. WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
  551. mc_writel(mc, mc->soc->intmask, MC_INTMASK);
  552. err = devm_request_irq(&pdev->dev, mc->irq, isr, IRQF_SHARED,
  553. dev_name(&pdev->dev), mc);
  554. if (err < 0) {
  555. dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
  556. err);
  557. return err;
  558. }
  559. err = tegra_mc_reset_setup(mc);
  560. if (err < 0)
  561. dev_err(&pdev->dev, "failed to register reset controller: %d\n",
  562. err);
  563. if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
  564. mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
  565. if (IS_ERR(mc->smmu))
  566. dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
  567. PTR_ERR(mc->smmu));
  568. }
  569. return 0;
  570. }
  571. static struct platform_driver tegra_mc_driver = {
  572. .driver = {
  573. .name = "tegra-mc",
  574. .of_match_table = tegra_mc_of_match,
  575. .suppress_bind_attrs = true,
  576. },
  577. .prevent_deferred_probe = true,
  578. .probe = tegra_mc_probe,
  579. };
  580. static int tegra_mc_init(void)
  581. {
  582. return platform_driver_register(&tegra_mc_driver);
  583. }
  584. arch_initcall(tegra_mc_init);
  585. MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
  586. MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
  587. MODULE_LICENSE("GPL v2");