spi-nand-base.c 14 KB

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  1. /*
  2. * Copyright (C) 2014 Imagination Technologies Ltd.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * Notes:
  9. * 1. Erase and program operations need to call write_enable() first,
  10. * to clear the enable bit. This bit is cleared automatically after
  11. * the erase or program operation.
  12. *
  13. */
  14. #include <linux/device.h>
  15. #include <linux/err.h>
  16. #include <linux/errno.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/mtd/rawnand.h>
  20. #include <linux/mtd/mtd.h>
  21. #include <linux/mtd/partitions.h>
  22. #include <linux/mtd/spi-nand.h>
  23. #include <linux/of.h>
  24. #include <linux/slab.h>
  25. /* Registers common to all devices */
  26. #define SPI_NAND_LOCK_REG 0xa0
  27. #define SPI_NAND_PROT_UNLOCK_ALL 0x0
  28. #define SPI_NAND_FEATURE_REG 0xb0
  29. #define SPI_NAND_ECC_EN BIT(4)
  30. #define SPI_NAND_QUAD_EN BIT(0)
  31. #define SPI_NAND_STATUS_REG 0xc0
  32. #define SPI_NAND_STATUS_REG_ECC_MASK 0x3
  33. #define SPI_NAND_STATUS_REG_ECC_SHIFT 4
  34. #define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3)
  35. #define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2)
  36. #define SPI_NAND_STATUS_REG_WREN BIT(1)
  37. #define SPI_NAND_STATUS_REG_BUSY BIT(0)
  38. #define SPI_NAND_CMD_BUF_LEN 8
  39. /* Rewind and fill the buffer with 0xff */
  40. static void spi_nand_clear_buffer(struct spi_nand *snand)
  41. {
  42. snand->buf_start = 0;
  43. memset(snand->data_buf, 0xff, snand->buf_size);
  44. }
  45. static int spi_nand_enable_ecc(struct spi_nand *snand)
  46. {
  47. int ret;
  48. ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
  49. if (ret)
  50. return ret;
  51. snand->buf[0] |= SPI_NAND_ECC_EN;
  52. ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
  53. if (ret)
  54. return ret;
  55. snand->ecc = true;
  56. return 0;
  57. }
  58. static int spi_nand_disable_ecc(struct spi_nand *snand)
  59. {
  60. int ret;
  61. ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
  62. if (ret)
  63. return ret;
  64. snand->buf[0] &= ~SPI_NAND_ECC_EN;
  65. ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
  66. if (ret)
  67. return ret;
  68. snand->ecc = false;
  69. return 0;
  70. }
  71. static int spi_nand_enable_quad(struct spi_nand *snand)
  72. {
  73. int ret;
  74. ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
  75. if (ret)
  76. return ret;
  77. snand->buf[0] |= SPI_NAND_QUAD_EN;
  78. ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
  79. if (ret)
  80. return ret;
  81. return 0;
  82. }
  83. /*
  84. * Wait until the status register busy bit is cleared.
  85. * Returns a negatie errno on error or time out, and a non-negative status
  86. * value if the device is ready.
  87. */
  88. static int spi_nand_wait_till_ready(struct spi_nand *snand)
  89. {
  90. unsigned long deadline = jiffies + msecs_to_jiffies(100);
  91. bool timeout = false;
  92. int ret;
  93. /*
  94. * Perhaps we should set a different timeout for each
  95. * operation (reset, read, write, erase).
  96. */
  97. while (!timeout) {
  98. if (time_after_eq(jiffies, deadline))
  99. timeout = true;
  100. ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
  101. if (ret < 0) {
  102. dev_err(snand->dev, "error reading status register\n");
  103. return ret;
  104. } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) {
  105. return snand->buf[0];
  106. }
  107. cond_resched();
  108. }
  109. dev_err(snand->dev, "operation timed out\n");
  110. return -ETIMEDOUT;
  111. }
  112. static int spi_nand_reset(struct spi_nand *snand)
  113. {
  114. int ret;
  115. ret = snand->reset(snand);
  116. if (ret < 0) {
  117. dev_err(snand->dev, "reset command failed\n");
  118. return ret;
  119. }
  120. /*
  121. * The NAND core won't wait after a device reset, so we need
  122. * to do that here.
  123. */
  124. ret = spi_nand_wait_till_ready(snand);
  125. if (ret < 0)
  126. return ret;
  127. return 0;
  128. }
  129. static int spi_nand_status(struct spi_nand *snand)
  130. {
  131. int ret, status;
  132. ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
  133. if (ret < 0) {
  134. dev_err(snand->dev, "error reading status register\n");
  135. return ret;
  136. }
  137. status = snand->buf[0];
  138. /* Convert this into standard NAND_STATUS values */
  139. if (status & SPI_NAND_STATUS_REG_BUSY)
  140. snand->buf[0] = 0;
  141. else
  142. snand->buf[0] = NAND_STATUS_READY;
  143. if (status & SPI_NAND_STATUS_REG_PROG_FAIL ||
  144. status & SPI_NAND_STATUS_REG_ERASE_FAIL)
  145. snand->buf[0] |= NAND_STATUS_FAIL;
  146. /*
  147. * Since we unlock the entire device at initialization, unconditionally
  148. * set the WP bit to indicate it's not protected.
  149. */
  150. snand->buf[0] |= NAND_STATUS_WP;
  151. return 0;
  152. }
  153. static int spi_nand_erase(struct spi_nand *snand, int page_addr)
  154. {
  155. int ret;
  156. ret = snand->write_enable(snand);
  157. if (ret < 0) {
  158. dev_err(snand->dev, "write enable command failed\n");
  159. return ret;
  160. }
  161. ret = snand->block_erase(snand, page_addr);
  162. if (ret < 0) {
  163. dev_err(snand->dev, "block erase command failed\n");
  164. return ret;
  165. }
  166. return 0;
  167. }
  168. static int spi_nand_write(struct spi_nand *snand)
  169. {
  170. int ret;
  171. /* Enable quad mode */
  172. ret = spi_nand_enable_quad(snand);
  173. if (ret) {
  174. dev_err(snand->dev, "error %d enabling quad mode\n", ret);
  175. return ret;
  176. }
  177. /* Store the page to cache */
  178. ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf);
  179. if (ret < 0) {
  180. dev_err(snand->dev, "error %d storing page 0x%x to cache\n",
  181. ret, snand->page_addr);
  182. return ret;
  183. }
  184. ret = snand->write_enable(snand);
  185. if (ret < 0) {
  186. dev_err(snand->dev, "write enable command failed\n");
  187. return ret;
  188. }
  189. /* Get page from the device cache into our internal buffer */
  190. ret = snand->write_page(snand, snand->page_addr);
  191. if (ret < 0) {
  192. dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
  193. ret, snand->page_addr);
  194. return ret;
  195. }
  196. return 0;
  197. }
  198. static int spi_nand_read_id(struct spi_nand *snand)
  199. {
  200. int ret;
  201. ret = snand->read_id(snand, snand->data_buf);
  202. if (ret < 0) {
  203. dev_err(snand->dev, "error %d reading ID\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr,
  209. unsigned int page_offset, size_t length)
  210. {
  211. unsigned int corrected = 0, ecc_error = 0;
  212. int ret;
  213. /* Load a page into the cache register */
  214. ret = snand->load_page(snand, page_addr);
  215. if (ret < 0) {
  216. dev_err(snand->dev, "error %d loading page 0x%x to cache\n",
  217. ret, page_addr);
  218. return ret;
  219. }
  220. ret = spi_nand_wait_till_ready(snand);
  221. if (ret < 0)
  222. return ret;
  223. if (snand->ecc) {
  224. snand->get_ecc_status(ret, &corrected, &ecc_error);
  225. snand->bitflips = corrected;
  226. /*
  227. * If there's an ECC error, print a message and notify MTD
  228. * about it. Then complete the read, to load actual data on
  229. * the buffer (instead of the status result).
  230. */
  231. if (ecc_error) {
  232. dev_err(snand->dev,
  233. "internal ECC error reading page 0x%x\n",
  234. page_addr);
  235. snand->nand_chip.mtd.ecc_stats.failed++;
  236. } else {
  237. snand->nand_chip.mtd.ecc_stats.corrected += corrected;
  238. }
  239. }
  240. /* Enable quad mode */
  241. ret = spi_nand_enable_quad(snand);
  242. if (ret) {
  243. dev_err(snand->dev, "error %d enabling quad mode\n", ret);
  244. return ret;
  245. }
  246. /* Get page from the device cache into our internal buffer */
  247. ret = snand->read_cache(snand, page_offset, length, snand->data_buf);
  248. if (ret < 0) {
  249. dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
  250. ret, page_addr);
  251. return ret;
  252. }
  253. return 0;
  254. }
  255. static u8 spi_nand_read_byte(struct mtd_info *mtd)
  256. {
  257. struct nand_chip *chip = mtd_to_nand(mtd);
  258. struct spi_nand *snand = nand_get_controller_data(chip);
  259. char val = 0xff;
  260. if (snand->buf_start < snand->buf_size)
  261. val = snand->data_buf[snand->buf_start++];
  262. return val;
  263. }
  264. static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  265. {
  266. struct nand_chip *chip = mtd_to_nand(mtd);
  267. struct spi_nand *snand = nand_get_controller_data(chip);
  268. size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
  269. memcpy(snand->data_buf + snand->buf_start, buf, n);
  270. snand->buf_start += n;
  271. }
  272. static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  273. {
  274. struct nand_chip *chip = mtd_to_nand(mtd);
  275. struct spi_nand *snand = nand_get_controller_data(chip);
  276. size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
  277. memcpy(buf, snand->data_buf + snand->buf_start, n);
  278. snand->buf_start += n;
  279. }
  280. static int spi_nand_write_page_hwecc(struct mtd_info *mtd,
  281. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  282. int page)
  283. {
  284. chip->write_buf(mtd, buf, mtd->writesize);
  285. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  286. return 0;
  287. }
  288. static int spi_nand_read_page_hwecc(struct mtd_info *mtd,
  289. struct nand_chip *chip, uint8_t *buf, int oob_required,
  290. int page)
  291. {
  292. struct spi_nand *snand = nand_get_controller_data(chip);
  293. chip->read_buf(mtd, buf, mtd->writesize);
  294. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  295. return snand->bitflips;
  296. }
  297. static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
  298. {
  299. struct spi_nand *snand = nand_get_controller_data(chip);
  300. int ret;
  301. ret = spi_nand_wait_till_ready(snand);
  302. if (ret < 0) {
  303. return NAND_STATUS_FAIL;
  304. } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) {
  305. dev_err(snand->dev, "page program failed\n");
  306. return NAND_STATUS_FAIL;
  307. } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) {
  308. dev_err(snand->dev, "block erase failed\n");
  309. return NAND_STATUS_FAIL;
  310. }
  311. return NAND_STATUS_READY;
  312. }
  313. static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command,
  314. int column, int page_addr)
  315. {
  316. struct nand_chip *chip = mtd_to_nand(mtd);
  317. struct spi_nand *snand = nand_get_controller_data(chip);
  318. /*
  319. * In case there's any unsupported command, let's make sure
  320. * we don't keep garbage around in the buffer.
  321. */
  322. if (command != NAND_CMD_PAGEPROG) {
  323. spi_nand_clear_buffer(snand);
  324. snand->page_addr = 0;
  325. }
  326. switch (command) {
  327. case NAND_CMD_READ0:
  328. spi_nand_read_page(snand, page_addr, 0, mtd->writesize);
  329. break;
  330. case NAND_CMD_READOOB:
  331. spi_nand_disable_ecc(snand);
  332. spi_nand_read_page(snand, page_addr, mtd->writesize,
  333. mtd->oobsize);
  334. spi_nand_enable_ecc(snand);
  335. break;
  336. case NAND_CMD_READID:
  337. spi_nand_read_id(snand);
  338. break;
  339. case NAND_CMD_ERASE1:
  340. spi_nand_erase(snand, page_addr);
  341. break;
  342. case NAND_CMD_ERASE2:
  343. /* There's nothing to do here, as the erase is one-step */
  344. break;
  345. case NAND_CMD_SEQIN:
  346. snand->buf_start = column;
  347. snand->page_addr = page_addr;
  348. break;
  349. case NAND_CMD_PAGEPROG:
  350. spi_nand_write(snand);
  351. break;
  352. case NAND_CMD_STATUS:
  353. spi_nand_status(snand);
  354. break;
  355. case NAND_CMD_RESET:
  356. spi_nand_reset(snand);
  357. break;
  358. default:
  359. dev_err(&mtd->dev, "unknown command 0x%x\n", command);
  360. }
  361. }
  362. static void spi_nand_select_chip(struct mtd_info *mtd, int chip)
  363. {
  364. /* We need this to override the default */
  365. }
  366. int spi_nand_check(struct spi_nand *snand)
  367. {
  368. if (!snand->dev)
  369. return -ENODEV;
  370. if (!snand->read_cache)
  371. return -ENODEV;
  372. if (!snand->load_page)
  373. return -ENODEV;
  374. if (!snand->store_cache)
  375. return -ENODEV;
  376. if (!snand->write_page)
  377. return -ENODEV;
  378. if (!snand->write_reg)
  379. return -ENODEV;
  380. if (!snand->read_reg)
  381. return -ENODEV;
  382. if (!snand->block_erase)
  383. return -ENODEV;
  384. if (!snand->reset)
  385. return -ENODEV;
  386. if (!snand->write_enable)
  387. return -ENODEV;
  388. if (!snand->write_disable)
  389. return -ENODEV;
  390. if (!snand->get_ecc_status)
  391. return -ENODEV;
  392. return 0;
  393. }
  394. static int spi_nand_attach_chip(struct nand_chip *chip)
  395. {
  396. struct spi_nand *snand = nand_get_controller_data(chip);
  397. struct mtd_info *mtd = nand_to_mtd(chip);
  398. int ret;
  399. /*
  400. * SPI NAND has on-die ECC, which means we can correct as much as
  401. * we are required to. This must be done after identification of
  402. * the device.
  403. */
  404. chip->ecc.strength = chip->ecc_strength_ds;
  405. chip->ecc.size = chip->ecc_step_ds;
  406. /*
  407. * Unlock all the device before calling nand_scan_tail. This is needed
  408. * in case the in-flash bad block table needs to be created.
  409. * We could override __nand_unlock(), but since it's not currently used
  410. * by the NAND core we call this explicitly.
  411. */
  412. snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL;
  413. ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf);
  414. if (ret)
  415. return ret;
  416. /* Free the buffer and allocate a good one, to fit a page plus OOB */
  417. kfree(snand->data_buf);
  418. snand->buf_size = mtd->writesize + mtd->oobsize;
  419. snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
  420. if (!snand->data_buf)
  421. return -ENOMEM;
  422. return 0;
  423. }
  424. static const struct nand_controller_ops spi_nand_controller_ops = {
  425. .attach_chip = spi_nand_attach_chip,
  426. };
  427. int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids)
  428. {
  429. struct nand_chip *chip = &snand->nand_chip;
  430. struct mtd_info *mtd = nand_to_mtd(chip);
  431. struct device_node *np = snand->dev->of_node;
  432. const char __maybe_unused *of_mtd_name = NULL;
  433. int ret;
  434. /* Let's check all the hooks are in-place so we don't panic later */
  435. ret = spi_nand_check(snand);
  436. if (ret)
  437. return ret;
  438. nand_controller_init(&snand->controller);
  439. snand->controller.ops = &spi_nand_controller_ops;
  440. nand_set_controller_data(chip, snand);
  441. nand_set_flash_node(chip, np);
  442. chip->controller = &snand->controller;
  443. chip->read_buf = spi_nand_read_buf;
  444. chip->write_buf = spi_nand_write_buf;
  445. chip->read_byte = spi_nand_read_byte;
  446. chip->cmdfunc = spi_nand_cmdfunc;
  447. chip->waitfunc = spi_nand_waitfunc;
  448. chip->select_chip = spi_nand_select_chip;
  449. chip->options |= NAND_NO_SUBPAGE_WRITE;
  450. chip->bits_per_cell = 1;
  451. mtd_set_ooblayout(mtd, snand->ooblayout);
  452. chip->ecc.read_page = spi_nand_read_page_hwecc;
  453. chip->ecc.write_page = spi_nand_write_page_hwecc;
  454. chip->ecc.mode = NAND_ECC_HW;
  455. if (of_property_read_bool(np, "nand-on-flash-bbt"))
  456. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
  457. #ifdef CONFIG_MTD_OF_PARTS
  458. of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
  459. #endif
  460. if (of_mtd_name)
  461. mtd->name = of_mtd_name;
  462. else
  463. mtd->name = snand->name;
  464. mtd->owner = THIS_MODULE;
  465. /* Allocate buffer to be used to read/write the internal registers */
  466. snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL);
  467. if (!snand->buf)
  468. return -ENOMEM;
  469. /* This is enabled at device power up but we'd better make sure */
  470. ret = spi_nand_enable_ecc(snand);
  471. if (ret)
  472. return ret;
  473. /* Preallocate buffer for flash identification (NAND_CMD_READID) */
  474. snand->buf_size = SPI_NAND_CMD_BUF_LEN;
  475. snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
  476. ret = nand_scan_with_ids(chip, 1, flash_ids);
  477. if (ret)
  478. return ret;
  479. return mtd_device_register(mtd, NULL, 0);
  480. }
  481. EXPORT_SYMBOL_GPL(spi_nand_register);
  482. void spi_nand_unregister(struct spi_nand *snand)
  483. {
  484. kfree(snand->buf);
  485. kfree(snand->data_buf);
  486. }
  487. EXPORT_SYMBOL_GPL(spi_nand_unregister);
  488. MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>");
  489. MODULE_DESCRIPTION("Framework for SPI NAND");
  490. MODULE_LICENSE("GPL v2");