spi-nand-device.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494
  1. /*
  2. * Copyright (C) 2014 Imagination Technologies Ltd.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * Notes:
  9. * 1. We avoid using a stack-allocated buffer for SPI messages. Using
  10. * a kmalloced buffer is probably better, given we shouldn't assume
  11. * any particular usage by SPI core.
  12. */
  13. #include <linux/device.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/module.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/partitions.h>
  19. #include <linux/mtd/spi-nand.h>
  20. #include <linux/sizes.h>
  21. #include <linux/spi/spi.h>
  22. /* SPI NAND commands */
  23. #define SPI_NAND_WRITE_ENABLE 0x06
  24. #define SPI_NAND_WRITE_DISABLE 0x04
  25. #define SPI_NAND_GET_FEATURE 0x0f
  26. #define SPI_NAND_SET_FEATURE 0x1f
  27. #define SPI_NAND_PAGE_READ 0x13
  28. #define SPI_NAND_READ_CACHE 0x03
  29. #define SPI_NAND_FAST_READ_CACHE 0x0b
  30. #define SPI_NAND_READ_CACHE_X2 0x3b
  31. #define SPI_NAND_READ_CACHE_X4 0x6b
  32. #define SPI_NAND_READ_CACHE_DUAL_IO 0xbb
  33. #define SPI_NAND_READ_CACHE_QUAD_IO 0xeb
  34. #define SPI_NAND_READ_ID 0x9f
  35. #define SPI_NAND_PROGRAM_LOAD 0x02
  36. #define SPI_NAND_PROGRAM_LOAD4 0x32
  37. #define SPI_NAND_PROGRAM_EXEC 0x10
  38. #define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84
  39. #define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4
  40. #define SPI_NAND_BLOCK_ERASE 0xd8
  41. #define SPI_NAND_RESET 0xff
  42. #define SPI_NAND_GD5F_READID_LEN 2
  43. #define SPI_NAND_GD5F_ECC_MASK (BIT(0) | BIT(1) | BIT(2))
  44. #define SPI_NAND_GD5F_ECC_UNCORR (BIT(0) | BIT(1) | BIT(2))
  45. #define SPI_NAND_GD5F_ECC_SHIFT 4
  46. static int spi_nand_gd5f_ooblayout_256_ecc(struct mtd_info *mtd, int section,
  47. struct mtd_oob_region *oobregion)
  48. {
  49. if (section)
  50. return -ERANGE;
  51. oobregion->offset = 128;
  52. oobregion->length = 128;
  53. return 0;
  54. }
  55. static int spi_nand_gd5f_ooblayout_256_free(struct mtd_info *mtd, int section,
  56. struct mtd_oob_region *oobregion)
  57. {
  58. if (section)
  59. return -ERANGE;
  60. oobregion->offset = 1;
  61. oobregion->length = 127;
  62. return 0;
  63. }
  64. static struct mtd_ooblayout_ops spi_nand_gd5f_oob_256_ops = {
  65. .ecc = spi_nand_gd5f_ooblayout_256_ecc,
  66. .free = spi_nand_gd5f_ooblayout_256_free,
  67. };
  68. static struct nand_flash_dev spi_nand_flash_ids[] = {
  69. {
  70. .name = "SPI NAND 512MiB 3,3V",
  71. .id = { NAND_MFR_GIGADEVICE, 0xb4 },
  72. .chipsize = 512,
  73. .pagesize = SZ_4K,
  74. .erasesize = SZ_256K,
  75. .id_len = 2,
  76. .oobsize = 256,
  77. .ecc.strength_ds = 8,
  78. .ecc.step_ds = 512,
  79. },
  80. {
  81. .name = "SPI NAND 512MiB 1,8V",
  82. .id = { NAND_MFR_GIGADEVICE, 0xa4 },
  83. .chipsize = 512,
  84. .pagesize = SZ_4K,
  85. .erasesize = SZ_256K,
  86. .id_len = 2,
  87. .oobsize = 256,
  88. .ecc.strength_ds = 8,
  89. .ecc.step_ds = 512,
  90. },
  91. {
  92. .name = "SPI NAND 128MiB 3,3V",
  93. .id = { NAND_MFR_GIGADEVICE, 0xd1 },
  94. .chipsize = 128,
  95. .pagesize = SZ_2K,
  96. .erasesize = SZ_128K,
  97. .id_len = 2,
  98. .oobsize = 128,
  99. .ecc.strength_ds = 8,
  100. .ecc.step_ds = 512,
  101. },
  102. {
  103. .name = "SPI NAND 128MiB 1,8V",
  104. .id = { NAND_MFR_GIGADEVICE, 0xc1 },
  105. .chipsize = 128,
  106. .pagesize = SZ_2K,
  107. .erasesize = SZ_128K,
  108. .id_len = 2,
  109. .oobsize = 128,
  110. .ecc.strength_ds = 8,
  111. .ecc.step_ds = 512,
  112. },
  113. };
  114. enum spi_nand_device_variant {
  115. SPI_NAND_GENERIC,
  116. SPI_NAND_GD5F,
  117. };
  118. struct spi_nand_device_cmd {
  119. /*
  120. * Command and address. I/O errors have been observed if a
  121. * separate spi_transfer is used for command and address,
  122. * so keep them together.
  123. */
  124. u32 n_cmd;
  125. u8 cmd[5];
  126. /* Tx data */
  127. u32 n_tx;
  128. u8 *tx_buf;
  129. /* Rx data */
  130. u32 n_rx;
  131. u8 *rx_buf;
  132. u8 rx_nbits;
  133. u8 tx_nbits;
  134. };
  135. struct spi_nand_device {
  136. struct spi_nand spi_nand;
  137. struct spi_device *spi;
  138. struct spi_nand_device_cmd cmd;
  139. };
  140. static int spi_nand_send_command(struct spi_device *spi,
  141. struct spi_nand_device_cmd *cmd)
  142. {
  143. struct spi_message message;
  144. struct spi_transfer x[2];
  145. if (!cmd->n_cmd) {
  146. dev_err(&spi->dev, "cannot send an empty command\n");
  147. return -EINVAL;
  148. }
  149. if (cmd->n_tx && cmd->n_rx) {
  150. dev_err(&spi->dev, "cannot send and receive data at the same time\n");
  151. return -EINVAL;
  152. }
  153. spi_message_init(&message);
  154. memset(x, 0, sizeof(x));
  155. /* Command and address */
  156. x[0].len = cmd->n_cmd;
  157. x[0].tx_buf = cmd->cmd;
  158. x[0].tx_nbits = cmd->tx_nbits;
  159. spi_message_add_tail(&x[0], &message);
  160. /* Data to be transmitted */
  161. if (cmd->n_tx) {
  162. x[1].len = cmd->n_tx;
  163. x[1].tx_buf = cmd->tx_buf;
  164. x[1].tx_nbits = cmd->tx_nbits;
  165. spi_message_add_tail(&x[1], &message);
  166. }
  167. /* Data to be received */
  168. if (cmd->n_rx) {
  169. x[1].len = cmd->n_rx;
  170. x[1].rx_buf = cmd->rx_buf;
  171. x[1].rx_nbits = cmd->rx_nbits;
  172. spi_message_add_tail(&x[1], &message);
  173. }
  174. return spi_sync(spi, &message);
  175. }
  176. static int spi_nand_device_reset(struct spi_nand *snand)
  177. {
  178. struct spi_nand_device *snand_dev = snand->priv;
  179. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  180. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  181. cmd->n_cmd = 1;
  182. cmd->cmd[0] = SPI_NAND_RESET;
  183. dev_dbg(snand->dev, "%s\n", __func__);
  184. return spi_nand_send_command(snand_dev->spi, cmd);
  185. }
  186. static int spi_nand_device_read_reg(struct spi_nand *snand, u8 opcode, u8 *buf)
  187. {
  188. struct spi_nand_device *snand_dev = snand->priv;
  189. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  190. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  191. cmd->n_cmd = 2;
  192. cmd->cmd[0] = SPI_NAND_GET_FEATURE;
  193. cmd->cmd[1] = opcode;
  194. cmd->n_rx = 1;
  195. cmd->rx_buf = buf;
  196. dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode);
  197. return spi_nand_send_command(snand_dev->spi, cmd);
  198. }
  199. static int spi_nand_device_write_reg(struct spi_nand *snand, u8 opcode, u8 *buf)
  200. {
  201. struct spi_nand_device *snand_dev = snand->priv;
  202. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  203. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  204. cmd->n_cmd = 2;
  205. cmd->cmd[0] = SPI_NAND_SET_FEATURE;
  206. cmd->cmd[1] = opcode;
  207. cmd->n_tx = 1;
  208. cmd->tx_buf = buf;
  209. dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode);
  210. return spi_nand_send_command(snand_dev->spi, cmd);
  211. }
  212. static int spi_nand_device_write_enable(struct spi_nand *snand)
  213. {
  214. struct spi_nand_device *snand_dev = snand->priv;
  215. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  216. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  217. cmd->n_cmd = 1;
  218. cmd->cmd[0] = SPI_NAND_WRITE_ENABLE;
  219. dev_dbg(snand->dev, "%s\n", __func__);
  220. return spi_nand_send_command(snand_dev->spi, cmd);
  221. }
  222. static int spi_nand_device_write_disable(struct spi_nand *snand)
  223. {
  224. struct spi_nand_device *snand_dev = snand->priv;
  225. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  226. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  227. cmd->n_cmd = 1;
  228. cmd->cmd[0] = SPI_NAND_WRITE_DISABLE;
  229. dev_dbg(snand->dev, "%s\n", __func__);
  230. return spi_nand_send_command(snand_dev->spi, cmd);
  231. }
  232. static int spi_nand_device_write_page(struct spi_nand *snand,
  233. unsigned int page_addr)
  234. {
  235. struct spi_nand_device *snand_dev = snand->priv;
  236. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  237. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  238. cmd->n_cmd = 4;
  239. cmd->cmd[0] = SPI_NAND_PROGRAM_EXEC;
  240. cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16);
  241. cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8);
  242. cmd->cmd[3] = (u8)(page_addr & 0xff);
  243. dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr);
  244. return spi_nand_send_command(snand_dev->spi, cmd);
  245. }
  246. static int spi_nand_device_store_cache(struct spi_nand *snand,
  247. unsigned int page_offset, size_t length,
  248. u8 *write_buf)
  249. {
  250. struct spi_nand_device *snand_dev = snand->priv;
  251. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  252. struct spi_device *spi = snand_dev->spi;
  253. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  254. cmd->n_cmd = 3;
  255. cmd->cmd[0] = spi->mode & SPI_TX_QUAD ? SPI_NAND_PROGRAM_LOAD4 :
  256. SPI_NAND_PROGRAM_LOAD;
  257. cmd->cmd[1] = (u8)((page_offset & 0xff00) >> 8);
  258. cmd->cmd[2] = (u8)(page_offset & 0xff);
  259. cmd->n_tx = length;
  260. cmd->tx_buf = write_buf;
  261. cmd->tx_nbits = spi->mode & SPI_TX_QUAD ? 4 : 1;
  262. dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset);
  263. return spi_nand_send_command(snand_dev->spi, cmd);
  264. }
  265. static int spi_nand_device_load_page(struct spi_nand *snand,
  266. unsigned int page_addr)
  267. {
  268. struct spi_nand_device *snand_dev = snand->priv;
  269. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  270. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  271. cmd->n_cmd = 4;
  272. cmd->cmd[0] = SPI_NAND_PAGE_READ;
  273. cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16);
  274. cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8);
  275. cmd->cmd[3] = (u8)(page_addr & 0xff);
  276. dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr);
  277. return spi_nand_send_command(snand_dev->spi, cmd);
  278. }
  279. static int spi_nand_device_read_cache(struct spi_nand *snand,
  280. unsigned int page_offset, size_t length,
  281. u8 *read_buf)
  282. {
  283. struct spi_nand_device *snand_dev = snand->priv;
  284. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  285. struct spi_device *spi = snand_dev->spi;
  286. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  287. if ((spi->mode & SPI_RX_DUAL) || (spi->mode & SPI_RX_QUAD))
  288. cmd->n_cmd = 5;
  289. else
  290. cmd->n_cmd = 4;
  291. cmd->cmd[0] = (spi->mode & SPI_RX_QUAD) ? SPI_NAND_READ_CACHE_X4 :
  292. ((spi->mode & SPI_RX_DUAL) ? SPI_NAND_READ_CACHE_X2 :
  293. SPI_NAND_READ_CACHE);
  294. cmd->cmd[1] = 0; /* dummy byte */
  295. cmd->cmd[2] = (u8)((page_offset & 0xff00) >> 8);
  296. cmd->cmd[3] = (u8)(page_offset & 0xff);
  297. cmd->cmd[4] = 0; /* dummy byte */
  298. cmd->n_rx = length;
  299. cmd->rx_buf = read_buf;
  300. cmd->rx_nbits = (spi->mode & SPI_RX_QUAD) ? 4 :
  301. ((spi->mode & SPI_RX_DUAL) ? 2 : 1);
  302. dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset);
  303. return spi_nand_send_command(snand_dev->spi, cmd);
  304. }
  305. static int spi_nand_device_block_erase(struct spi_nand *snand,
  306. unsigned int page_addr)
  307. {
  308. struct spi_nand_device *snand_dev = snand->priv;
  309. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  310. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  311. cmd->n_cmd = 4;
  312. cmd->cmd[0] = SPI_NAND_BLOCK_ERASE;
  313. cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16);
  314. cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8);
  315. cmd->cmd[3] = (u8)(page_addr & 0xff);
  316. dev_dbg(snand->dev, "%s: block 0x%x\n", __func__, page_addr);
  317. return spi_nand_send_command(snand_dev->spi, cmd);
  318. }
  319. static int spi_nand_gd5f_read_id(struct spi_nand *snand, u8 *buf)
  320. {
  321. struct spi_nand_device *snand_dev = snand->priv;
  322. struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
  323. memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
  324. cmd->n_cmd = 2;
  325. cmd->cmd[0] = SPI_NAND_READ_ID;
  326. cmd->cmd[1] = 0;
  327. cmd->n_rx = SPI_NAND_GD5F_READID_LEN;
  328. cmd->rx_buf = buf;
  329. dev_dbg(snand->dev, "%s\n", __func__);
  330. return spi_nand_send_command(snand_dev->spi, cmd);
  331. }
  332. static void spi_nand_gd5f_ecc_status(unsigned int status,
  333. unsigned int *corrected,
  334. unsigned int *ecc_error)
  335. {
  336. unsigned int ecc_status = (status >> SPI_NAND_GD5F_ECC_SHIFT) &
  337. SPI_NAND_GD5F_ECC_MASK;
  338. *ecc_error = (ecc_status == SPI_NAND_GD5F_ECC_UNCORR) ? 1 : 0;
  339. if (*ecc_error == 0)
  340. *corrected = (ecc_status > 1) ? (2 + ecc_status) : 0;
  341. }
  342. static int spi_nand_device_probe(struct spi_device *spi)
  343. {
  344. enum spi_nand_device_variant variant;
  345. struct spi_nand_device *priv;
  346. struct spi_nand *snand;
  347. int ret;
  348. priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
  349. if (!priv)
  350. return -ENOMEM;
  351. snand = &priv->spi_nand;
  352. snand->read_cache = spi_nand_device_read_cache;
  353. snand->load_page = spi_nand_device_load_page;
  354. snand->store_cache = spi_nand_device_store_cache;
  355. snand->write_page = spi_nand_device_write_page;
  356. snand->write_reg = spi_nand_device_write_reg;
  357. snand->read_reg = spi_nand_device_read_reg;
  358. snand->block_erase = spi_nand_device_block_erase;
  359. snand->reset = spi_nand_device_reset;
  360. snand->write_enable = spi_nand_device_write_enable;
  361. snand->write_disable = spi_nand_device_write_disable;
  362. snand->dev = &spi->dev;
  363. snand->priv = priv;
  364. /* This'll mean we won't need to specify any specific compatible string
  365. * for a given device, and instead just support spi-nand.
  366. */
  367. variant = spi_get_device_id(spi)->driver_data;
  368. switch (variant) {
  369. case SPI_NAND_GD5F:
  370. snand->read_id = spi_nand_gd5f_read_id;
  371. snand->get_ecc_status = spi_nand_gd5f_ecc_status;
  372. snand->ooblayout = &spi_nand_gd5f_oob_256_ops;
  373. break;
  374. default:
  375. dev_err(snand->dev, "unknown device\n");
  376. return -ENODEV;
  377. }
  378. spi_set_drvdata(spi, snand);
  379. priv->spi = spi;
  380. ret = spi_nand_register(snand, spi_nand_flash_ids);
  381. if (ret)
  382. return ret;
  383. return 0;
  384. }
  385. static int spi_nand_device_remove(struct spi_device *spi)
  386. {
  387. struct spi_nand *snand = spi_get_drvdata(spi);
  388. spi_nand_unregister(snand);
  389. return 0;
  390. }
  391. const struct spi_device_id spi_nand_id_table[] = {
  392. { "spi-nand", SPI_NAND_GENERIC },
  393. { "gd5f", SPI_NAND_GD5F },
  394. { },
  395. };
  396. MODULE_DEVICE_TABLE(spi, spi_nand_id_table);
  397. static struct spi_driver spi_nand_device_driver = {
  398. .driver = {
  399. .name = "spi_nand_device",
  400. .owner = THIS_MODULE,
  401. },
  402. .id_table = spi_nand_id_table,
  403. .probe = spi_nand_device_probe,
  404. .remove = spi_nand_device_remove,
  405. };
  406. module_spi_driver(spi_nand_device_driver);
  407. MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>");
  408. MODULE_DESCRIPTION("SPI NAND device support");
  409. MODULE_LICENSE("GPL v2");