pinctrl-aspeed.h 25 KB

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  1. /*
  2. * Copyright (C) 2016 IBM Corp.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9. #ifndef PINCTRL_ASPEED
  10. #define PINCTRL_ASPEED
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include <linux/pinctrl/pinmux.h>
  13. #include <linux/pinctrl/pinconf.h>
  14. #include <linux/pinctrl/pinconf-generic.h>
  15. #include <linux/regmap.h>
  16. /*
  17. * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
  18. * functions. The SoC function enabled on a pin is determined on a priority
  19. * basis where a given pin can provide a number of different signal types.
  20. *
  21. * The signal active on a pin is described by both a priority level and
  22. * compound logical expressions involving multiple operators, registers and
  23. * bits. Some difficulty arises as the pin's function bit masks for each
  24. * priority level are frequently not the same (i.e. cannot just flip a bit to
  25. * change from a high to low priority signal), or even in the same register.
  26. * Further, not all signals can be unmuxed, as some expressions depend on
  27. * values in the hardware strapping register (which is treated as read-only).
  28. *
  29. * SoC Multi-function Pin Expression Examples
  30. * ------------------------------------------
  31. *
  32. * Here are some sample mux configurations from the AST2400 and AST2500
  33. * datasheets to illustrate the corner cases, roughly in order of least to most
  34. * corner. The signal priorities are in decending order from P0 (highest).
  35. *
  36. * D6 is a pin with a single function (beside GPIO); a high priority signal
  37. * that participates in one function:
  38. *
  39. * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
  40. * -----+---------+-----------+-----------------------------+-----------+---------------+----------
  41. * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
  42. * -----+---------+-----------+-----------------------------+-----------+---------------+----------
  43. *
  44. * C5 is a multi-signal pin (high and low priority signals). Here we touch
  45. * different registers for the different functions that enable each signal:
  46. *
  47. * -----+---------+-----------+-----------------------------+-----------+---------------+----------
  48. * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
  49. * -----+---------+-----------+-----------------------------+-----------+---------------+----------
  50. *
  51. * E19 is a single-signal pin with two functions that influence the active
  52. * signal. In this case both bits have the same meaning - enable a dedicated
  53. * LPC reset pin. However it's not always the case that the bits in the
  54. * OR-relationship have the same meaning.
  55. *
  56. * -----+---------+-----------+-----------------------------+-----------+---------------+----------
  57. * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
  58. * -----+---------+-----------+-----------------------------+-----------+---------------+----------
  59. *
  60. * For example, pin B19 has a low-priority signal that's enabled by two
  61. * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
  62. * bit in the STRAP register. The ACPI bit configures signals on pins in
  63. * addition to B19. Both of the low priority functions as well as the high
  64. * priority function must be disabled for GPIOF1 to be used.
  65. *
  66. * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
  67. * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
  68. * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
  69. * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
  70. *
  71. * For pin E18, the SoC ANDs the expected state of three bits to determine the
  72. * pin's active signal:
  73. *
  74. * * SCU3C[3]: Enable external SOC reset function
  75. * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
  76. * * SCU90[31]: Select SPI interface CS# output
  77. *
  78. * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
  79. * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
  80. * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
  81. *
  82. * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
  83. * selecting the signals on pin E18)
  84. *
  85. * Pin T5 is a multi-signal pin with a more complex configuration:
  86. *
  87. * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
  88. * -----+---------+-----------+------------------------------+-----------+---------------+----------
  89. * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
  90. * -----+---------+-----------+------------------------------+-----------+---------------+----------
  91. *
  92. * The high priority signal configuration is best thought of in terms of its
  93. * exploded form, with reference to the SCU90[5:4] bits:
  94. *
  95. * * SCU90[5:4]=00: disable
  96. * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
  97. * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
  98. * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
  99. *
  100. * Re-writing:
  101. *
  102. * -----+---------+-----------+------------------------------+-----------+---------------+----------
  103. * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
  104. * | (SCU90[5:4]=2 & SCU84[17]=1)
  105. * | (SCU90[5:4]=3 & SCU84[17]=1)
  106. * -----+---------+-----------+------------------------------+-----------+---------------+----------
  107. *
  108. * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
  109. * function pin", where the signal itself is determined by whether SCU94[5:4]
  110. * is disabled or in one of the 18, 24 or 30bit video modes.
  111. *
  112. * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
  113. * W1 and U5:
  114. *
  115. * -----+---------+-----------+------------------------------+-----------+---------------+----------
  116. * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
  117. * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
  118. * -----+---------+-----------+------------------------------+-----------+---------------+----------
  119. *
  120. * The examples of T5 and W1 are particularly fertile, as they also demonstrate
  121. * that despite operating as part of the video input bus each signal needs to
  122. * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
  123. * register bit. This is a little crazy if the bus doesn't have optional
  124. * signals, but is used to decent effect with some of the UARTs where not all
  125. * signals are required. However, this isn't done consistently - UART1 is
  126. * enabled on a per-pin basis, and by contrast, all signals for UART6 are
  127. * enabled by a single bit.
  128. *
  129. * Further, the high and low priority signals listed in the table above share
  130. * a configuration bit. The VPI signals should operate in concert in a single
  131. * function, but the UART signals should retain the ability to be configured
  132. * independently. This pushes the implementation down the path of tagging a
  133. * signal's expressions with the function they participate in, rather than
  134. * defining masks affecting multiple signals per function. The latter approach
  135. * fails in this instance where applying the configuration for the UART pin of
  136. * interest will stomp on the state of other UART signals when disabling the
  137. * VPI functions on the current pin.
  138. *
  139. * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
  140. * -----+------------+-----------+---------------------------+-----------+---------------+------------
  141. * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
  142. * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
  143. * -----+------------+-----------+---------------------------+-----------+---------------+------------
  144. *
  145. * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
  146. * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
  147. * should be treated like any other signal type with full function expression
  148. * requirements, and not assumed to be the default case. Separately, GPIOT0 and
  149. * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
  150. * pins in the function's group to disable the higher-priority signals such
  151. * that the signal for the function of interest is correctly enabled.
  152. *
  153. * Finally, three priority levels aren't always enough; the AST2500 brings with
  154. * it 18 pins of five priority levels, however the 18 pins only use three of
  155. * the five priority levels.
  156. *
  157. * Ultimately the requirement to control pins in the examples above drive the
  158. * design:
  159. *
  160. * * Pins provide signals according to functions activated in the mux
  161. * configuration
  162. *
  163. * * Pins provide up to five signal types in a priority order
  164. *
  165. * * For priorities levels defined on a pin, each priority provides one signal
  166. *
  167. * * Enabling lower priority signals requires higher priority signals be
  168. * disabled
  169. *
  170. * * A function represents a set of signals; functions are distinct if their
  171. * sets of signals are not equal
  172. *
  173. * * Signals participate in one or more functions
  174. *
  175. * * A function is described by an expression of one or more signal
  176. * descriptors, which compare bit values in a register
  177. *
  178. * * A signal expression is the smallest set of signal descriptors whose
  179. * comparisons must evaluate 'true' for a signal to be enabled on a pin.
  180. *
  181. * * A function's signal is active on a pin if evaluating all signal
  182. * descriptors in the pin's signal expression for the function yields a 'true'
  183. * result
  184. *
  185. * * A signal at a given priority on a given pin is active if any of the
  186. * functions in which the signal participates are active, and no higher
  187. * priority signal on the pin is active
  188. *
  189. * * GPIO is configured per-pin
  190. *
  191. * And so:
  192. *
  193. * * To disable a signal, any function(s) activating the signal must be
  194. * disabled
  195. *
  196. * * Each pin must know the signal expressions of functions in which it
  197. * participates, for the purpose of enabling the Other function. This is done
  198. * by deactivating all functions that activate higher priority signals on the
  199. * pin.
  200. *
  201. * As a concrete example:
  202. *
  203. * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
  204. *
  205. * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
  206. *
  207. * * The NDCD1 signal participates in just its own NDCD1 function
  208. *
  209. * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
  210. * prioritised
  211. *
  212. * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
  213. * and VPI30 functions all be disabled
  214. *
  215. * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
  216. * to provide GPIOL6
  217. *
  218. * Considerations
  219. * --------------
  220. *
  221. * If pinctrl allows us to allocate a pin we can configure a function without
  222. * concern for the function of already allocated pins, if pin groups are
  223. * created with respect to the SoC functions in which they participate. This is
  224. * intuitive, but it did not feel obvious from the bit/pin relationships.
  225. *
  226. * Conversely, failing to allocate all pins in a group indicates some bits (as
  227. * well as pins) required for the group's configuration will already be in use,
  228. * likely in a way that's inconsistent with the requirements of the failed
  229. * group.
  230. */
  231. #define ASPEED_IP_SCU 0
  232. #define ASPEED_IP_GFX 1
  233. #define ASPEED_IP_LPC 2
  234. #define ASPEED_NR_PINMUX_IPS 3
  235. /*
  236. * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
  237. * references registers by the device/offset mnemonic. The register macros
  238. * below are named the same way to ease transcription and verification (as
  239. * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
  240. * reference registers beyond those dedicated to pinmux, such as the system
  241. * reset control and MAC clock configuration registers. The AST2500 goes a step
  242. * further and references registers in the graphics IP block, but that isn't
  243. * handled yet.
  244. */
  245. #define SCU2C 0x2C /* Misc. Control Register */
  246. #define SCU3C 0x3C /* System Reset Control/Status Register */
  247. #define SCU48 0x48 /* MAC Interface Clock Delay Setting */
  248. #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
  249. #define HW_REVISION_ID 0x7C /* Silicon revision ID register */
  250. #define SCU80 0x80 /* Multi-function Pin Control #1 */
  251. #define SCU84 0x84 /* Multi-function Pin Control #2 */
  252. #define SCU88 0x88 /* Multi-function Pin Control #3 */
  253. #define SCU8C 0x8C /* Multi-function Pin Control #4 */
  254. #define SCU90 0x90 /* Multi-function Pin Control #5 */
  255. #define SCU94 0x94 /* Multi-function Pin Control #6 */
  256. #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
  257. #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
  258. #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
  259. #define SCUAC 0xAC /* Multi-function Pin Control #10 */
  260. #define HW_STRAP2 0xD0 /* Strapping */
  261. /**
  262. * A signal descriptor, which describes the register, bits and the
  263. * enable/disable values that should be compared or written.
  264. *
  265. * @ip: The IP block identifier, used as an index into the regmap array in
  266. * struct aspeed_pinctrl_data
  267. * @reg: The register offset with respect to the base address of the IP block
  268. * @mask: The mask to apply to the register. The lowest set bit of the mask is
  269. * used to derive the shift value.
  270. * @enable: The value that enables the function. Value should be in the LSBs,
  271. * not at the position of the mask.
  272. * @disable: The value that disables the function. Value should be in the
  273. * LSBs, not at the position of the mask.
  274. */
  275. struct aspeed_sig_desc {
  276. unsigned int ip;
  277. unsigned int reg;
  278. u32 mask;
  279. u32 enable;
  280. u32 disable;
  281. };
  282. /**
  283. * Describes a signal expression. The expression is evaluated by ANDing the
  284. * evaluation of the descriptors.
  285. *
  286. * @signal: The signal name for the priority level on the pin. If the signal
  287. * type is GPIO, then the signal name must begin with the string
  288. * "GPIO", e.g. GPIOA0, GPIOT4 etc.
  289. * @function: The name of the function the signal participates in for the
  290. * associated expression
  291. * @ndescs: The number of signal descriptors in the expression
  292. * @descs: Pointer to an array of signal descriptors that comprise the
  293. * function expression
  294. */
  295. struct aspeed_sig_expr {
  296. const char *signal;
  297. const char *function;
  298. int ndescs;
  299. const struct aspeed_sig_desc *descs;
  300. };
  301. /**
  302. * A struct capturing the list of expressions enabling signals at each priority
  303. * for a given pin. The signal configuration for a priority level is evaluated
  304. * by ORing the evaluation of the signal expressions in the respective
  305. * priority's list.
  306. *
  307. * @name: A name for the pin
  308. * @prios: A pointer to an array of expression list pointers
  309. *
  310. */
  311. struct aspeed_pin_desc {
  312. const char *name;
  313. const struct aspeed_sig_expr ***prios;
  314. };
  315. /* Macro hell */
  316. #define SIG_DESC_IP_BIT(ip, reg, idx, val) \
  317. { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
  318. /**
  319. * Short-hand macro for describing an SCU descriptor enabled by the state of
  320. * one bit. The disable value is derived.
  321. *
  322. * @reg: The signal's associated register, offset from base
  323. * @idx: The signal's bit index in the register
  324. * @val: The value (0 or 1) that enables the function
  325. */
  326. #define SIG_DESC_BIT(reg, idx, val) \
  327. SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
  328. #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
  329. /**
  330. * A further short-hand macro expanding to an SCU descriptor enabled by a set
  331. * bit.
  332. *
  333. * @reg: The register, offset from base
  334. * @idx: The bit index in the register
  335. */
  336. #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
  337. #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
  338. #define SIG_DESC_LIST_DECL(sig, func, ...) \
  339. static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
  340. { __VA_ARGS__ }
  341. #define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
  342. #define SIG_EXPR_DECL_(sig, func) \
  343. static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
  344. { \
  345. .signal = #sig, \
  346. .function = #func, \
  347. .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
  348. .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
  349. }
  350. /**
  351. * Declare a signal expression.
  352. *
  353. * @sig: A macro symbol name for the signal (is subjected to stringification
  354. * and token pasting)
  355. * @func: The function in which the signal is participating
  356. * @...: Signal descriptors that define the signal expression
  357. *
  358. * For example, the following declares the ROMD8 signal for the ROM16 function:
  359. *
  360. * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
  361. *
  362. * And with multiple signal descriptors:
  363. *
  364. * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
  365. * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
  366. */
  367. #define SIG_EXPR_DECL(sig, func, ...) \
  368. SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
  369. SIG_EXPR_DECL_(sig, func)
  370. /**
  371. * Declare a pointer to a signal expression
  372. *
  373. * @sig: The macro symbol name for the signal (subjected to token pasting)
  374. * @func: The macro symbol name for the function (subjected to token pasting)
  375. */
  376. #define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
  377. #define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
  378. /**
  379. * Declare a signal expression list for reference in a struct aspeed_pin_prio.
  380. *
  381. * @sig: A macro symbol name for the signal (is subjected to token pasting)
  382. * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
  383. *
  384. * For example, the 16-bit ROM bus can be enabled by one of two possible signal
  385. * expressions:
  386. *
  387. * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
  388. * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
  389. * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
  390. * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
  391. * SIG_EXPR_PTR(ROMD8, ROM16S));
  392. */
  393. #define SIG_EXPR_LIST_DECL(sig, ...) \
  394. static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
  395. { __VA_ARGS__, NULL }
  396. /**
  397. * A short-hand macro for declaring a function expression and an expression
  398. * list with a single function.
  399. *
  400. * @func: A macro symbol name for the function (is subjected to token pasting)
  401. * @...: Function descriptors that define the function expression
  402. *
  403. * For example, signal NCTS6 participates in its own function with one group:
  404. *
  405. * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
  406. */
  407. #define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
  408. SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
  409. SIG_EXPR_DECL_(sig, func); \
  410. SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
  411. #define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
  412. SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
  413. #define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
  414. #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
  415. #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
  416. #define PIN_SYM(pin) pin_ ## pin
  417. #define MS_PIN_DECL_(pin, ...) \
  418. static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
  419. { __VA_ARGS__, NULL }; \
  420. static const struct aspeed_pin_desc PIN_SYM(pin) = \
  421. { #pin, PIN_EXPRS_PTR(pin) }
  422. /**
  423. * Declare a multi-signal pin
  424. *
  425. * @pin: The pin number
  426. * @other: Macro name for "other" functionality (subjected to stringification)
  427. * @high: Macro name for the highest priority signal functions
  428. * @low: Macro name for the low signal functions
  429. *
  430. * For example:
  431. *
  432. * #define A8 56
  433. * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
  434. * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
  435. * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
  436. * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
  437. * SIG_EXPR_PTR(ROMD8, ROM16S));
  438. * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
  439. * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
  440. */
  441. #define MS_PIN_DECL(pin, other, high, low) \
  442. SIG_EXPR_LIST_DECL_SINGLE(other, other); \
  443. MS_PIN_DECL_(pin, \
  444. SIG_EXPR_LIST_PTR(high), \
  445. SIG_EXPR_LIST_PTR(low), \
  446. SIG_EXPR_LIST_PTR(other))
  447. #define PIN_GROUP_SYM(func) pins_ ## func
  448. #define FUNC_GROUP_SYM(func) groups_ ## func
  449. #define FUNC_GROUP_DECL(func, ...) \
  450. static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
  451. static const char *FUNC_GROUP_SYM(func)[] = { #func }
  452. /**
  453. * Declare a single signal pin
  454. *
  455. * @pin: The pin number
  456. * @other: Macro name for "other" functionality (subjected to stringification)
  457. * @sig: Macro name for the signal (subjected to stringification)
  458. *
  459. * For example:
  460. *
  461. * #define E3 80
  462. * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
  463. * SS_PIN_DECL(E3, GPIOK0, SCL5);
  464. */
  465. #define SS_PIN_DECL(pin, other, sig) \
  466. SIG_EXPR_LIST_DECL_SINGLE(other, other); \
  467. MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
  468. /**
  469. * Single signal, single function pin declaration
  470. *
  471. * @pin: The pin number
  472. * @other: Macro name for "other" functionality (subjected to stringification)
  473. * @sig: Macro name for the signal (subjected to stringification)
  474. * @...: Signal descriptors that define the function expression
  475. *
  476. * For example:
  477. *
  478. * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
  479. */
  480. #define SSSF_PIN_DECL(pin, other, sig, ...) \
  481. SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
  482. SIG_EXPR_LIST_DECL_SINGLE(other, other); \
  483. MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
  484. FUNC_GROUP_DECL(sig, pin)
  485. #define GPIO_PIN_DECL(pin, gpio) \
  486. SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
  487. MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
  488. /**
  489. * @param The pinconf parameter type
  490. * @pins The pin range this config struct covers, [low, high]
  491. * @reg The register housing the configuration bits
  492. * @mask The mask to select the bits of interest in @reg
  493. */
  494. struct aspeed_pin_config {
  495. enum pin_config_param param;
  496. unsigned int pins[2];
  497. unsigned int reg;
  498. u8 bit;
  499. u8 value;
  500. };
  501. struct aspeed_pinctrl_data {
  502. struct regmap *maps[ASPEED_NR_PINMUX_IPS];
  503. const struct pinctrl_pin_desc *pins;
  504. const unsigned int npins;
  505. const struct aspeed_pin_group *groups;
  506. const unsigned int ngroups;
  507. const struct aspeed_pin_function *functions;
  508. const unsigned int nfunctions;
  509. const struct aspeed_pin_config *configs;
  510. const unsigned int nconfigs;
  511. };
  512. #define ASPEED_PINCTRL_PIN(name_) \
  513. [name_] = { \
  514. .number = name_, \
  515. .name = #name_, \
  516. .drv_data = (void *) &(PIN_SYM(name_)) \
  517. }
  518. struct aspeed_pin_group {
  519. const char *name;
  520. const unsigned int *pins;
  521. const unsigned int npins;
  522. };
  523. #define ASPEED_PINCTRL_GROUP(name_) { \
  524. .name = #name_, \
  525. .pins = &(PIN_GROUP_SYM(name_))[0], \
  526. .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
  527. }
  528. struct aspeed_pin_function {
  529. const char *name;
  530. const char *const *groups;
  531. unsigned int ngroups;
  532. };
  533. #define ASPEED_PINCTRL_FUNC(name_, ...) { \
  534. .name = #name_, \
  535. .groups = &FUNC_GROUP_SYM(name_)[0], \
  536. .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
  537. }
  538. int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
  539. const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  540. unsigned int group);
  541. int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  542. unsigned int group, const unsigned int **pins,
  543. unsigned int *npins);
  544. void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  545. struct seq_file *s, unsigned int offset);
  546. int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev);
  547. const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
  548. unsigned int function);
  549. int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
  550. unsigned int function, const char * const **groups,
  551. unsigned int * const num_groups);
  552. int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
  553. unsigned int group);
  554. int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
  555. struct pinctrl_gpio_range *range,
  556. unsigned int offset);
  557. int aspeed_pinctrl_probe(struct platform_device *pdev,
  558. struct pinctrl_desc *pdesc,
  559. struct aspeed_pinctrl_data *pdata);
  560. int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
  561. unsigned long *config);
  562. int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
  563. unsigned long *configs, unsigned int num_configs);
  564. int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
  565. unsigned int selector,
  566. unsigned long *config);
  567. int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
  568. unsigned int selector,
  569. unsigned long *configs,
  570. unsigned int num_configs);
  571. #endif /* PINCTRL_ASPEED */