lpfc_hw.h 127 KB

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  1. /*******************************************************************
  2. * This file is part of the Emulex Linux Device Driver for *
  3. * Fibre Channel Host Bus Adapters. *
  4. * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term *
  5. * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
  6. * Copyright (C) 2004-2016 Emulex. All rights reserved. *
  7. * EMULEX and SLI are trademarks of Emulex. *
  8. * www.broadcom.com *
  9. * *
  10. * This program is free software; you can redistribute it and/or *
  11. * modify it under the terms of version 2 of the GNU General *
  12. * Public License as published by the Free Software Foundation. *
  13. * This program is distributed in the hope that it will be useful. *
  14. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  15. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  16. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  17. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  19. * more details, a copy of which can be found in the file COPYING *
  20. * included with this package. *
  21. *******************************************************************/
  22. #define FDMI_DID 0xfffffaU
  23. #define NameServer_DID 0xfffffcU
  24. #define SCR_DID 0xfffffdU
  25. #define Fabric_DID 0xfffffeU
  26. #define Bcast_DID 0xffffffU
  27. #define Mask_DID 0xffffffU
  28. #define CT_DID_MASK 0xffff00U
  29. #define Fabric_DID_MASK 0xfff000U
  30. #define WELL_KNOWN_DID_MASK 0xfffff0U
  31. #define PT2PT_LocalID 1
  32. #define PT2PT_RemoteID 2
  33. #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
  34. #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
  35. #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
  36. #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
  37. #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
  38. 0 */
  39. #define FCELSSIZE 1024 /* maximum ELS transfer size */
  40. #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
  41. #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
  42. #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
  43. #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
  44. #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
  45. #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
  46. #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
  47. #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  48. #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  49. #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
  50. #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
  51. #define SLI2_IOCB_CMD_R3_ENTRIES 0
  52. #define SLI2_IOCB_RSP_R3_ENTRIES 0
  53. #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  54. #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  55. #define SLI2_IOCB_CMD_SIZE 32
  56. #define SLI2_IOCB_RSP_SIZE 32
  57. #define SLI3_IOCB_CMD_SIZE 128
  58. #define SLI3_IOCB_RSP_SIZE 64
  59. #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
  60. #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
  61. /* vendor ID used in SCSI netlink calls */
  62. #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
  63. #define FW_REV_STR_SIZE 32
  64. /* Common Transport structures and definitions */
  65. union CtRevisionId {
  66. /* Structure is in Big Endian format */
  67. struct {
  68. uint32_t Revision:8;
  69. uint32_t InId:24;
  70. } bits;
  71. uint32_t word;
  72. };
  73. union CtCommandResponse {
  74. /* Structure is in Big Endian format */
  75. struct {
  76. uint32_t CmdRsp:16;
  77. uint32_t Size:16;
  78. } bits;
  79. uint32_t word;
  80. };
  81. /* FC4 Feature bits for RFF_ID */
  82. #define FC4_FEATURE_TARGET 0x1
  83. #define FC4_FEATURE_INIT 0x2
  84. #define FC4_FEATURE_NVME_DISC 0x4
  85. struct lpfc_sli_ct_request {
  86. /* Structure is in Big Endian format */
  87. union CtRevisionId RevisionId;
  88. uint8_t FsType;
  89. uint8_t FsSubType;
  90. uint8_t Options;
  91. uint8_t Rsrvd1;
  92. union CtCommandResponse CommandResponse;
  93. uint8_t Rsrvd2;
  94. uint8_t ReasonCode;
  95. uint8_t Explanation;
  96. uint8_t VendorUnique;
  97. #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
  98. union {
  99. uint32_t PortID;
  100. struct gid {
  101. uint8_t PortType; /* for GID_PT requests */
  102. uint8_t DomainScope;
  103. uint8_t AreaScope;
  104. uint8_t Fc4Type; /* for GID_FT requests */
  105. } gid;
  106. struct gid_ff {
  107. uint8_t Flags;
  108. uint8_t DomainScope;
  109. uint8_t AreaScope;
  110. uint8_t rsvd1;
  111. uint8_t rsvd2;
  112. uint8_t rsvd3;
  113. uint8_t Fc4FBits;
  114. uint8_t Fc4Type;
  115. } gid_ff;
  116. struct rft {
  117. uint32_t PortId; /* For RFT_ID requests */
  118. #ifdef __BIG_ENDIAN_BITFIELD
  119. uint32_t rsvd0:16;
  120. uint32_t rsvd1:7;
  121. uint32_t fcpReg:1; /* Type 8 */
  122. uint32_t rsvd2:2;
  123. uint32_t ipReg:1; /* Type 5 */
  124. uint32_t rsvd3:5;
  125. #else /* __LITTLE_ENDIAN_BITFIELD */
  126. uint32_t rsvd0:16;
  127. uint32_t fcpReg:1; /* Type 8 */
  128. uint32_t rsvd1:7;
  129. uint32_t rsvd3:5;
  130. uint32_t ipReg:1; /* Type 5 */
  131. uint32_t rsvd2:2;
  132. #endif
  133. uint32_t rsvd[7];
  134. } rft;
  135. struct rnn {
  136. uint32_t PortId; /* For RNN_ID requests */
  137. uint8_t wwnn[8];
  138. } rnn;
  139. struct rsnn { /* For RSNN_ID requests */
  140. uint8_t wwnn[8];
  141. uint8_t len;
  142. uint8_t symbname[255];
  143. } rsnn;
  144. struct da_id { /* For DA_ID requests */
  145. uint32_t port_id;
  146. } da_id;
  147. struct rspn { /* For RSPN_ID requests */
  148. uint32_t PortId;
  149. uint8_t len;
  150. uint8_t symbname[255];
  151. } rspn;
  152. struct gff {
  153. uint32_t PortId;
  154. } gff;
  155. struct gff_acc {
  156. uint8_t fbits[128];
  157. } gff_acc;
  158. struct gft {
  159. uint32_t PortId;
  160. } gft;
  161. struct gft_acc {
  162. uint32_t fc4_types[8];
  163. } gft_acc;
  164. #define FCP_TYPE_FEATURE_OFFSET 7
  165. struct rff {
  166. uint32_t PortId;
  167. uint8_t reserved[2];
  168. uint8_t fbits;
  169. uint8_t type_code; /* type=8 for FCP */
  170. } rff;
  171. } un;
  172. };
  173. #define LPFC_MAX_CT_SIZE (60 * 4096)
  174. #define SLI_CT_REVISION 1
  175. #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  176. sizeof(struct gid))
  177. #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  178. sizeof(struct gid_ff))
  179. #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  180. sizeof(struct gff))
  181. #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  182. sizeof(struct gft))
  183. #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  184. sizeof(struct rft))
  185. #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  186. sizeof(struct rff))
  187. #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  188. sizeof(struct rnn))
  189. #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  190. sizeof(struct rsnn))
  191. #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  192. sizeof(struct da_id))
  193. #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
  194. sizeof(struct rspn))
  195. /*
  196. * FsType Definitions
  197. */
  198. #define SLI_CT_MANAGEMENT_SERVICE 0xFA
  199. #define SLI_CT_TIME_SERVICE 0xFB
  200. #define SLI_CT_DIRECTORY_SERVICE 0xFC
  201. #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
  202. /*
  203. * Directory Service Subtypes
  204. */
  205. #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
  206. /*
  207. * Response Codes
  208. */
  209. #define SLI_CT_RESPONSE_FS_RJT 0x8001
  210. #define SLI_CT_RESPONSE_FS_ACC 0x8002
  211. /*
  212. * Reason Codes
  213. */
  214. #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
  215. #define SLI_CT_INVALID_COMMAND 0x01
  216. #define SLI_CT_INVALID_VERSION 0x02
  217. #define SLI_CT_LOGICAL_ERROR 0x03
  218. #define SLI_CT_INVALID_IU_SIZE 0x04
  219. #define SLI_CT_LOGICAL_BUSY 0x05
  220. #define SLI_CT_PROTOCOL_ERROR 0x07
  221. #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
  222. #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
  223. #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
  224. #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
  225. #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
  226. #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
  227. #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
  228. #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
  229. #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
  230. #define SLI_CT_VENDOR_UNIQUE 0xff
  231. /*
  232. * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
  233. */
  234. #define SLI_CT_NO_PORT_ID 0x01
  235. #define SLI_CT_NO_PORT_NAME 0x02
  236. #define SLI_CT_NO_NODE_NAME 0x03
  237. #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
  238. #define SLI_CT_NO_IP_ADDRESS 0x05
  239. #define SLI_CT_NO_IPA 0x06
  240. #define SLI_CT_NO_FC4_TYPES 0x07
  241. #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
  242. #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
  243. #define SLI_CT_NO_PORT_TYPE 0x0A
  244. #define SLI_CT_ACCESS_DENIED 0x10
  245. #define SLI_CT_INVALID_PORT_ID 0x11
  246. #define SLI_CT_DATABASE_EMPTY 0x12
  247. /*
  248. * Name Server Command Codes
  249. */
  250. #define SLI_CTNS_GA_NXT 0x0100
  251. #define SLI_CTNS_GPN_ID 0x0112
  252. #define SLI_CTNS_GNN_ID 0x0113
  253. #define SLI_CTNS_GCS_ID 0x0114
  254. #define SLI_CTNS_GFT_ID 0x0117
  255. #define SLI_CTNS_GSPN_ID 0x0118
  256. #define SLI_CTNS_GPT_ID 0x011A
  257. #define SLI_CTNS_GFF_ID 0x011F
  258. #define SLI_CTNS_GID_PN 0x0121
  259. #define SLI_CTNS_GID_NN 0x0131
  260. #define SLI_CTNS_GIP_NN 0x0135
  261. #define SLI_CTNS_GIPA_NN 0x0136
  262. #define SLI_CTNS_GSNN_NN 0x0139
  263. #define SLI_CTNS_GNN_IP 0x0153
  264. #define SLI_CTNS_GIPA_IP 0x0156
  265. #define SLI_CTNS_GID_FT 0x0171
  266. #define SLI_CTNS_GID_FF 0x01F1
  267. #define SLI_CTNS_GID_PT 0x01A1
  268. #define SLI_CTNS_RPN_ID 0x0212
  269. #define SLI_CTNS_RNN_ID 0x0213
  270. #define SLI_CTNS_RCS_ID 0x0214
  271. #define SLI_CTNS_RFT_ID 0x0217
  272. #define SLI_CTNS_RSPN_ID 0x0218
  273. #define SLI_CTNS_RPT_ID 0x021A
  274. #define SLI_CTNS_RFF_ID 0x021F
  275. #define SLI_CTNS_RIP_NN 0x0235
  276. #define SLI_CTNS_RIPA_NN 0x0236
  277. #define SLI_CTNS_RSNN_NN 0x0239
  278. #define SLI_CTNS_DA_ID 0x0300
  279. /*
  280. * Port Types
  281. */
  282. #define SLI_CTPT_N_PORT 0x01
  283. #define SLI_CTPT_NL_PORT 0x02
  284. #define SLI_CTPT_FNL_PORT 0x03
  285. #define SLI_CTPT_IP 0x04
  286. #define SLI_CTPT_FCP 0x08
  287. #define SLI_CTPT_NVME 0x28
  288. #define SLI_CTPT_NX_PORT 0x7F
  289. #define SLI_CTPT_F_PORT 0x81
  290. #define SLI_CTPT_FL_PORT 0x82
  291. #define SLI_CTPT_E_PORT 0x84
  292. #define SLI_CT_LAST_ENTRY 0x80000000
  293. /* Fibre Channel Service Parameter definitions */
  294. #define FC_PH_4_0 6 /* FC-PH version 4.0 */
  295. #define FC_PH_4_1 7 /* FC-PH version 4.1 */
  296. #define FC_PH_4_2 8 /* FC-PH version 4.2 */
  297. #define FC_PH_4_3 9 /* FC-PH version 4.3 */
  298. #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
  299. #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
  300. #define FC_PH3 0x20 /* FC-PH-3 version */
  301. #define FF_FRAME_SIZE 2048
  302. struct lpfc_name {
  303. union {
  304. struct {
  305. #ifdef __BIG_ENDIAN_BITFIELD
  306. uint8_t nameType:4; /* FC Word 0, bit 28:31 */
  307. uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
  308. 8:11 of IEEE ext */
  309. #else /* __LITTLE_ENDIAN_BITFIELD */
  310. uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
  311. 8:11 of IEEE ext */
  312. uint8_t nameType:4; /* FC Word 0, bit 28:31 */
  313. #endif
  314. #define NAME_IEEE 0x1 /* IEEE name - nameType */
  315. #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
  316. #define NAME_FC_TYPE 0x3 /* FC native name type */
  317. #define NAME_IP_TYPE 0x4 /* IP address */
  318. #define NAME_CCITT_TYPE 0xC
  319. #define NAME_CCITT_GR_TYPE 0xE
  320. uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
  321. extended Lsb */
  322. uint8_t IEEE[6]; /* FC IEEE address */
  323. } s;
  324. uint8_t wwn[8];
  325. uint64_t name;
  326. } u;
  327. };
  328. struct csp {
  329. uint8_t fcphHigh; /* FC Word 0, byte 0 */
  330. uint8_t fcphLow;
  331. uint8_t bbCreditMsb;
  332. uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
  333. /*
  334. * Word 1 Bit 31 in common service parameter is overloaded.
  335. * Word 1 Bit 31 in FLOGI request is multiple NPort request
  336. * Word 1 Bit 31 in FLOGI response is clean address bit
  337. */
  338. #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
  339. /*
  340. * Word 1 Bit 30 in common service parameter is overloaded.
  341. * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
  342. * Word 1 Bit 30 in PLOGI request is random offset
  343. */
  344. #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
  345. /*
  346. * Word 1 Bit 29 in common service parameter is overloaded.
  347. * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
  348. * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
  349. */
  350. #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
  351. #ifdef __BIG_ENDIAN_BITFIELD
  352. uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
  353. uint16_t randomOffset:1; /* FC Word 1, bit 30 */
  354. uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
  355. uint16_t fPort:1; /* FC Word 1, bit 28 */
  356. uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
  357. uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
  358. uint16_t multicast:1; /* FC Word 1, bit 25 */
  359. uint16_t broadcast:1; /* FC Word 1, bit 24 */
  360. uint16_t huntgroup:1; /* FC Word 1, bit 23 */
  361. uint16_t simplex:1; /* FC Word 1, bit 22 */
  362. uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
  363. uint16_t dhd:1; /* FC Word 1, bit 18 */
  364. uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
  365. uint16_t payloadlength:1; /* FC Word 1, bit 16 */
  366. #else /* __LITTLE_ENDIAN_BITFIELD */
  367. uint16_t broadcast:1; /* FC Word 1, bit 24 */
  368. uint16_t multicast:1; /* FC Word 1, bit 25 */
  369. uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
  370. uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
  371. uint16_t fPort:1; /* FC Word 1, bit 28 */
  372. uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
  373. uint16_t randomOffset:1; /* FC Word 1, bit 30 */
  374. uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
  375. uint16_t payloadlength:1; /* FC Word 1, bit 16 */
  376. uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
  377. uint16_t dhd:1; /* FC Word 1, bit 18 */
  378. uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
  379. uint16_t simplex:1; /* FC Word 1, bit 22 */
  380. uint16_t huntgroup:1; /* FC Word 1, bit 23 */
  381. #endif
  382. uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
  383. uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
  384. union {
  385. struct {
  386. uint8_t word2Reserved1; /* FC Word 2 byte 0 */
  387. uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
  388. uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
  389. uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
  390. } nPort;
  391. uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
  392. } w2;
  393. uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
  394. };
  395. struct class_parms {
  396. #ifdef __BIG_ENDIAN_BITFIELD
  397. uint8_t classValid:1; /* FC Word 0, bit 31 */
  398. uint8_t intermix:1; /* FC Word 0, bit 30 */
  399. uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
  400. uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
  401. uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
  402. uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
  403. #else /* __LITTLE_ENDIAN_BITFIELD */
  404. uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
  405. uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
  406. uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
  407. uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
  408. uint8_t intermix:1; /* FC Word 0, bit 30 */
  409. uint8_t classValid:1; /* FC Word 0, bit 31 */
  410. #endif
  411. uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
  412. #ifdef __BIG_ENDIAN_BITFIELD
  413. uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
  414. uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
  415. uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
  416. uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
  417. uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
  418. #else /* __LITTLE_ENDIAN_BITFIELD */
  419. uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
  420. uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
  421. uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
  422. uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
  423. uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
  424. #endif
  425. uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
  426. #ifdef __BIG_ENDIAN_BITFIELD
  427. uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
  428. uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
  429. uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
  430. uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
  431. uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
  432. uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
  433. #else /* __LITTLE_ENDIAN_BITFIELD */
  434. uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
  435. uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
  436. uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
  437. uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
  438. uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
  439. uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
  440. #endif
  441. uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
  442. uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
  443. uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
  444. uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
  445. uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
  446. uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
  447. uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
  448. uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
  449. uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
  450. uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
  451. uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
  452. };
  453. #define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/
  454. struct serv_parm { /* Structure is in Big Endian format */
  455. struct csp cmn;
  456. struct lpfc_name portName;
  457. struct lpfc_name nodeName;
  458. struct class_parms cls1;
  459. struct class_parms cls2;
  460. struct class_parms cls3;
  461. struct class_parms cls4;
  462. union {
  463. uint8_t vendorVersion[16];
  464. struct {
  465. uint32_t vid;
  466. #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
  467. uint32_t flags;
  468. #define LPFC_VV_SUPPRESS_RSP 1
  469. } vv;
  470. } un;
  471. };
  472. /*
  473. * Virtual Fabric Tagging Header
  474. */
  475. struct fc_vft_header {
  476. uint32_t word0;
  477. #define fc_vft_hdr_r_ctl_SHIFT 24
  478. #define fc_vft_hdr_r_ctl_MASK 0xFF
  479. #define fc_vft_hdr_r_ctl_WORD word0
  480. #define fc_vft_hdr_ver_SHIFT 22
  481. #define fc_vft_hdr_ver_MASK 0x3
  482. #define fc_vft_hdr_ver_WORD word0
  483. #define fc_vft_hdr_type_SHIFT 18
  484. #define fc_vft_hdr_type_MASK 0xF
  485. #define fc_vft_hdr_type_WORD word0
  486. #define fc_vft_hdr_e_SHIFT 16
  487. #define fc_vft_hdr_e_MASK 0x1
  488. #define fc_vft_hdr_e_WORD word0
  489. #define fc_vft_hdr_priority_SHIFT 13
  490. #define fc_vft_hdr_priority_MASK 0x7
  491. #define fc_vft_hdr_priority_WORD word0
  492. #define fc_vft_hdr_vf_id_SHIFT 1
  493. #define fc_vft_hdr_vf_id_MASK 0xFFF
  494. #define fc_vft_hdr_vf_id_WORD word0
  495. uint32_t word1;
  496. #define fc_vft_hdr_hopct_SHIFT 24
  497. #define fc_vft_hdr_hopct_MASK 0xFF
  498. #define fc_vft_hdr_hopct_WORD word1
  499. };
  500. /*
  501. * Extended Link Service LS_COMMAND codes (Payload Word 0)
  502. */
  503. #ifdef __BIG_ENDIAN_BITFIELD
  504. #define ELS_CMD_MASK 0xffff0000
  505. #define ELS_RSP_MASK 0xff000000
  506. #define ELS_CMD_LS_RJT 0x01000000
  507. #define ELS_CMD_ACC 0x02000000
  508. #define ELS_CMD_PLOGI 0x03000000
  509. #define ELS_CMD_FLOGI 0x04000000
  510. #define ELS_CMD_LOGO 0x05000000
  511. #define ELS_CMD_ABTX 0x06000000
  512. #define ELS_CMD_RCS 0x07000000
  513. #define ELS_CMD_RES 0x08000000
  514. #define ELS_CMD_RSS 0x09000000
  515. #define ELS_CMD_RSI 0x0A000000
  516. #define ELS_CMD_ESTS 0x0B000000
  517. #define ELS_CMD_ESTC 0x0C000000
  518. #define ELS_CMD_ADVC 0x0D000000
  519. #define ELS_CMD_RTV 0x0E000000
  520. #define ELS_CMD_RLS 0x0F000000
  521. #define ELS_CMD_ECHO 0x10000000
  522. #define ELS_CMD_TEST 0x11000000
  523. #define ELS_CMD_RRQ 0x12000000
  524. #define ELS_CMD_REC 0x13000000
  525. #define ELS_CMD_RDP 0x18000000
  526. #define ELS_CMD_PRLI 0x20100014
  527. #define ELS_CMD_NVMEPRLI 0x20140018
  528. #define ELS_CMD_PRLO 0x21100014
  529. #define ELS_CMD_PRLO_ACC 0x02100014
  530. #define ELS_CMD_PDISC 0x50000000
  531. #define ELS_CMD_FDISC 0x51000000
  532. #define ELS_CMD_ADISC 0x52000000
  533. #define ELS_CMD_FARP 0x54000000
  534. #define ELS_CMD_FARPR 0x55000000
  535. #define ELS_CMD_RPS 0x56000000
  536. #define ELS_CMD_RPL 0x57000000
  537. #define ELS_CMD_FAN 0x60000000
  538. #define ELS_CMD_RSCN 0x61040000
  539. #define ELS_CMD_SCR 0x62000000
  540. #define ELS_CMD_RNID 0x78000000
  541. #define ELS_CMD_LIRR 0x7A000000
  542. #define ELS_CMD_LCB 0x81000000
  543. #else /* __LITTLE_ENDIAN_BITFIELD */
  544. #define ELS_CMD_MASK 0xffff
  545. #define ELS_RSP_MASK 0xff
  546. #define ELS_CMD_LS_RJT 0x01
  547. #define ELS_CMD_ACC 0x02
  548. #define ELS_CMD_PLOGI 0x03
  549. #define ELS_CMD_FLOGI 0x04
  550. #define ELS_CMD_LOGO 0x05
  551. #define ELS_CMD_ABTX 0x06
  552. #define ELS_CMD_RCS 0x07
  553. #define ELS_CMD_RES 0x08
  554. #define ELS_CMD_RSS 0x09
  555. #define ELS_CMD_RSI 0x0A
  556. #define ELS_CMD_ESTS 0x0B
  557. #define ELS_CMD_ESTC 0x0C
  558. #define ELS_CMD_ADVC 0x0D
  559. #define ELS_CMD_RTV 0x0E
  560. #define ELS_CMD_RLS 0x0F
  561. #define ELS_CMD_ECHO 0x10
  562. #define ELS_CMD_TEST 0x11
  563. #define ELS_CMD_RRQ 0x12
  564. #define ELS_CMD_REC 0x13
  565. #define ELS_CMD_RDP 0x18
  566. #define ELS_CMD_PRLI 0x14001020
  567. #define ELS_CMD_NVMEPRLI 0x18001420
  568. #define ELS_CMD_PRLO 0x14001021
  569. #define ELS_CMD_PRLO_ACC 0x14001002
  570. #define ELS_CMD_PDISC 0x50
  571. #define ELS_CMD_FDISC 0x51
  572. #define ELS_CMD_ADISC 0x52
  573. #define ELS_CMD_FARP 0x54
  574. #define ELS_CMD_FARPR 0x55
  575. #define ELS_CMD_RPS 0x56
  576. #define ELS_CMD_RPL 0x57
  577. #define ELS_CMD_FAN 0x60
  578. #define ELS_CMD_RSCN 0x0461
  579. #define ELS_CMD_SCR 0x62
  580. #define ELS_CMD_RNID 0x78
  581. #define ELS_CMD_LIRR 0x7A
  582. #define ELS_CMD_LCB 0x81
  583. #endif
  584. /*
  585. * LS_RJT Payload Definition
  586. */
  587. struct ls_rjt { /* Structure is in Big Endian format */
  588. union {
  589. uint32_t lsRjtError;
  590. struct {
  591. uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
  592. uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
  593. /* LS_RJT reason codes */
  594. #define LSRJT_INVALID_CMD 0x01
  595. #define LSRJT_LOGICAL_ERR 0x03
  596. #define LSRJT_LOGICAL_BSY 0x05
  597. #define LSRJT_PROTOCOL_ERR 0x07
  598. #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
  599. #define LSRJT_CMD_UNSUPPORTED 0x0B
  600. #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
  601. uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
  602. /* LS_RJT reason explanation */
  603. #define LSEXP_NOTHING_MORE 0x00
  604. #define LSEXP_SPARM_OPTIONS 0x01
  605. #define LSEXP_SPARM_ICTL 0x03
  606. #define LSEXP_SPARM_RCTL 0x05
  607. #define LSEXP_SPARM_RCV_SIZE 0x07
  608. #define LSEXP_SPARM_CONCUR_SEQ 0x09
  609. #define LSEXP_SPARM_CREDIT 0x0B
  610. #define LSEXP_INVALID_PNAME 0x0D
  611. #define LSEXP_INVALID_NNAME 0x0E
  612. #define LSEXP_INVALID_CSP 0x0F
  613. #define LSEXP_INVALID_ASSOC_HDR 0x11
  614. #define LSEXP_ASSOC_HDR_REQ 0x13
  615. #define LSEXP_INVALID_O_SID 0x15
  616. #define LSEXP_INVALID_OX_RX 0x17
  617. #define LSEXP_CMD_IN_PROGRESS 0x19
  618. #define LSEXP_PORT_LOGIN_REQ 0x1E
  619. #define LSEXP_INVALID_NPORT_ID 0x1F
  620. #define LSEXP_INVALID_SEQ_ID 0x21
  621. #define LSEXP_INVALID_XCHG 0x23
  622. #define LSEXP_INACTIVE_XCHG 0x25
  623. #define LSEXP_RQ_REQUIRED 0x27
  624. #define LSEXP_OUT_OF_RESOURCE 0x29
  625. #define LSEXP_CANT_GIVE_DATA 0x2A
  626. #define LSEXP_REQ_UNSUPPORTED 0x2C
  627. uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
  628. } b;
  629. } un;
  630. };
  631. /*
  632. * N_Port Login (FLOGO/PLOGO Request) Payload Definition
  633. */
  634. typedef struct _LOGO { /* Structure is in Big Endian format */
  635. union {
  636. uint32_t nPortId32; /* Access nPortId as a word */
  637. struct {
  638. uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
  639. uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
  640. uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
  641. uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
  642. } b;
  643. } un;
  644. struct lpfc_name portName; /* N_port name field */
  645. } LOGO;
  646. /*
  647. * FCP Login (PRLI Request / ACC) Payload Definition
  648. */
  649. #define PRLX_PAGE_LEN 0x10
  650. #define TPRLO_PAGE_LEN 0x14
  651. typedef struct _PRLI { /* Structure is in Big Endian format */
  652. uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
  653. #define PRLI_FCP_TYPE 0x08
  654. #define PRLI_NVME_TYPE 0x28
  655. uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
  656. #ifdef __BIG_ENDIAN_BITFIELD
  657. uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
  658. uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
  659. uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
  660. /* ACC = imagePairEstablished */
  661. uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
  662. uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
  663. #else /* __LITTLE_ENDIAN_BITFIELD */
  664. uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
  665. uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
  666. uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
  667. uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
  668. uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
  669. /* ACC = imagePairEstablished */
  670. #endif
  671. #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
  672. #define PRLI_NO_RESOURCES 0x2
  673. #define PRLI_INIT_INCOMPLETE 0x3
  674. #define PRLI_NO_SUCH_PA 0x4
  675. #define PRLI_PREDEF_CONFIG 0x5
  676. #define PRLI_PARTIAL_SUCCESS 0x6
  677. #define PRLI_INVALID_PAGE_CNT 0x7
  678. uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
  679. uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
  680. uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
  681. uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
  682. uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
  683. #ifdef __BIG_ENDIAN_BITFIELD
  684. uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
  685. uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
  686. uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
  687. uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
  688. uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
  689. uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
  690. uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
  691. uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
  692. uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
  693. uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
  694. uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
  695. uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
  696. uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
  697. uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
  698. uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
  699. uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
  700. #else /* __LITTLE_ENDIAN_BITFIELD */
  701. uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
  702. uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
  703. uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
  704. uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
  705. uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
  706. uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
  707. uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
  708. uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
  709. uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
  710. uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
  711. uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
  712. uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
  713. uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
  714. uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
  715. uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
  716. uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
  717. #endif
  718. } PRLI;
  719. /*
  720. * FCP Logout (PRLO Request / ACC) Payload Definition
  721. */
  722. typedef struct _PRLO { /* Structure is in Big Endian format */
  723. uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
  724. #define PRLO_FCP_TYPE 0x08
  725. uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
  726. #ifdef __BIG_ENDIAN_BITFIELD
  727. uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
  728. uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
  729. uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
  730. uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
  731. #else /* __LITTLE_ENDIAN_BITFIELD */
  732. uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
  733. uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
  734. uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
  735. uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
  736. #endif
  737. #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
  738. #define PRLO_NO_SUCH_IMAGE 0x4
  739. #define PRLO_INVALID_PAGE_CNT 0x7
  740. uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
  741. uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
  742. uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
  743. uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
  744. } PRLO;
  745. typedef struct _ADISC { /* Structure is in Big Endian format */
  746. uint32_t hardAL_PA;
  747. struct lpfc_name portName;
  748. struct lpfc_name nodeName;
  749. uint32_t DID;
  750. } ADISC;
  751. typedef struct _FARP { /* Structure is in Big Endian format */
  752. uint32_t Mflags:8;
  753. uint32_t Odid:24;
  754. #define FARP_NO_ACTION 0 /* FARP information enclosed, no
  755. action */
  756. #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
  757. #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
  758. #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
  759. #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
  760. supported */
  761. #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
  762. supported */
  763. uint32_t Rflags:8;
  764. uint32_t Rdid:24;
  765. #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
  766. #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
  767. struct lpfc_name OportName;
  768. struct lpfc_name OnodeName;
  769. struct lpfc_name RportName;
  770. struct lpfc_name RnodeName;
  771. uint8_t Oipaddr[16];
  772. uint8_t Ripaddr[16];
  773. } FARP;
  774. typedef struct _FAN { /* Structure is in Big Endian format */
  775. uint32_t Fdid;
  776. struct lpfc_name FportName;
  777. struct lpfc_name FnodeName;
  778. } FAN;
  779. typedef struct _SCR { /* Structure is in Big Endian format */
  780. uint8_t resvd1;
  781. uint8_t resvd2;
  782. uint8_t resvd3;
  783. uint8_t Function;
  784. #define SCR_FUNC_FABRIC 0x01
  785. #define SCR_FUNC_NPORT 0x02
  786. #define SCR_FUNC_FULL 0x03
  787. #define SCR_CLEAR 0xff
  788. } SCR;
  789. typedef struct _RNID_TOP_DISC {
  790. struct lpfc_name portName;
  791. uint8_t resvd[8];
  792. uint32_t unitType;
  793. #define RNID_HBA 0x7
  794. #define RNID_HOST 0xa
  795. #define RNID_DRIVER 0xd
  796. uint32_t physPort;
  797. uint32_t attachedNodes;
  798. uint16_t ipVersion;
  799. #define RNID_IPV4 0x1
  800. #define RNID_IPV6 0x2
  801. uint16_t UDPport;
  802. uint8_t ipAddr[16];
  803. uint16_t resvd1;
  804. uint16_t flags;
  805. #define RNID_TD_SUPPORT 0x1
  806. #define RNID_LP_VALID 0x2
  807. } RNID_TOP_DISC;
  808. typedef struct _RNID { /* Structure is in Big Endian format */
  809. uint8_t Format;
  810. #define RNID_TOPOLOGY_DISC 0xdf
  811. uint8_t CommonLen;
  812. uint8_t resvd1;
  813. uint8_t SpecificLen;
  814. struct lpfc_name portName;
  815. struct lpfc_name nodeName;
  816. union {
  817. RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
  818. } un;
  819. } RNID;
  820. typedef struct _RPS { /* Structure is in Big Endian format */
  821. union {
  822. uint32_t portNum;
  823. struct lpfc_name portName;
  824. } un;
  825. } RPS;
  826. typedef struct _RPS_RSP { /* Structure is in Big Endian format */
  827. uint16_t rsvd1;
  828. uint16_t portStatus;
  829. uint32_t linkFailureCnt;
  830. uint32_t lossSyncCnt;
  831. uint32_t lossSignalCnt;
  832. uint32_t primSeqErrCnt;
  833. uint32_t invalidXmitWord;
  834. uint32_t crcCnt;
  835. } RPS_RSP;
  836. struct RLS { /* Structure is in Big Endian format */
  837. uint32_t rls;
  838. #define rls_rsvd_SHIFT 24
  839. #define rls_rsvd_MASK 0x000000ff
  840. #define rls_rsvd_WORD rls
  841. #define rls_did_SHIFT 0
  842. #define rls_did_MASK 0x00ffffff
  843. #define rls_did_WORD rls
  844. };
  845. struct RLS_RSP { /* Structure is in Big Endian format */
  846. uint32_t linkFailureCnt;
  847. uint32_t lossSyncCnt;
  848. uint32_t lossSignalCnt;
  849. uint32_t primSeqErrCnt;
  850. uint32_t invalidXmitWord;
  851. uint32_t crcCnt;
  852. };
  853. struct RRQ { /* Structure is in Big Endian format */
  854. uint32_t rrq;
  855. #define rrq_rsvd_SHIFT 24
  856. #define rrq_rsvd_MASK 0x000000ff
  857. #define rrq_rsvd_WORD rrq
  858. #define rrq_did_SHIFT 0
  859. #define rrq_did_MASK 0x00ffffff
  860. #define rrq_did_WORD rrq
  861. uint32_t rrq_exchg;
  862. #define rrq_oxid_SHIFT 16
  863. #define rrq_oxid_MASK 0xffff
  864. #define rrq_oxid_WORD rrq_exchg
  865. #define rrq_rxid_SHIFT 0
  866. #define rrq_rxid_MASK 0xffff
  867. #define rrq_rxid_WORD rrq_exchg
  868. };
  869. #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
  870. #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
  871. struct RTV_RSP { /* Structure is in Big Endian format */
  872. uint32_t ratov;
  873. uint32_t edtov;
  874. uint32_t qtov;
  875. #define qtov_rsvd0_SHIFT 28
  876. #define qtov_rsvd0_MASK 0x0000000f
  877. #define qtov_rsvd0_WORD qtov /* reserved */
  878. #define qtov_edtovres_SHIFT 27
  879. #define qtov_edtovres_MASK 0x00000001
  880. #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
  881. #define qtov__rsvd1_SHIFT 19
  882. #define qtov_rsvd1_MASK 0x0000003f
  883. #define qtov_rsvd1_WORD qtov /* reserved */
  884. #define qtov_rttov_SHIFT 18
  885. #define qtov_rttov_MASK 0x00000001
  886. #define qtov_rttov_WORD qtov /* R_T_TOV value */
  887. #define qtov_rsvd2_SHIFT 0
  888. #define qtov_rsvd2_MASK 0x0003ffff
  889. #define qtov_rsvd2_WORD qtov /* reserved */
  890. };
  891. typedef struct _RPL { /* Structure is in Big Endian format */
  892. uint32_t maxsize;
  893. uint32_t index;
  894. } RPL;
  895. typedef struct _PORT_NUM_BLK {
  896. uint32_t portNum;
  897. uint32_t portID;
  898. struct lpfc_name portName;
  899. } PORT_NUM_BLK;
  900. typedef struct _RPL_RSP { /* Structure is in Big Endian format */
  901. uint32_t listLen;
  902. uint32_t index;
  903. PORT_NUM_BLK port_num_blk;
  904. } RPL_RSP;
  905. /* This is used for RSCN command */
  906. typedef struct _D_ID { /* Structure is in Big Endian format */
  907. union {
  908. uint32_t word;
  909. struct {
  910. #ifdef __BIG_ENDIAN_BITFIELD
  911. uint8_t resv;
  912. uint8_t domain;
  913. uint8_t area;
  914. uint8_t id;
  915. #else /* __LITTLE_ENDIAN_BITFIELD */
  916. uint8_t id;
  917. uint8_t area;
  918. uint8_t domain;
  919. uint8_t resv;
  920. #endif
  921. } b;
  922. } un;
  923. } D_ID;
  924. #define RSCN_ADDRESS_FORMAT_PORT 0x0
  925. #define RSCN_ADDRESS_FORMAT_AREA 0x1
  926. #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
  927. #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
  928. #define RSCN_ADDRESS_FORMAT_MASK 0x3
  929. /*
  930. * Structure to define all ELS Payload types
  931. */
  932. typedef struct _ELS_PKT { /* Structure is in Big Endian format */
  933. uint8_t elsCode; /* FC Word 0, bit 24:31 */
  934. uint8_t elsByte1;
  935. uint8_t elsByte2;
  936. uint8_t elsByte3;
  937. union {
  938. struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
  939. struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
  940. LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
  941. PRLI prli; /* Payload for PRLI/ACC */
  942. PRLO prlo; /* Payload for PRLO/ACC */
  943. ADISC adisc; /* Payload for ADISC/ACC */
  944. FARP farp; /* Payload for FARP/ACC */
  945. FAN fan; /* Payload for FAN */
  946. SCR scr; /* Payload for SCR/ACC */
  947. RNID rnid; /* Payload for RNID */
  948. uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
  949. } un;
  950. } ELS_PKT;
  951. /*
  952. * Link Cable Beacon (LCB) ELS Frame
  953. */
  954. struct fc_lcb_request_frame {
  955. uint32_t lcb_command; /* ELS command opcode (0x81) */
  956. uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
  957. #define LPFC_LCB_ON 0x1
  958. #define LPFC_LCB_OFF 0x2
  959. uint8_t reserved[2];
  960. uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
  961. uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
  962. #define LPFC_LCB_GREEN 0x1
  963. #define LPFC_LCB_AMBER 0x2
  964. uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
  965. #define LCB_CAPABILITY_DURATION 1
  966. #define BEACON_VERSION_V1 1
  967. #define BEACON_VERSION_V0 0
  968. uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
  969. };
  970. /*
  971. * Link Cable Beacon (LCB) ELS Response Frame
  972. */
  973. struct fc_lcb_res_frame {
  974. uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
  975. uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
  976. uint8_t reserved[2];
  977. uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
  978. uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
  979. uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
  980. uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
  981. };
  982. /*
  983. * Read Diagnostic Parameters (RDP) ELS frame.
  984. */
  985. #define SFF_PG0_IDENT_SFP 0x3
  986. #define SFP_FLAG_PT_OPTICAL 0x0
  987. #define SFP_FLAG_PT_SWLASER 0x01
  988. #define SFP_FLAG_PT_LWLASER_LC1310 0x02
  989. #define SFP_FLAG_PT_LWLASER_LL1550 0x03
  990. #define SFP_FLAG_PT_MASK 0x0F
  991. #define SFP_FLAG_PT_SHIFT 0
  992. #define SFP_FLAG_IS_OPTICAL_PORT 0x01
  993. #define SFP_FLAG_IS_OPTICAL_MASK 0x010
  994. #define SFP_FLAG_IS_OPTICAL_SHIFT 4
  995. #define SFP_FLAG_IS_DESC_VALID 0x01
  996. #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
  997. #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
  998. #define SFP_FLAG_CT_UNKNOWN 0x0
  999. #define SFP_FLAG_CT_SFP_PLUS 0x01
  1000. #define SFP_FLAG_CT_MASK 0x3C
  1001. #define SFP_FLAG_CT_SHIFT 6
  1002. struct fc_rdp_port_name_info {
  1003. uint8_t wwnn[8];
  1004. uint8_t wwpn[8];
  1005. };
  1006. /*
  1007. * Link Error Status Block Structure (FC-FS-3) for RDP
  1008. * This similar to RPS ELS
  1009. */
  1010. struct fc_link_status {
  1011. uint32_t link_failure_cnt;
  1012. uint32_t loss_of_synch_cnt;
  1013. uint32_t loss_of_signal_cnt;
  1014. uint32_t primitive_seq_proto_err;
  1015. uint32_t invalid_trans_word;
  1016. uint32_t invalid_crc_cnt;
  1017. };
  1018. #define RDP_PORT_NAMES_DESC_TAG 0x00010003
  1019. struct fc_rdp_port_name_desc {
  1020. uint32_t tag; /* 0001 0003h */
  1021. uint32_t length; /* set to size of payload struct */
  1022. struct fc_rdp_port_name_info port_names;
  1023. };
  1024. struct fc_rdp_fec_info {
  1025. uint32_t CorrectedBlocks;
  1026. uint32_t UncorrectableBlocks;
  1027. };
  1028. #define RDP_FEC_DESC_TAG 0x00010005
  1029. struct fc_fec_rdp_desc {
  1030. uint32_t tag;
  1031. uint32_t length;
  1032. struct fc_rdp_fec_info info;
  1033. };
  1034. struct fc_rdp_link_error_status_payload_info {
  1035. struct fc_link_status link_status; /* 24 bytes */
  1036. uint32_t port_type; /* bits 31-30 only */
  1037. };
  1038. #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
  1039. struct fc_rdp_link_error_status_desc {
  1040. uint32_t tag; /* 0001 0002h */
  1041. uint32_t length; /* set to size of payload struct */
  1042. struct fc_rdp_link_error_status_payload_info info;
  1043. };
  1044. #define VN_PT_PHY_UNKNOWN 0x00
  1045. #define VN_PT_PHY_PF_PORT 0x01
  1046. #define VN_PT_PHY_ETH_MAC 0x10
  1047. #define VN_PT_PHY_SHIFT 30
  1048. #define RDP_PS_1GB 0x8000
  1049. #define RDP_PS_2GB 0x4000
  1050. #define RDP_PS_4GB 0x2000
  1051. #define RDP_PS_10GB 0x1000
  1052. #define RDP_PS_8GB 0x0800
  1053. #define RDP_PS_16GB 0x0400
  1054. #define RDP_PS_32GB 0x0200
  1055. #define RDP_PS_64GB 0x0100
  1056. #define RDP_PS_128GB 0x0080
  1057. #define RDP_PS_256GB 0x0040
  1058. #define RDP_CAP_USER_CONFIGURED 0x0002
  1059. #define RDP_CAP_UNKNOWN 0x0001
  1060. #define RDP_PS_UNKNOWN 0x0002
  1061. #define RDP_PS_NOT_ESTABLISHED 0x0001
  1062. struct fc_rdp_port_speed {
  1063. uint16_t capabilities;
  1064. uint16_t speed;
  1065. };
  1066. struct fc_rdp_port_speed_info {
  1067. struct fc_rdp_port_speed port_speed;
  1068. };
  1069. #define RDP_PORT_SPEED_DESC_TAG 0x00010001
  1070. struct fc_rdp_port_speed_desc {
  1071. uint32_t tag; /* 00010001h */
  1072. uint32_t length; /* set to size of payload struct */
  1073. struct fc_rdp_port_speed_info info;
  1074. };
  1075. #define RDP_NPORT_ID_SIZE 4
  1076. #define RDP_N_PORT_DESC_TAG 0x00000003
  1077. struct fc_rdp_nport_desc {
  1078. uint32_t tag; /* 0000 0003h, big endian */
  1079. uint32_t length; /* size of RDP_N_PORT_ID struct */
  1080. uint32_t nport_id : 12;
  1081. uint32_t reserved : 8;
  1082. };
  1083. struct fc_rdp_link_service_info {
  1084. uint32_t els_req; /* Request payload word 0 value.*/
  1085. };
  1086. #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
  1087. struct fc_rdp_link_service_desc {
  1088. uint32_t tag; /* Descriptor tag 1 */
  1089. uint32_t length; /* set to size of payload struct. */
  1090. struct fc_rdp_link_service_info payload;
  1091. /* must be ELS req Word 0(0x18) */
  1092. };
  1093. struct fc_rdp_sfp_info {
  1094. uint16_t temperature;
  1095. uint16_t vcc;
  1096. uint16_t tx_bias;
  1097. uint16_t tx_power;
  1098. uint16_t rx_power;
  1099. uint16_t flags;
  1100. };
  1101. #define RDP_SFP_DESC_TAG 0x00010000
  1102. struct fc_rdp_sfp_desc {
  1103. uint32_t tag;
  1104. uint32_t length; /* set to size of sfp_info struct */
  1105. struct fc_rdp_sfp_info sfp_info;
  1106. };
  1107. /* Buffer Credit Descriptor */
  1108. struct fc_rdp_bbc_info {
  1109. uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
  1110. uint32_t attached_port_bbc;
  1111. uint32_t rtt; /* Round trip time */
  1112. };
  1113. #define RDP_BBC_DESC_TAG 0x00010006
  1114. struct fc_rdp_bbc_desc {
  1115. uint32_t tag;
  1116. uint32_t length;
  1117. struct fc_rdp_bbc_info bbc_info;
  1118. };
  1119. /* Optical Element Type Transgression Flags */
  1120. #define RDP_OET_LOW_WARNING 0x1
  1121. #define RDP_OET_HIGH_WARNING 0x2
  1122. #define RDP_OET_LOW_ALARM 0x4
  1123. #define RDP_OET_HIGH_ALARM 0x8
  1124. #define RDP_OED_TEMPERATURE 0x1
  1125. #define RDP_OED_VOLTAGE 0x2
  1126. #define RDP_OED_TXBIAS 0x3
  1127. #define RDP_OED_TXPOWER 0x4
  1128. #define RDP_OED_RXPOWER 0x5
  1129. #define RDP_OED_TYPE_SHIFT 28
  1130. /* Optical Element Data descriptor */
  1131. struct fc_rdp_oed_info {
  1132. uint16_t hi_alarm;
  1133. uint16_t lo_alarm;
  1134. uint16_t hi_warning;
  1135. uint16_t lo_warning;
  1136. uint32_t function_flags;
  1137. };
  1138. #define RDP_OED_DESC_TAG 0x00010007
  1139. struct fc_rdp_oed_sfp_desc {
  1140. uint32_t tag;
  1141. uint32_t length;
  1142. struct fc_rdp_oed_info oed_info;
  1143. };
  1144. /* Optical Product Data descriptor */
  1145. struct fc_rdp_opd_sfp_info {
  1146. uint8_t vendor_name[16];
  1147. uint8_t model_number[16];
  1148. uint8_t serial_number[16];
  1149. uint8_t revision[4];
  1150. uint8_t date[8];
  1151. };
  1152. #define RDP_OPD_DESC_TAG 0x00010008
  1153. struct fc_rdp_opd_sfp_desc {
  1154. uint32_t tag;
  1155. uint32_t length;
  1156. struct fc_rdp_opd_sfp_info opd_info;
  1157. };
  1158. struct fc_rdp_req_frame {
  1159. uint32_t rdp_command; /* ELS command opcode (0x18)*/
  1160. uint32_t rdp_des_length; /* RDP Payload Word 1 */
  1161. struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
  1162. };
  1163. struct fc_rdp_res_frame {
  1164. uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
  1165. uint32_t length; /* FC Word 1 */
  1166. struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
  1167. struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
  1168. struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
  1169. struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
  1170. struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
  1171. struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
  1172. struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
  1173. struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
  1174. struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
  1175. struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
  1176. struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
  1177. struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
  1178. struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
  1179. struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
  1180. };
  1181. /******** FDMI ********/
  1182. /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
  1183. #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
  1184. /* Definitions for HBA / Port attribute entries */
  1185. /* Attribute Entry */
  1186. struct lpfc_fdmi_attr_entry {
  1187. union {
  1188. uint32_t AttrInt;
  1189. uint8_t AttrTypes[32];
  1190. uint8_t AttrString[256];
  1191. struct lpfc_name AttrWWN;
  1192. } un;
  1193. };
  1194. struct lpfc_fdmi_attr_def { /* Defined in TLV format */
  1195. /* Structure is in Big Endian format */
  1196. uint32_t AttrType:16;
  1197. uint32_t AttrLen:16;
  1198. /* Marks start of Value (ATTRIBUTE_ENTRY) */
  1199. struct lpfc_fdmi_attr_entry AttrValue;
  1200. } __packed;
  1201. /*
  1202. * HBA Attribute Block
  1203. */
  1204. struct lpfc_fdmi_attr_block {
  1205. uint32_t EntryCnt; /* Number of HBA attribute entries */
  1206. struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
  1207. };
  1208. /*
  1209. * Port Entry
  1210. */
  1211. struct lpfc_fdmi_port_entry {
  1212. struct lpfc_name PortName;
  1213. };
  1214. /*
  1215. * HBA Identifier
  1216. */
  1217. struct lpfc_fdmi_hba_ident {
  1218. struct lpfc_name PortName;
  1219. };
  1220. /*
  1221. * Registered Port List Format
  1222. */
  1223. struct lpfc_fdmi_reg_port_list {
  1224. uint32_t EntryCnt;
  1225. struct lpfc_fdmi_port_entry pe;
  1226. } __packed;
  1227. /*
  1228. * Register HBA(RHBA)
  1229. */
  1230. struct lpfc_fdmi_reg_hba {
  1231. struct lpfc_fdmi_hba_ident hi;
  1232. struct lpfc_fdmi_reg_port_list rpl;
  1233. };
  1234. /*
  1235. * Register HBA Attributes (RHAT)
  1236. */
  1237. struct lpfc_fdmi_reg_hbaattr {
  1238. struct lpfc_name HBA_PortName;
  1239. struct lpfc_fdmi_attr_block ab;
  1240. };
  1241. /*
  1242. * Register Port Attributes (RPA)
  1243. */
  1244. struct lpfc_fdmi_reg_portattr {
  1245. struct lpfc_name PortName;
  1246. struct lpfc_fdmi_attr_block ab;
  1247. };
  1248. /*
  1249. * HBA MAnagement Operations Command Codes
  1250. */
  1251. #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
  1252. #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
  1253. #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
  1254. #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
  1255. #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
  1256. #define SLI_MGMT_RHBA 0x200 /* Register HBA */
  1257. #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
  1258. #define SLI_MGMT_RPRT 0x210 /* Register Port */
  1259. #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
  1260. #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
  1261. #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
  1262. #define SLI_MGMT_DPRT 0x310 /* De-register Port */
  1263. #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
  1264. #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
  1265. /*
  1266. * HBA Attribute Types
  1267. */
  1268. #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
  1269. #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
  1270. #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
  1271. #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
  1272. #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
  1273. #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
  1274. #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
  1275. #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
  1276. #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
  1277. #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
  1278. #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
  1279. #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
  1280. #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
  1281. #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
  1282. #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
  1283. #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
  1284. #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
  1285. #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
  1286. /* Bit mask for all individual HBA attributes */
  1287. #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
  1288. #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
  1289. #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
  1290. #define LPFC_FDMI_HBA_ATTR_model 0x00000008
  1291. #define LPFC_FDMI_HBA_ATTR_description 0x00000010
  1292. #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
  1293. #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
  1294. #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
  1295. #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
  1296. #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
  1297. #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
  1298. #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
  1299. #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
  1300. #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
  1301. #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
  1302. #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
  1303. #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
  1304. #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
  1305. /* Bit mask for FDMI-1 defined HBA attributes */
  1306. #define LPFC_FDMI1_HBA_ATTR 0x000007ff
  1307. /* Bit mask for FDMI-2 defined HBA attributes */
  1308. /* Skip vendor_info and bios_state */
  1309. #define LPFC_FDMI2_HBA_ATTR 0x0002efff
  1310. /*
  1311. * Port Attrubute Types
  1312. */
  1313. #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
  1314. #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
  1315. #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
  1316. #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
  1317. #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
  1318. #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
  1319. #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
  1320. #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
  1321. #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
  1322. #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
  1323. #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
  1324. #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
  1325. #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
  1326. #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
  1327. #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
  1328. #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
  1329. #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
  1330. #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
  1331. #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
  1332. #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
  1333. #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
  1334. #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
  1335. #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
  1336. /* Bit mask for all individual PORT attributes */
  1337. #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
  1338. #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
  1339. #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
  1340. #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
  1341. #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
  1342. #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
  1343. #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
  1344. #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
  1345. #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
  1346. #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
  1347. #define LPFC_FDMI_PORT_ATTR_class 0x00000400
  1348. #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
  1349. #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
  1350. #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
  1351. #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
  1352. #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
  1353. #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
  1354. #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
  1355. #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
  1356. #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
  1357. #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
  1358. #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
  1359. #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
  1360. /* Bit mask for FDMI-1 defined PORT attributes */
  1361. #define LPFC_FDMI1_PORT_ATTR 0x0000003f
  1362. /* Bit mask for FDMI-2 defined PORT attributes */
  1363. #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
  1364. /* Bit mask for Smart SAN defined PORT attributes */
  1365. #define LPFC_FDMI2_SMART_ATTR 0x007fffff
  1366. /* Defines for PORT port state attribute */
  1367. #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
  1368. #define LPFC_FDMI_PORTSTATE_ONLINE 2
  1369. /* Defines for PORT port type attribute */
  1370. #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
  1371. #define LPFC_FDMI_PORTTYPE_NPORT 1
  1372. #define LPFC_FDMI_PORTTYPE_NLPORT 2
  1373. /*
  1374. * Begin HBA configuration parameters.
  1375. * The PCI configuration register BAR assignments are:
  1376. * BAR0, offset 0x10 - SLIM base memory address
  1377. * BAR1, offset 0x14 - SLIM base memory high address
  1378. * BAR2, offset 0x18 - REGISTER base memory address
  1379. * BAR3, offset 0x1c - REGISTER base memory high address
  1380. * BAR4, offset 0x20 - BIU I/O registers
  1381. * BAR5, offset 0x24 - REGISTER base io high address
  1382. */
  1383. /* Number of rings currently used and available. */
  1384. #define MAX_SLI3_CONFIGURED_RINGS 3
  1385. #define MAX_SLI3_RINGS 4
  1386. /* IOCB / Mailbox is owned by FireFly */
  1387. #define OWN_CHIP 1
  1388. /* IOCB / Mailbox is owned by Host */
  1389. #define OWN_HOST 0
  1390. /* Number of 4-byte words in an IOCB. */
  1391. #define IOCB_WORD_SZ 8
  1392. /* network headers for Dfctl field */
  1393. #define FC_NET_HDR 0x20
  1394. /* Start FireFly Register definitions */
  1395. #define PCI_VENDOR_ID_EMULEX 0x10df
  1396. #define PCI_DEVICE_ID_FIREFLY 0x1ae5
  1397. #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
  1398. #define PCI_DEVICE_ID_BALIUS 0xe131
  1399. #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
  1400. #define PCI_DEVICE_ID_LANCER_FC 0xe200
  1401. #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
  1402. #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
  1403. #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
  1404. #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
  1405. #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
  1406. #define PCI_DEVICE_ID_SAT_SMB 0xf011
  1407. #define PCI_DEVICE_ID_SAT_MID 0xf015
  1408. #define PCI_DEVICE_ID_RFLY 0xf095
  1409. #define PCI_DEVICE_ID_PFLY 0xf098
  1410. #define PCI_DEVICE_ID_LP101 0xf0a1
  1411. #define PCI_DEVICE_ID_TFLY 0xf0a5
  1412. #define PCI_DEVICE_ID_BSMB 0xf0d1
  1413. #define PCI_DEVICE_ID_BMID 0xf0d5
  1414. #define PCI_DEVICE_ID_ZSMB 0xf0e1
  1415. #define PCI_DEVICE_ID_ZMID 0xf0e5
  1416. #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
  1417. #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
  1418. #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
  1419. #define PCI_DEVICE_ID_SAT 0xf100
  1420. #define PCI_DEVICE_ID_SAT_SCSP 0xf111
  1421. #define PCI_DEVICE_ID_SAT_DCSP 0xf112
  1422. #define PCI_DEVICE_ID_FALCON 0xf180
  1423. #define PCI_DEVICE_ID_SUPERFLY 0xf700
  1424. #define PCI_DEVICE_ID_DRAGONFLY 0xf800
  1425. #define PCI_DEVICE_ID_CENTAUR 0xf900
  1426. #define PCI_DEVICE_ID_PEGASUS 0xf980
  1427. #define PCI_DEVICE_ID_THOR 0xfa00
  1428. #define PCI_DEVICE_ID_VIPER 0xfb00
  1429. #define PCI_DEVICE_ID_LP10000S 0xfc00
  1430. #define PCI_DEVICE_ID_LP11000S 0xfc10
  1431. #define PCI_DEVICE_ID_LPE11000S 0xfc20
  1432. #define PCI_DEVICE_ID_SAT_S 0xfc40
  1433. #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
  1434. #define PCI_DEVICE_ID_HELIOS 0xfd00
  1435. #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
  1436. #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
  1437. #define PCI_DEVICE_ID_ZEPHYR 0xfe00
  1438. #define PCI_DEVICE_ID_HORNET 0xfe05
  1439. #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
  1440. #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
  1441. #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
  1442. #define PCI_DEVICE_ID_TIGERSHARK 0x0704
  1443. #define PCI_DEVICE_ID_TOMCAT 0x0714
  1444. #define PCI_DEVICE_ID_SKYHAWK 0x0724
  1445. #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
  1446. #define JEDEC_ID_ADDRESS 0x0080001c
  1447. #define FIREFLY_JEDEC_ID 0x1ACC
  1448. #define SUPERFLY_JEDEC_ID 0x0020
  1449. #define DRAGONFLY_JEDEC_ID 0x0021
  1450. #define DRAGONFLY_V2_JEDEC_ID 0x0025
  1451. #define CENTAUR_2G_JEDEC_ID 0x0026
  1452. #define CENTAUR_1G_JEDEC_ID 0x0028
  1453. #define PEGASUS_ORION_JEDEC_ID 0x0036
  1454. #define PEGASUS_JEDEC_ID 0x0038
  1455. #define THOR_JEDEC_ID 0x0012
  1456. #define HELIOS_JEDEC_ID 0x0364
  1457. #define ZEPHYR_JEDEC_ID 0x0577
  1458. #define VIPER_JEDEC_ID 0x4838
  1459. #define SATURN_JEDEC_ID 0x1004
  1460. #define HORNET_JDEC_ID 0x2057706D
  1461. #define JEDEC_ID_MASK 0x0FFFF000
  1462. #define JEDEC_ID_SHIFT 12
  1463. #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
  1464. typedef struct { /* FireFly BIU registers */
  1465. uint32_t hostAtt; /* See definitions for Host Attention
  1466. register */
  1467. uint32_t chipAtt; /* See definitions for Chip Attention
  1468. register */
  1469. uint32_t hostStatus; /* See definitions for Host Status register */
  1470. uint32_t hostControl; /* See definitions for Host Control register */
  1471. uint32_t buiConfig; /* See definitions for BIU configuration
  1472. register */
  1473. } FF_REGS;
  1474. /* IO Register size in bytes */
  1475. #define FF_REG_AREA_SIZE 256
  1476. /* Host Attention Register */
  1477. #define HA_REG_OFFSET 0 /* Byte offset from register base address */
  1478. #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
  1479. #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
  1480. #define HA_R0ATT 0x00000008 /* Bit 3 */
  1481. #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
  1482. #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
  1483. #define HA_R1ATT 0x00000080 /* Bit 7 */
  1484. #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
  1485. #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
  1486. #define HA_R2ATT 0x00000800 /* Bit 11 */
  1487. #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
  1488. #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
  1489. #define HA_R3ATT 0x00008000 /* Bit 15 */
  1490. #define HA_LATT 0x20000000 /* Bit 29 */
  1491. #define HA_MBATT 0x40000000 /* Bit 30 */
  1492. #define HA_ERATT 0x80000000 /* Bit 31 */
  1493. #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
  1494. #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
  1495. #define HA_RXATT 0x00000008 /* Bit 3 */
  1496. #define HA_RXMASK 0x0000000f
  1497. #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
  1498. #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
  1499. #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
  1500. #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
  1501. #define HA_R0_POS 3
  1502. #define HA_R1_POS 7
  1503. #define HA_R2_POS 11
  1504. #define HA_R3_POS 15
  1505. #define HA_LE_POS 29
  1506. #define HA_MB_POS 30
  1507. #define HA_ER_POS 31
  1508. /* Chip Attention Register */
  1509. #define CA_REG_OFFSET 4 /* Byte offset from register base address */
  1510. #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
  1511. #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
  1512. #define CA_R0ATT 0x00000008 /* Bit 3 */
  1513. #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
  1514. #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
  1515. #define CA_R1ATT 0x00000080 /* Bit 7 */
  1516. #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
  1517. #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
  1518. #define CA_R2ATT 0x00000800 /* Bit 11 */
  1519. #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
  1520. #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
  1521. #define CA_R3ATT 0x00008000 /* Bit 15 */
  1522. #define CA_MBATT 0x40000000 /* Bit 30 */
  1523. /* Host Status Register */
  1524. #define HS_REG_OFFSET 8 /* Byte offset from register base address */
  1525. #define HS_MBRDY 0x00400000 /* Bit 22 */
  1526. #define HS_FFRDY 0x00800000 /* Bit 23 */
  1527. #define HS_FFER8 0x01000000 /* Bit 24 */
  1528. #define HS_FFER7 0x02000000 /* Bit 25 */
  1529. #define HS_FFER6 0x04000000 /* Bit 26 */
  1530. #define HS_FFER5 0x08000000 /* Bit 27 */
  1531. #define HS_FFER4 0x10000000 /* Bit 28 */
  1532. #define HS_FFER3 0x20000000 /* Bit 29 */
  1533. #define HS_FFER2 0x40000000 /* Bit 30 */
  1534. #define HS_FFER1 0x80000000 /* Bit 31 */
  1535. #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
  1536. #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
  1537. #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
  1538. /* Host Control Register */
  1539. #define HC_REG_OFFSET 12 /* Byte offset from register base address */
  1540. #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
  1541. #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
  1542. #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
  1543. #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
  1544. #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
  1545. #define HC_INITHBI 0x02000000 /* Bit 25 */
  1546. #define HC_INITMB 0x04000000 /* Bit 26 */
  1547. #define HC_INITFF 0x08000000 /* Bit 27 */
  1548. #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
  1549. #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
  1550. /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
  1551. #define MSIX_DFLT_ID 0
  1552. #define MSIX_RNG0_ID 0
  1553. #define MSIX_RNG1_ID 1
  1554. #define MSIX_RNG2_ID 2
  1555. #define MSIX_RNG3_ID 3
  1556. #define MSIX_LINK_ID 4
  1557. #define MSIX_MBOX_ID 5
  1558. #define MSIX_SPARE0_ID 6
  1559. #define MSIX_SPARE1_ID 7
  1560. /* Mailbox Commands */
  1561. #define MBX_SHUTDOWN 0x00 /* terminate testing */
  1562. #define MBX_LOAD_SM 0x01
  1563. #define MBX_READ_NV 0x02
  1564. #define MBX_WRITE_NV 0x03
  1565. #define MBX_RUN_BIU_DIAG 0x04
  1566. #define MBX_INIT_LINK 0x05
  1567. #define MBX_DOWN_LINK 0x06
  1568. #define MBX_CONFIG_LINK 0x07
  1569. #define MBX_CONFIG_RING 0x09
  1570. #define MBX_RESET_RING 0x0A
  1571. #define MBX_READ_CONFIG 0x0B
  1572. #define MBX_READ_RCONFIG 0x0C
  1573. #define MBX_READ_SPARM 0x0D
  1574. #define MBX_READ_STATUS 0x0E
  1575. #define MBX_READ_RPI 0x0F
  1576. #define MBX_READ_XRI 0x10
  1577. #define MBX_READ_REV 0x11
  1578. #define MBX_READ_LNK_STAT 0x12
  1579. #define MBX_REG_LOGIN 0x13
  1580. #define MBX_UNREG_LOGIN 0x14
  1581. #define MBX_CLEAR_LA 0x16
  1582. #define MBX_DUMP_MEMORY 0x17
  1583. #define MBX_DUMP_CONTEXT 0x18
  1584. #define MBX_RUN_DIAGS 0x19
  1585. #define MBX_RESTART 0x1A
  1586. #define MBX_UPDATE_CFG 0x1B
  1587. #define MBX_DOWN_LOAD 0x1C
  1588. #define MBX_DEL_LD_ENTRY 0x1D
  1589. #define MBX_RUN_PROGRAM 0x1E
  1590. #define MBX_SET_MASK 0x20
  1591. #define MBX_SET_VARIABLE 0x21
  1592. #define MBX_UNREG_D_ID 0x23
  1593. #define MBX_KILL_BOARD 0x24
  1594. #define MBX_CONFIG_FARP 0x25
  1595. #define MBX_BEACON 0x2A
  1596. #define MBX_CONFIG_MSI 0x30
  1597. #define MBX_HEARTBEAT 0x31
  1598. #define MBX_WRITE_VPARMS 0x32
  1599. #define MBX_ASYNCEVT_ENABLE 0x33
  1600. #define MBX_READ_EVENT_LOG_STATUS 0x37
  1601. #define MBX_READ_EVENT_LOG 0x38
  1602. #define MBX_WRITE_EVENT_LOG 0x39
  1603. #define MBX_PORT_CAPABILITIES 0x3B
  1604. #define MBX_PORT_IOV_CONTROL 0x3C
  1605. #define MBX_CONFIG_HBQ 0x7C
  1606. #define MBX_LOAD_AREA 0x81
  1607. #define MBX_RUN_BIU_DIAG64 0x84
  1608. #define MBX_CONFIG_PORT 0x88
  1609. #define MBX_READ_SPARM64 0x8D
  1610. #define MBX_READ_RPI64 0x8F
  1611. #define MBX_REG_LOGIN64 0x93
  1612. #define MBX_READ_TOPOLOGY 0x95
  1613. #define MBX_REG_VPI 0x96
  1614. #define MBX_UNREG_VPI 0x97
  1615. #define MBX_WRITE_WWN 0x98
  1616. #define MBX_SET_DEBUG 0x99
  1617. #define MBX_LOAD_EXP_ROM 0x9C
  1618. #define MBX_SLI4_CONFIG 0x9B
  1619. #define MBX_SLI4_REQ_FTRS 0x9D
  1620. #define MBX_MAX_CMDS 0x9E
  1621. #define MBX_RESUME_RPI 0x9E
  1622. #define MBX_SLI2_CMD_MASK 0x80
  1623. #define MBX_REG_VFI 0x9F
  1624. #define MBX_REG_FCFI 0xA0
  1625. #define MBX_UNREG_VFI 0xA1
  1626. #define MBX_UNREG_FCFI 0xA2
  1627. #define MBX_INIT_VFI 0xA3
  1628. #define MBX_INIT_VPI 0xA4
  1629. #define MBX_ACCESS_VDATA 0xA5
  1630. #define MBX_REG_FCFI_MRQ 0xAF
  1631. #define MBX_AUTH_PORT 0xF8
  1632. #define MBX_SECURITY_MGMT 0xF9
  1633. /* IOCB Commands */
  1634. #define CMD_RCV_SEQUENCE_CX 0x01
  1635. #define CMD_XMIT_SEQUENCE_CR 0x02
  1636. #define CMD_XMIT_SEQUENCE_CX 0x03
  1637. #define CMD_XMIT_BCAST_CN 0x04
  1638. #define CMD_XMIT_BCAST_CX 0x05
  1639. #define CMD_QUE_RING_BUF_CN 0x06
  1640. #define CMD_QUE_XRI_BUF_CX 0x07
  1641. #define CMD_IOCB_CONTINUE_CN 0x08
  1642. #define CMD_RET_XRI_BUF_CX 0x09
  1643. #define CMD_ELS_REQUEST_CR 0x0A
  1644. #define CMD_ELS_REQUEST_CX 0x0B
  1645. #define CMD_RCV_ELS_REQ_CX 0x0D
  1646. #define CMD_ABORT_XRI_CN 0x0E
  1647. #define CMD_ABORT_XRI_CX 0x0F
  1648. #define CMD_CLOSE_XRI_CN 0x10
  1649. #define CMD_CLOSE_XRI_CX 0x11
  1650. #define CMD_CREATE_XRI_CR 0x12
  1651. #define CMD_CREATE_XRI_CX 0x13
  1652. #define CMD_GET_RPI_CN 0x14
  1653. #define CMD_XMIT_ELS_RSP_CX 0x15
  1654. #define CMD_GET_RPI_CR 0x16
  1655. #define CMD_XRI_ABORTED_CX 0x17
  1656. #define CMD_FCP_IWRITE_CR 0x18
  1657. #define CMD_FCP_IWRITE_CX 0x19
  1658. #define CMD_FCP_IREAD_CR 0x1A
  1659. #define CMD_FCP_IREAD_CX 0x1B
  1660. #define CMD_FCP_ICMND_CR 0x1C
  1661. #define CMD_FCP_ICMND_CX 0x1D
  1662. #define CMD_FCP_TSEND_CX 0x1F
  1663. #define CMD_FCP_TRECEIVE_CX 0x21
  1664. #define CMD_FCP_TRSP_CX 0x23
  1665. #define CMD_FCP_AUTO_TRSP_CX 0x29
  1666. #define CMD_ADAPTER_MSG 0x20
  1667. #define CMD_ADAPTER_DUMP 0x22
  1668. /* SLI_2 IOCB Command Set */
  1669. #define CMD_ASYNC_STATUS 0x7C
  1670. #define CMD_RCV_SEQUENCE64_CX 0x81
  1671. #define CMD_XMIT_SEQUENCE64_CR 0x82
  1672. #define CMD_XMIT_SEQUENCE64_CX 0x83
  1673. #define CMD_XMIT_BCAST64_CN 0x84
  1674. #define CMD_XMIT_BCAST64_CX 0x85
  1675. #define CMD_QUE_RING_BUF64_CN 0x86
  1676. #define CMD_QUE_XRI_BUF64_CX 0x87
  1677. #define CMD_IOCB_CONTINUE64_CN 0x88
  1678. #define CMD_RET_XRI_BUF64_CX 0x89
  1679. #define CMD_ELS_REQUEST64_CR 0x8A
  1680. #define CMD_ELS_REQUEST64_CX 0x8B
  1681. #define CMD_ABORT_MXRI64_CN 0x8C
  1682. #define CMD_RCV_ELS_REQ64_CX 0x8D
  1683. #define CMD_XMIT_ELS_RSP64_CX 0x95
  1684. #define CMD_XMIT_BLS_RSP64_CX 0x97
  1685. #define CMD_FCP_IWRITE64_CR 0x98
  1686. #define CMD_FCP_IWRITE64_CX 0x99
  1687. #define CMD_FCP_IREAD64_CR 0x9A
  1688. #define CMD_FCP_IREAD64_CX 0x9B
  1689. #define CMD_FCP_ICMND64_CR 0x9C
  1690. #define CMD_FCP_ICMND64_CX 0x9D
  1691. #define CMD_FCP_TSEND64_CX 0x9F
  1692. #define CMD_FCP_TRECEIVE64_CX 0xA1
  1693. #define CMD_FCP_TRSP64_CX 0xA3
  1694. #define CMD_QUE_XRI64_CX 0xB3
  1695. #define CMD_IOCB_RCV_SEQ64_CX 0xB5
  1696. #define CMD_IOCB_RCV_ELS64_CX 0xB7
  1697. #define CMD_IOCB_RET_XRI64_CX 0xB9
  1698. #define CMD_IOCB_RCV_CONT64_CX 0xBB
  1699. #define CMD_GEN_REQUEST64_CR 0xC2
  1700. #define CMD_GEN_REQUEST64_CX 0xC3
  1701. /* Unhandled SLI-3 Commands */
  1702. #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
  1703. #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
  1704. #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
  1705. #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
  1706. #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
  1707. #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
  1708. #define CMD_IOCB_RET_HBQE64_CN 0xCA
  1709. #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
  1710. #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
  1711. #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
  1712. #define CMD_IOCB_LOGENTRY_CN 0x94
  1713. #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
  1714. /* Data Security SLI Commands */
  1715. #define DSSCMD_IWRITE64_CR 0xF8
  1716. #define DSSCMD_IWRITE64_CX 0xF9
  1717. #define DSSCMD_IREAD64_CR 0xFA
  1718. #define DSSCMD_IREAD64_CX 0xFB
  1719. #define CMD_MAX_IOCB_CMD 0xFB
  1720. #define CMD_IOCB_MASK 0xff
  1721. #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
  1722. iocb */
  1723. #define LPFC_MAX_ADPTMSG 32 /* max msg data */
  1724. /*
  1725. * Define Status
  1726. */
  1727. #define MBX_SUCCESS 0
  1728. #define MBXERR_NUM_RINGS 1
  1729. #define MBXERR_NUM_IOCBS 2
  1730. #define MBXERR_IOCBS_EXCEEDED 3
  1731. #define MBXERR_BAD_RING_NUMBER 4
  1732. #define MBXERR_MASK_ENTRIES_RANGE 5
  1733. #define MBXERR_MASKS_EXCEEDED 6
  1734. #define MBXERR_BAD_PROFILE 7
  1735. #define MBXERR_BAD_DEF_CLASS 8
  1736. #define MBXERR_BAD_MAX_RESPONDER 9
  1737. #define MBXERR_BAD_MAX_ORIGINATOR 10
  1738. #define MBXERR_RPI_REGISTERED 11
  1739. #define MBXERR_RPI_FULL 12
  1740. #define MBXERR_NO_RESOURCES 13
  1741. #define MBXERR_BAD_RCV_LENGTH 14
  1742. #define MBXERR_DMA_ERROR 15
  1743. #define MBXERR_ERROR 16
  1744. #define MBXERR_LINK_DOWN 0x33
  1745. #define MBXERR_SEC_NO_PERMISSION 0xF02
  1746. #define MBX_NOT_FINISHED 255
  1747. #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
  1748. #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
  1749. #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
  1750. /*
  1751. * return code Fail
  1752. */
  1753. #define FAILURE 1
  1754. /*
  1755. * Begin Structure Definitions for Mailbox Commands
  1756. */
  1757. typedef struct {
  1758. #ifdef __BIG_ENDIAN_BITFIELD
  1759. uint8_t tval;
  1760. uint8_t tmask;
  1761. uint8_t rval;
  1762. uint8_t rmask;
  1763. #else /* __LITTLE_ENDIAN_BITFIELD */
  1764. uint8_t rmask;
  1765. uint8_t rval;
  1766. uint8_t tmask;
  1767. uint8_t tval;
  1768. #endif
  1769. } RR_REG;
  1770. struct ulp_bde {
  1771. uint32_t bdeAddress;
  1772. #ifdef __BIG_ENDIAN_BITFIELD
  1773. uint32_t bdeReserved:4;
  1774. uint32_t bdeAddrHigh:4;
  1775. uint32_t bdeSize:24;
  1776. #else /* __LITTLE_ENDIAN_BITFIELD */
  1777. uint32_t bdeSize:24;
  1778. uint32_t bdeAddrHigh:4;
  1779. uint32_t bdeReserved:4;
  1780. #endif
  1781. };
  1782. typedef struct ULP_BDL { /* SLI-2 */
  1783. #ifdef __BIG_ENDIAN_BITFIELD
  1784. uint32_t bdeFlags:8; /* BDL Flags */
  1785. uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
  1786. #else /* __LITTLE_ENDIAN_BITFIELD */
  1787. uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
  1788. uint32_t bdeFlags:8; /* BDL Flags */
  1789. #endif
  1790. uint32_t addrLow; /* Address 0:31 */
  1791. uint32_t addrHigh; /* Address 32:63 */
  1792. uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
  1793. } ULP_BDL;
  1794. /*
  1795. * BlockGuard Definitions
  1796. */
  1797. enum lpfc_protgrp_type {
  1798. LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
  1799. LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
  1800. LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
  1801. LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
  1802. };
  1803. /* PDE Descriptors */
  1804. #define LPFC_PDE5_DESCRIPTOR 0x85
  1805. #define LPFC_PDE6_DESCRIPTOR 0x86
  1806. #define LPFC_PDE7_DESCRIPTOR 0x87
  1807. /* BlockGuard Opcodes */
  1808. #define BG_OP_IN_NODIF_OUT_CRC 0x0
  1809. #define BG_OP_IN_CRC_OUT_NODIF 0x1
  1810. #define BG_OP_IN_NODIF_OUT_CSUM 0x2
  1811. #define BG_OP_IN_CSUM_OUT_NODIF 0x3
  1812. #define BG_OP_IN_CRC_OUT_CRC 0x4
  1813. #define BG_OP_IN_CSUM_OUT_CSUM 0x5
  1814. #define BG_OP_IN_CRC_OUT_CSUM 0x6
  1815. #define BG_OP_IN_CSUM_OUT_CRC 0x7
  1816. #define BG_OP_RAW_MODE 0x8
  1817. struct lpfc_pde5 {
  1818. uint32_t word0;
  1819. #define pde5_type_SHIFT 24
  1820. #define pde5_type_MASK 0x000000ff
  1821. #define pde5_type_WORD word0
  1822. #define pde5_rsvd0_SHIFT 0
  1823. #define pde5_rsvd0_MASK 0x00ffffff
  1824. #define pde5_rsvd0_WORD word0
  1825. uint32_t reftag; /* Reference Tag Value */
  1826. uint32_t reftagtr; /* Reference Tag Translation Value */
  1827. };
  1828. struct lpfc_pde6 {
  1829. uint32_t word0;
  1830. #define pde6_type_SHIFT 24
  1831. #define pde6_type_MASK 0x000000ff
  1832. #define pde6_type_WORD word0
  1833. #define pde6_rsvd0_SHIFT 0
  1834. #define pde6_rsvd0_MASK 0x00ffffff
  1835. #define pde6_rsvd0_WORD word0
  1836. uint32_t word1;
  1837. #define pde6_rsvd1_SHIFT 26
  1838. #define pde6_rsvd1_MASK 0x0000003f
  1839. #define pde6_rsvd1_WORD word1
  1840. #define pde6_na_SHIFT 25
  1841. #define pde6_na_MASK 0x00000001
  1842. #define pde6_na_WORD word1
  1843. #define pde6_rsvd2_SHIFT 16
  1844. #define pde6_rsvd2_MASK 0x000001FF
  1845. #define pde6_rsvd2_WORD word1
  1846. #define pde6_apptagtr_SHIFT 0
  1847. #define pde6_apptagtr_MASK 0x0000ffff
  1848. #define pde6_apptagtr_WORD word1
  1849. uint32_t word2;
  1850. #define pde6_optx_SHIFT 28
  1851. #define pde6_optx_MASK 0x0000000f
  1852. #define pde6_optx_WORD word2
  1853. #define pde6_oprx_SHIFT 24
  1854. #define pde6_oprx_MASK 0x0000000f
  1855. #define pde6_oprx_WORD word2
  1856. #define pde6_nr_SHIFT 23
  1857. #define pde6_nr_MASK 0x00000001
  1858. #define pde6_nr_WORD word2
  1859. #define pde6_ce_SHIFT 22
  1860. #define pde6_ce_MASK 0x00000001
  1861. #define pde6_ce_WORD word2
  1862. #define pde6_re_SHIFT 21
  1863. #define pde6_re_MASK 0x00000001
  1864. #define pde6_re_WORD word2
  1865. #define pde6_ae_SHIFT 20
  1866. #define pde6_ae_MASK 0x00000001
  1867. #define pde6_ae_WORD word2
  1868. #define pde6_ai_SHIFT 19
  1869. #define pde6_ai_MASK 0x00000001
  1870. #define pde6_ai_WORD word2
  1871. #define pde6_bs_SHIFT 16
  1872. #define pde6_bs_MASK 0x00000007
  1873. #define pde6_bs_WORD word2
  1874. #define pde6_apptagval_SHIFT 0
  1875. #define pde6_apptagval_MASK 0x0000ffff
  1876. #define pde6_apptagval_WORD word2
  1877. };
  1878. struct lpfc_pde7 {
  1879. uint32_t word0;
  1880. #define pde7_type_SHIFT 24
  1881. #define pde7_type_MASK 0x000000ff
  1882. #define pde7_type_WORD word0
  1883. #define pde7_rsvd0_SHIFT 0
  1884. #define pde7_rsvd0_MASK 0x00ffffff
  1885. #define pde7_rsvd0_WORD word0
  1886. uint32_t addrHigh;
  1887. uint32_t addrLow;
  1888. };
  1889. /* Structure for MB Command LOAD_SM and DOWN_LOAD */
  1890. typedef struct {
  1891. #ifdef __BIG_ENDIAN_BITFIELD
  1892. uint32_t rsvd2:25;
  1893. uint32_t acknowledgment:1;
  1894. uint32_t version:1;
  1895. uint32_t erase_or_prog:1;
  1896. uint32_t update_flash:1;
  1897. uint32_t update_ram:1;
  1898. uint32_t method:1;
  1899. uint32_t load_cmplt:1;
  1900. #else /* __LITTLE_ENDIAN_BITFIELD */
  1901. uint32_t load_cmplt:1;
  1902. uint32_t method:1;
  1903. uint32_t update_ram:1;
  1904. uint32_t update_flash:1;
  1905. uint32_t erase_or_prog:1;
  1906. uint32_t version:1;
  1907. uint32_t acknowledgment:1;
  1908. uint32_t rsvd2:25;
  1909. #endif
  1910. uint32_t dl_to_adr_low;
  1911. uint32_t dl_to_adr_high;
  1912. uint32_t dl_len;
  1913. union {
  1914. uint32_t dl_from_mbx_offset;
  1915. struct ulp_bde dl_from_bde;
  1916. struct ulp_bde64 dl_from_bde64;
  1917. } un;
  1918. } LOAD_SM_VAR;
  1919. /* Structure for MB Command READ_NVPARM (02) */
  1920. typedef struct {
  1921. uint32_t rsvd1[3]; /* Read as all one's */
  1922. uint32_t rsvd2; /* Read as all zero's */
  1923. uint32_t portname[2]; /* N_PORT name */
  1924. uint32_t nodename[2]; /* NODE name */
  1925. #ifdef __BIG_ENDIAN_BITFIELD
  1926. uint32_t pref_DID:24;
  1927. uint32_t hardAL_PA:8;
  1928. #else /* __LITTLE_ENDIAN_BITFIELD */
  1929. uint32_t hardAL_PA:8;
  1930. uint32_t pref_DID:24;
  1931. #endif
  1932. uint32_t rsvd3[21]; /* Read as all one's */
  1933. } READ_NV_VAR;
  1934. /* Structure for MB Command WRITE_NVPARMS (03) */
  1935. typedef struct {
  1936. uint32_t rsvd1[3]; /* Must be all one's */
  1937. uint32_t rsvd2; /* Must be all zero's */
  1938. uint32_t portname[2]; /* N_PORT name */
  1939. uint32_t nodename[2]; /* NODE name */
  1940. #ifdef __BIG_ENDIAN_BITFIELD
  1941. uint32_t pref_DID:24;
  1942. uint32_t hardAL_PA:8;
  1943. #else /* __LITTLE_ENDIAN_BITFIELD */
  1944. uint32_t hardAL_PA:8;
  1945. uint32_t pref_DID:24;
  1946. #endif
  1947. uint32_t rsvd3[21]; /* Must be all one's */
  1948. } WRITE_NV_VAR;
  1949. /* Structure for MB Command RUN_BIU_DIAG (04) */
  1950. /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
  1951. typedef struct {
  1952. uint32_t rsvd1;
  1953. union {
  1954. struct {
  1955. struct ulp_bde xmit_bde;
  1956. struct ulp_bde rcv_bde;
  1957. } s1;
  1958. struct {
  1959. struct ulp_bde64 xmit_bde64;
  1960. struct ulp_bde64 rcv_bde64;
  1961. } s2;
  1962. } un;
  1963. } BIU_DIAG_VAR;
  1964. /* Structure for MB command READ_EVENT_LOG (0x38) */
  1965. struct READ_EVENT_LOG_VAR {
  1966. uint32_t word1;
  1967. #define lpfc_event_log_SHIFT 29
  1968. #define lpfc_event_log_MASK 0x00000001
  1969. #define lpfc_event_log_WORD word1
  1970. #define USE_MAILBOX_RESPONSE 1
  1971. uint32_t offset;
  1972. struct ulp_bde64 rcv_bde64;
  1973. };
  1974. /* Structure for MB Command INIT_LINK (05) */
  1975. typedef struct {
  1976. #ifdef __BIG_ENDIAN_BITFIELD
  1977. uint32_t rsvd1:24;
  1978. uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
  1979. #else /* __LITTLE_ENDIAN_BITFIELD */
  1980. uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
  1981. uint32_t rsvd1:24;
  1982. #endif
  1983. #ifdef __BIG_ENDIAN_BITFIELD
  1984. uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
  1985. uint8_t rsvd2;
  1986. uint16_t link_flags;
  1987. #else /* __LITTLE_ENDIAN_BITFIELD */
  1988. uint16_t link_flags;
  1989. uint8_t rsvd2;
  1990. uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
  1991. #endif
  1992. #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
  1993. #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
  1994. #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
  1995. #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
  1996. #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
  1997. #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
  1998. #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
  1999. #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
  2000. #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
  2001. #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
  2002. uint32_t link_speed;
  2003. #define LINK_SPEED_AUTO 0x0 /* Auto selection */
  2004. #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
  2005. #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
  2006. #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
  2007. #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
  2008. #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
  2009. #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
  2010. #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
  2011. #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
  2012. #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
  2013. #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
  2014. } INIT_LINK_VAR;
  2015. /* Structure for MB Command DOWN_LINK (06) */
  2016. typedef struct {
  2017. uint32_t rsvd1;
  2018. } DOWN_LINK_VAR;
  2019. /* Structure for MB Command CONFIG_LINK (07) */
  2020. typedef struct {
  2021. #ifdef __BIG_ENDIAN_BITFIELD
  2022. uint32_t cr:1;
  2023. uint32_t ci:1;
  2024. uint32_t cr_delay:6;
  2025. uint32_t cr_count:8;
  2026. uint32_t rsvd1:8;
  2027. uint32_t MaxBBC:8;
  2028. #else /* __LITTLE_ENDIAN_BITFIELD */
  2029. uint32_t MaxBBC:8;
  2030. uint32_t rsvd1:8;
  2031. uint32_t cr_count:8;
  2032. uint32_t cr_delay:6;
  2033. uint32_t ci:1;
  2034. uint32_t cr:1;
  2035. #endif
  2036. uint32_t myId;
  2037. uint32_t rsvd2;
  2038. uint32_t edtov;
  2039. uint32_t arbtov;
  2040. uint32_t ratov;
  2041. uint32_t rttov;
  2042. uint32_t altov;
  2043. uint32_t crtov;
  2044. #ifdef __BIG_ENDIAN_BITFIELD
  2045. uint32_t rsvd4:19;
  2046. uint32_t cscn:1;
  2047. uint32_t bbscn:4;
  2048. uint32_t rsvd3:8;
  2049. #else /* __LITTLE_ENDIAN_BITFIELD */
  2050. uint32_t rsvd3:8;
  2051. uint32_t bbscn:4;
  2052. uint32_t cscn:1;
  2053. uint32_t rsvd4:19;
  2054. #endif
  2055. #ifdef __BIG_ENDIAN_BITFIELD
  2056. uint32_t rrq_enable:1;
  2057. uint32_t rrq_immed:1;
  2058. uint32_t rsvd5:29;
  2059. uint32_t ack0_enable:1;
  2060. #else /* __LITTLE_ENDIAN_BITFIELD */
  2061. uint32_t ack0_enable:1;
  2062. uint32_t rsvd5:29;
  2063. uint32_t rrq_immed:1;
  2064. uint32_t rrq_enable:1;
  2065. #endif
  2066. } CONFIG_LINK;
  2067. /* Structure for MB Command PART_SLIM (08)
  2068. * will be removed since SLI1 is no longer supported!
  2069. */
  2070. typedef struct {
  2071. #ifdef __BIG_ENDIAN_BITFIELD
  2072. uint16_t offCiocb;
  2073. uint16_t numCiocb;
  2074. uint16_t offRiocb;
  2075. uint16_t numRiocb;
  2076. #else /* __LITTLE_ENDIAN_BITFIELD */
  2077. uint16_t numCiocb;
  2078. uint16_t offCiocb;
  2079. uint16_t numRiocb;
  2080. uint16_t offRiocb;
  2081. #endif
  2082. } RING_DEF;
  2083. typedef struct {
  2084. #ifdef __BIG_ENDIAN_BITFIELD
  2085. uint32_t unused1:24;
  2086. uint32_t numRing:8;
  2087. #else /* __LITTLE_ENDIAN_BITFIELD */
  2088. uint32_t numRing:8;
  2089. uint32_t unused1:24;
  2090. #endif
  2091. RING_DEF ringdef[4];
  2092. uint32_t hbainit;
  2093. } PART_SLIM_VAR;
  2094. /* Structure for MB Command CONFIG_RING (09) */
  2095. typedef struct {
  2096. #ifdef __BIG_ENDIAN_BITFIELD
  2097. uint32_t unused2:6;
  2098. uint32_t recvSeq:1;
  2099. uint32_t recvNotify:1;
  2100. uint32_t numMask:8;
  2101. uint32_t profile:8;
  2102. uint32_t unused1:4;
  2103. uint32_t ring:4;
  2104. #else /* __LITTLE_ENDIAN_BITFIELD */
  2105. uint32_t ring:4;
  2106. uint32_t unused1:4;
  2107. uint32_t profile:8;
  2108. uint32_t numMask:8;
  2109. uint32_t recvNotify:1;
  2110. uint32_t recvSeq:1;
  2111. uint32_t unused2:6;
  2112. #endif
  2113. #ifdef __BIG_ENDIAN_BITFIELD
  2114. uint16_t maxRespXchg;
  2115. uint16_t maxOrigXchg;
  2116. #else /* __LITTLE_ENDIAN_BITFIELD */
  2117. uint16_t maxOrigXchg;
  2118. uint16_t maxRespXchg;
  2119. #endif
  2120. RR_REG rrRegs[6];
  2121. } CONFIG_RING_VAR;
  2122. /* Structure for MB Command RESET_RING (10) */
  2123. typedef struct {
  2124. uint32_t ring_no;
  2125. } RESET_RING_VAR;
  2126. /* Structure for MB Command READ_CONFIG (11) */
  2127. typedef struct {
  2128. #ifdef __BIG_ENDIAN_BITFIELD
  2129. uint32_t cr:1;
  2130. uint32_t ci:1;
  2131. uint32_t cr_delay:6;
  2132. uint32_t cr_count:8;
  2133. uint32_t InitBBC:8;
  2134. uint32_t MaxBBC:8;
  2135. #else /* __LITTLE_ENDIAN_BITFIELD */
  2136. uint32_t MaxBBC:8;
  2137. uint32_t InitBBC:8;
  2138. uint32_t cr_count:8;
  2139. uint32_t cr_delay:6;
  2140. uint32_t ci:1;
  2141. uint32_t cr:1;
  2142. #endif
  2143. #ifdef __BIG_ENDIAN_BITFIELD
  2144. uint32_t topology:8;
  2145. uint32_t myDid:24;
  2146. #else /* __LITTLE_ENDIAN_BITFIELD */
  2147. uint32_t myDid:24;
  2148. uint32_t topology:8;
  2149. #endif
  2150. /* Defines for topology (defined previously) */
  2151. #ifdef __BIG_ENDIAN_BITFIELD
  2152. uint32_t AR:1;
  2153. uint32_t IR:1;
  2154. uint32_t rsvd1:29;
  2155. uint32_t ack0:1;
  2156. #else /* __LITTLE_ENDIAN_BITFIELD */
  2157. uint32_t ack0:1;
  2158. uint32_t rsvd1:29;
  2159. uint32_t IR:1;
  2160. uint32_t AR:1;
  2161. #endif
  2162. uint32_t edtov;
  2163. uint32_t arbtov;
  2164. uint32_t ratov;
  2165. uint32_t rttov;
  2166. uint32_t altov;
  2167. uint32_t lmt;
  2168. #define LMT_RESERVED 0x000 /* Not used */
  2169. #define LMT_1Gb 0x004
  2170. #define LMT_2Gb 0x008
  2171. #define LMT_4Gb 0x040
  2172. #define LMT_8Gb 0x080
  2173. #define LMT_10Gb 0x100
  2174. #define LMT_16Gb 0x200
  2175. #define LMT_32Gb 0x400
  2176. #define LMT_64Gb 0x800
  2177. #define LMT_128Gb 0x1000
  2178. #define LMT_256Gb 0x2000
  2179. uint32_t rsvd2;
  2180. uint32_t rsvd3;
  2181. uint32_t max_xri;
  2182. uint32_t max_iocb;
  2183. uint32_t max_rpi;
  2184. uint32_t avail_xri;
  2185. uint32_t avail_iocb;
  2186. uint32_t avail_rpi;
  2187. uint32_t max_vpi;
  2188. uint32_t rsvd4;
  2189. uint32_t rsvd5;
  2190. uint32_t avail_vpi;
  2191. } READ_CONFIG_VAR;
  2192. /* Structure for MB Command READ_RCONFIG (12) */
  2193. typedef struct {
  2194. #ifdef __BIG_ENDIAN_BITFIELD
  2195. uint32_t rsvd2:7;
  2196. uint32_t recvNotify:1;
  2197. uint32_t numMask:8;
  2198. uint32_t profile:8;
  2199. uint32_t rsvd1:4;
  2200. uint32_t ring:4;
  2201. #else /* __LITTLE_ENDIAN_BITFIELD */
  2202. uint32_t ring:4;
  2203. uint32_t rsvd1:4;
  2204. uint32_t profile:8;
  2205. uint32_t numMask:8;
  2206. uint32_t recvNotify:1;
  2207. uint32_t rsvd2:7;
  2208. #endif
  2209. #ifdef __BIG_ENDIAN_BITFIELD
  2210. uint16_t maxResp;
  2211. uint16_t maxOrig;
  2212. #else /* __LITTLE_ENDIAN_BITFIELD */
  2213. uint16_t maxOrig;
  2214. uint16_t maxResp;
  2215. #endif
  2216. RR_REG rrRegs[6];
  2217. #ifdef __BIG_ENDIAN_BITFIELD
  2218. uint16_t cmdRingOffset;
  2219. uint16_t cmdEntryCnt;
  2220. uint16_t rspRingOffset;
  2221. uint16_t rspEntryCnt;
  2222. uint16_t nextCmdOffset;
  2223. uint16_t rsvd3;
  2224. uint16_t nextRspOffset;
  2225. uint16_t rsvd4;
  2226. #else /* __LITTLE_ENDIAN_BITFIELD */
  2227. uint16_t cmdEntryCnt;
  2228. uint16_t cmdRingOffset;
  2229. uint16_t rspEntryCnt;
  2230. uint16_t rspRingOffset;
  2231. uint16_t rsvd3;
  2232. uint16_t nextCmdOffset;
  2233. uint16_t rsvd4;
  2234. uint16_t nextRspOffset;
  2235. #endif
  2236. } READ_RCONF_VAR;
  2237. /* Structure for MB Command READ_SPARM (13) */
  2238. /* Structure for MB Command READ_SPARM64 (0x8D) */
  2239. typedef struct {
  2240. uint32_t rsvd1;
  2241. uint32_t rsvd2;
  2242. union {
  2243. struct ulp_bde sp; /* This BDE points to struct serv_parm
  2244. structure */
  2245. struct ulp_bde64 sp64;
  2246. } un;
  2247. #ifdef __BIG_ENDIAN_BITFIELD
  2248. uint16_t rsvd3;
  2249. uint16_t vpi;
  2250. #else /* __LITTLE_ENDIAN_BITFIELD */
  2251. uint16_t vpi;
  2252. uint16_t rsvd3;
  2253. #endif
  2254. } READ_SPARM_VAR;
  2255. /* Structure for MB Command READ_STATUS (14) */
  2256. typedef struct {
  2257. #ifdef __BIG_ENDIAN_BITFIELD
  2258. uint32_t rsvd1:31;
  2259. uint32_t clrCounters:1;
  2260. uint16_t activeXriCnt;
  2261. uint16_t activeRpiCnt;
  2262. #else /* __LITTLE_ENDIAN_BITFIELD */
  2263. uint32_t clrCounters:1;
  2264. uint32_t rsvd1:31;
  2265. uint16_t activeRpiCnt;
  2266. uint16_t activeXriCnt;
  2267. #endif
  2268. uint32_t xmitByteCnt;
  2269. uint32_t rcvByteCnt;
  2270. uint32_t xmitFrameCnt;
  2271. uint32_t rcvFrameCnt;
  2272. uint32_t xmitSeqCnt;
  2273. uint32_t rcvSeqCnt;
  2274. uint32_t totalOrigExchanges;
  2275. uint32_t totalRespExchanges;
  2276. uint32_t rcvPbsyCnt;
  2277. uint32_t rcvFbsyCnt;
  2278. } READ_STATUS_VAR;
  2279. /* Structure for MB Command READ_RPI (15) */
  2280. /* Structure for MB Command READ_RPI64 (0x8F) */
  2281. typedef struct {
  2282. #ifdef __BIG_ENDIAN_BITFIELD
  2283. uint16_t nextRpi;
  2284. uint16_t reqRpi;
  2285. uint32_t rsvd2:8;
  2286. uint32_t DID:24;
  2287. #else /* __LITTLE_ENDIAN_BITFIELD */
  2288. uint16_t reqRpi;
  2289. uint16_t nextRpi;
  2290. uint32_t DID:24;
  2291. uint32_t rsvd2:8;
  2292. #endif
  2293. union {
  2294. struct ulp_bde sp;
  2295. struct ulp_bde64 sp64;
  2296. } un;
  2297. } READ_RPI_VAR;
  2298. /* Structure for MB Command READ_XRI (16) */
  2299. typedef struct {
  2300. #ifdef __BIG_ENDIAN_BITFIELD
  2301. uint16_t nextXri;
  2302. uint16_t reqXri;
  2303. uint16_t rsvd1;
  2304. uint16_t rpi;
  2305. uint32_t rsvd2:8;
  2306. uint32_t DID:24;
  2307. uint32_t rsvd3:8;
  2308. uint32_t SID:24;
  2309. uint32_t rsvd4;
  2310. uint8_t seqId;
  2311. uint8_t rsvd5;
  2312. uint16_t seqCount;
  2313. uint16_t oxId;
  2314. uint16_t rxId;
  2315. uint32_t rsvd6:30;
  2316. uint32_t si:1;
  2317. uint32_t exchOrig:1;
  2318. #else /* __LITTLE_ENDIAN_BITFIELD */
  2319. uint16_t reqXri;
  2320. uint16_t nextXri;
  2321. uint16_t rpi;
  2322. uint16_t rsvd1;
  2323. uint32_t DID:24;
  2324. uint32_t rsvd2:8;
  2325. uint32_t SID:24;
  2326. uint32_t rsvd3:8;
  2327. uint32_t rsvd4;
  2328. uint16_t seqCount;
  2329. uint8_t rsvd5;
  2330. uint8_t seqId;
  2331. uint16_t rxId;
  2332. uint16_t oxId;
  2333. uint32_t exchOrig:1;
  2334. uint32_t si:1;
  2335. uint32_t rsvd6:30;
  2336. #endif
  2337. } READ_XRI_VAR;
  2338. /* Structure for MB Command READ_REV (17) */
  2339. typedef struct {
  2340. #ifdef __BIG_ENDIAN_BITFIELD
  2341. uint32_t cv:1;
  2342. uint32_t rr:1;
  2343. uint32_t rsvd2:2;
  2344. uint32_t v3req:1;
  2345. uint32_t v3rsp:1;
  2346. uint32_t rsvd1:25;
  2347. uint32_t rv:1;
  2348. #else /* __LITTLE_ENDIAN_BITFIELD */
  2349. uint32_t rv:1;
  2350. uint32_t rsvd1:25;
  2351. uint32_t v3rsp:1;
  2352. uint32_t v3req:1;
  2353. uint32_t rsvd2:2;
  2354. uint32_t rr:1;
  2355. uint32_t cv:1;
  2356. #endif
  2357. uint32_t biuRev;
  2358. uint32_t smRev;
  2359. union {
  2360. uint32_t smFwRev;
  2361. struct {
  2362. #ifdef __BIG_ENDIAN_BITFIELD
  2363. uint8_t ProgType;
  2364. uint8_t ProgId;
  2365. uint16_t ProgVer:4;
  2366. uint16_t ProgRev:4;
  2367. uint16_t ProgFixLvl:2;
  2368. uint16_t ProgDistType:2;
  2369. uint16_t DistCnt:4;
  2370. #else /* __LITTLE_ENDIAN_BITFIELD */
  2371. uint16_t DistCnt:4;
  2372. uint16_t ProgDistType:2;
  2373. uint16_t ProgFixLvl:2;
  2374. uint16_t ProgRev:4;
  2375. uint16_t ProgVer:4;
  2376. uint8_t ProgId;
  2377. uint8_t ProgType;
  2378. #endif
  2379. } b;
  2380. } un;
  2381. uint32_t endecRev;
  2382. #ifdef __BIG_ENDIAN_BITFIELD
  2383. uint8_t feaLevelHigh;
  2384. uint8_t feaLevelLow;
  2385. uint8_t fcphHigh;
  2386. uint8_t fcphLow;
  2387. #else /* __LITTLE_ENDIAN_BITFIELD */
  2388. uint8_t fcphLow;
  2389. uint8_t fcphHigh;
  2390. uint8_t feaLevelLow;
  2391. uint8_t feaLevelHigh;
  2392. #endif
  2393. uint32_t postKernRev;
  2394. uint32_t opFwRev;
  2395. uint8_t opFwName[16];
  2396. uint32_t sli1FwRev;
  2397. uint8_t sli1FwName[16];
  2398. uint32_t sli2FwRev;
  2399. uint8_t sli2FwName[16];
  2400. uint32_t sli3Feat;
  2401. uint32_t RandomData[6];
  2402. } READ_REV_VAR;
  2403. /* Structure for MB Command READ_LINK_STAT (18) */
  2404. typedef struct {
  2405. uint32_t word0;
  2406. #define lpfc_read_link_stat_rec_SHIFT 0
  2407. #define lpfc_read_link_stat_rec_MASK 0x1
  2408. #define lpfc_read_link_stat_rec_WORD word0
  2409. #define lpfc_read_link_stat_gec_SHIFT 1
  2410. #define lpfc_read_link_stat_gec_MASK 0x1
  2411. #define lpfc_read_link_stat_gec_WORD word0
  2412. #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
  2413. #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
  2414. #define lpfc_read_link_stat_w02oftow23of_WORD word0
  2415. #define lpfc_read_link_stat_rsvd_SHIFT 24
  2416. #define lpfc_read_link_stat_rsvd_MASK 0x1F
  2417. #define lpfc_read_link_stat_rsvd_WORD word0
  2418. #define lpfc_read_link_stat_gec2_SHIFT 29
  2419. #define lpfc_read_link_stat_gec2_MASK 0x1
  2420. #define lpfc_read_link_stat_gec2_WORD word0
  2421. #define lpfc_read_link_stat_clrc_SHIFT 30
  2422. #define lpfc_read_link_stat_clrc_MASK 0x1
  2423. #define lpfc_read_link_stat_clrc_WORD word0
  2424. #define lpfc_read_link_stat_clof_SHIFT 31
  2425. #define lpfc_read_link_stat_clof_MASK 0x1
  2426. #define lpfc_read_link_stat_clof_WORD word0
  2427. uint32_t linkFailureCnt;
  2428. uint32_t lossSyncCnt;
  2429. uint32_t lossSignalCnt;
  2430. uint32_t primSeqErrCnt;
  2431. uint32_t invalidXmitWord;
  2432. uint32_t crcCnt;
  2433. uint32_t primSeqTimeout;
  2434. uint32_t elasticOverrun;
  2435. uint32_t arbTimeout;
  2436. uint32_t advRecBufCredit;
  2437. uint32_t curRecBufCredit;
  2438. uint32_t advTransBufCredit;
  2439. uint32_t curTransBufCredit;
  2440. uint32_t recEofCount;
  2441. uint32_t recEofdtiCount;
  2442. uint32_t recEofniCount;
  2443. uint32_t recSofcount;
  2444. uint32_t rsvd1;
  2445. uint32_t rsvd2;
  2446. uint32_t recDrpXriCount;
  2447. uint32_t fecCorrBlkCount;
  2448. uint32_t fecUncorrBlkCount;
  2449. } READ_LNK_VAR;
  2450. /* Structure for MB Command REG_LOGIN (19) */
  2451. /* Structure for MB Command REG_LOGIN64 (0x93) */
  2452. typedef struct {
  2453. #ifdef __BIG_ENDIAN_BITFIELD
  2454. uint16_t rsvd1;
  2455. uint16_t rpi;
  2456. uint32_t rsvd2:8;
  2457. uint32_t did:24;
  2458. #else /* __LITTLE_ENDIAN_BITFIELD */
  2459. uint16_t rpi;
  2460. uint16_t rsvd1;
  2461. uint32_t did:24;
  2462. uint32_t rsvd2:8;
  2463. #endif
  2464. union {
  2465. struct ulp_bde sp;
  2466. struct ulp_bde64 sp64;
  2467. } un;
  2468. #ifdef __BIG_ENDIAN_BITFIELD
  2469. uint16_t rsvd6;
  2470. uint16_t vpi;
  2471. #else /* __LITTLE_ENDIAN_BITFIELD */
  2472. uint16_t vpi;
  2473. uint16_t rsvd6;
  2474. #endif
  2475. } REG_LOGIN_VAR;
  2476. /* Word 30 contents for REG_LOGIN */
  2477. typedef union {
  2478. struct {
  2479. #ifdef __BIG_ENDIAN_BITFIELD
  2480. uint16_t rsvd1:12;
  2481. uint16_t wd30_class:4;
  2482. uint16_t xri;
  2483. #else /* __LITTLE_ENDIAN_BITFIELD */
  2484. uint16_t xri;
  2485. uint16_t wd30_class:4;
  2486. uint16_t rsvd1:12;
  2487. #endif
  2488. } f;
  2489. uint32_t word;
  2490. } REG_WD30;
  2491. /* Structure for MB Command UNREG_LOGIN (20) */
  2492. typedef struct {
  2493. #ifdef __BIG_ENDIAN_BITFIELD
  2494. uint16_t rsvd1;
  2495. uint16_t rpi;
  2496. uint32_t rsvd2;
  2497. uint32_t rsvd3;
  2498. uint32_t rsvd4;
  2499. uint32_t rsvd5;
  2500. uint16_t rsvd6;
  2501. uint16_t vpi;
  2502. #else /* __LITTLE_ENDIAN_BITFIELD */
  2503. uint16_t rpi;
  2504. uint16_t rsvd1;
  2505. uint32_t rsvd2;
  2506. uint32_t rsvd3;
  2507. uint32_t rsvd4;
  2508. uint32_t rsvd5;
  2509. uint16_t vpi;
  2510. uint16_t rsvd6;
  2511. #endif
  2512. } UNREG_LOGIN_VAR;
  2513. /* Structure for MB Command REG_VPI (0x96) */
  2514. typedef struct {
  2515. #ifdef __BIG_ENDIAN_BITFIELD
  2516. uint32_t rsvd1;
  2517. uint32_t rsvd2:7;
  2518. uint32_t upd:1;
  2519. uint32_t sid:24;
  2520. uint32_t wwn[2];
  2521. uint32_t rsvd5;
  2522. uint16_t vfi;
  2523. uint16_t vpi;
  2524. #else /* __LITTLE_ENDIAN */
  2525. uint32_t rsvd1;
  2526. uint32_t sid:24;
  2527. uint32_t upd:1;
  2528. uint32_t rsvd2:7;
  2529. uint32_t wwn[2];
  2530. uint32_t rsvd5;
  2531. uint16_t vpi;
  2532. uint16_t vfi;
  2533. #endif
  2534. } REG_VPI_VAR;
  2535. /* Structure for MB Command UNREG_VPI (0x97) */
  2536. typedef struct {
  2537. uint32_t rsvd1;
  2538. #ifdef __BIG_ENDIAN_BITFIELD
  2539. uint16_t rsvd2;
  2540. uint16_t sli4_vpi;
  2541. #else /* __LITTLE_ENDIAN */
  2542. uint16_t sli4_vpi;
  2543. uint16_t rsvd2;
  2544. #endif
  2545. uint32_t rsvd3;
  2546. uint32_t rsvd4;
  2547. uint32_t rsvd5;
  2548. #ifdef __BIG_ENDIAN_BITFIELD
  2549. uint16_t rsvd6;
  2550. uint16_t vpi;
  2551. #else /* __LITTLE_ENDIAN */
  2552. uint16_t vpi;
  2553. uint16_t rsvd6;
  2554. #endif
  2555. } UNREG_VPI_VAR;
  2556. /* Structure for MB Command UNREG_D_ID (0x23) */
  2557. typedef struct {
  2558. uint32_t did;
  2559. uint32_t rsvd2;
  2560. uint32_t rsvd3;
  2561. uint32_t rsvd4;
  2562. uint32_t rsvd5;
  2563. #ifdef __BIG_ENDIAN_BITFIELD
  2564. uint16_t rsvd6;
  2565. uint16_t vpi;
  2566. #else
  2567. uint16_t vpi;
  2568. uint16_t rsvd6;
  2569. #endif
  2570. } UNREG_D_ID_VAR;
  2571. /* Structure for MB Command READ_TOPOLOGY (0x95) */
  2572. struct lpfc_mbx_read_top {
  2573. uint32_t eventTag; /* Event tag */
  2574. uint32_t word2;
  2575. #define lpfc_mbx_read_top_fa_SHIFT 12
  2576. #define lpfc_mbx_read_top_fa_MASK 0x00000001
  2577. #define lpfc_mbx_read_top_fa_WORD word2
  2578. #define lpfc_mbx_read_top_mm_SHIFT 11
  2579. #define lpfc_mbx_read_top_mm_MASK 0x00000001
  2580. #define lpfc_mbx_read_top_mm_WORD word2
  2581. #define lpfc_mbx_read_top_pb_SHIFT 9
  2582. #define lpfc_mbx_read_top_pb_MASK 0X00000001
  2583. #define lpfc_mbx_read_top_pb_WORD word2
  2584. #define lpfc_mbx_read_top_il_SHIFT 8
  2585. #define lpfc_mbx_read_top_il_MASK 0x00000001
  2586. #define lpfc_mbx_read_top_il_WORD word2
  2587. #define lpfc_mbx_read_top_att_type_SHIFT 0
  2588. #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
  2589. #define lpfc_mbx_read_top_att_type_WORD word2
  2590. #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
  2591. #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
  2592. #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
  2593. #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
  2594. uint32_t word3;
  2595. #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
  2596. #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
  2597. #define lpfc_mbx_read_top_alpa_granted_WORD word3
  2598. #define lpfc_mbx_read_top_lip_alps_SHIFT 16
  2599. #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
  2600. #define lpfc_mbx_read_top_lip_alps_WORD word3
  2601. #define lpfc_mbx_read_top_lip_type_SHIFT 8
  2602. #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
  2603. #define lpfc_mbx_read_top_lip_type_WORD word3
  2604. #define lpfc_mbx_read_top_topology_SHIFT 0
  2605. #define lpfc_mbx_read_top_topology_MASK 0x000000FF
  2606. #define lpfc_mbx_read_top_topology_WORD word3
  2607. #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
  2608. #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
  2609. #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
  2610. /* store the LILP AL_PA position map into */
  2611. struct ulp_bde64 lilpBde64;
  2612. #define LPFC_ALPA_MAP_SIZE 128
  2613. uint32_t word7;
  2614. #define lpfc_mbx_read_top_ld_lu_SHIFT 31
  2615. #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
  2616. #define lpfc_mbx_read_top_ld_lu_WORD word7
  2617. #define lpfc_mbx_read_top_ld_tf_SHIFT 30
  2618. #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
  2619. #define lpfc_mbx_read_top_ld_tf_WORD word7
  2620. #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
  2621. #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
  2622. #define lpfc_mbx_read_top_ld_link_spd_WORD word7
  2623. #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
  2624. #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
  2625. #define lpfc_mbx_read_top_ld_nl_port_WORD word7
  2626. #define lpfc_mbx_read_top_ld_tx_SHIFT 2
  2627. #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
  2628. #define lpfc_mbx_read_top_ld_tx_WORD word7
  2629. #define lpfc_mbx_read_top_ld_rx_SHIFT 0
  2630. #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
  2631. #define lpfc_mbx_read_top_ld_rx_WORD word7
  2632. uint32_t word8;
  2633. #define lpfc_mbx_read_top_lu_SHIFT 31
  2634. #define lpfc_mbx_read_top_lu_MASK 0x00000001
  2635. #define lpfc_mbx_read_top_lu_WORD word8
  2636. #define lpfc_mbx_read_top_tf_SHIFT 30
  2637. #define lpfc_mbx_read_top_tf_MASK 0x00000001
  2638. #define lpfc_mbx_read_top_tf_WORD word8
  2639. #define lpfc_mbx_read_top_link_spd_SHIFT 8
  2640. #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
  2641. #define lpfc_mbx_read_top_link_spd_WORD word8
  2642. #define lpfc_mbx_read_top_nl_port_SHIFT 4
  2643. #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
  2644. #define lpfc_mbx_read_top_nl_port_WORD word8
  2645. #define lpfc_mbx_read_top_tx_SHIFT 2
  2646. #define lpfc_mbx_read_top_tx_MASK 0x00000003
  2647. #define lpfc_mbx_read_top_tx_WORD word8
  2648. #define lpfc_mbx_read_top_rx_SHIFT 0
  2649. #define lpfc_mbx_read_top_rx_MASK 0x00000003
  2650. #define lpfc_mbx_read_top_rx_WORD word8
  2651. #define LPFC_LINK_SPEED_UNKNOWN 0x0
  2652. #define LPFC_LINK_SPEED_1GHZ 0x04
  2653. #define LPFC_LINK_SPEED_2GHZ 0x08
  2654. #define LPFC_LINK_SPEED_4GHZ 0x10
  2655. #define LPFC_LINK_SPEED_8GHZ 0x20
  2656. #define LPFC_LINK_SPEED_10GHZ 0x40
  2657. #define LPFC_LINK_SPEED_16GHZ 0x80
  2658. #define LPFC_LINK_SPEED_32GHZ 0x90
  2659. #define LPFC_LINK_SPEED_64GHZ 0xA0
  2660. #define LPFC_LINK_SPEED_128GHZ 0xB0
  2661. #define LPFC_LINK_SPEED_256GHZ 0xC0
  2662. };
  2663. /* Structure for MB Command CLEAR_LA (22) */
  2664. typedef struct {
  2665. uint32_t eventTag; /* Event tag */
  2666. uint32_t rsvd1;
  2667. } CLEAR_LA_VAR;
  2668. /* Structure for MB Command DUMP */
  2669. typedef struct {
  2670. #ifdef __BIG_ENDIAN_BITFIELD
  2671. uint32_t rsvd:25;
  2672. uint32_t ra:1;
  2673. uint32_t co:1;
  2674. uint32_t cv:1;
  2675. uint32_t type:4;
  2676. uint32_t entry_index:16;
  2677. uint32_t region_id:16;
  2678. #else /* __LITTLE_ENDIAN_BITFIELD */
  2679. uint32_t type:4;
  2680. uint32_t cv:1;
  2681. uint32_t co:1;
  2682. uint32_t ra:1;
  2683. uint32_t rsvd:25;
  2684. uint32_t region_id:16;
  2685. uint32_t entry_index:16;
  2686. #endif
  2687. uint32_t sli4_length;
  2688. uint32_t word_cnt;
  2689. uint32_t resp_offset;
  2690. } DUMP_VAR;
  2691. #define DMP_MEM_REG 0x1
  2692. #define DMP_NV_PARAMS 0x2
  2693. #define DMP_LMSD 0x3 /* Link Module Serial Data */
  2694. #define DMP_WELL_KNOWN 0x4
  2695. #define DMP_REGION_VPD 0xe
  2696. #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
  2697. #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
  2698. #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
  2699. #define DMP_REGION_VPORT 0x16 /* VPort info region */
  2700. #define DMP_VPORT_REGION_SIZE 0x200
  2701. #define DMP_MBOX_OFFSET_WORD 0x5
  2702. #define DMP_REGION_23 0x17 /* fcoe param and port state region */
  2703. #define DMP_RGN23_SIZE 0x400
  2704. #define WAKE_UP_PARMS_REGION_ID 4
  2705. #define WAKE_UP_PARMS_WORD_SIZE 15
  2706. struct vport_rec {
  2707. uint8_t wwpn[8];
  2708. uint8_t wwnn[8];
  2709. };
  2710. #define VPORT_INFO_SIG 0x32324752
  2711. #define VPORT_INFO_REV_MASK 0xff
  2712. #define VPORT_INFO_REV 0x1
  2713. #define MAX_STATIC_VPORT_COUNT 16
  2714. struct static_vport_info {
  2715. uint32_t signature;
  2716. uint32_t rev;
  2717. struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
  2718. uint32_t resvd[66];
  2719. };
  2720. /* Option rom version structure */
  2721. struct prog_id {
  2722. #ifdef __BIG_ENDIAN_BITFIELD
  2723. uint8_t type;
  2724. uint8_t id;
  2725. uint32_t ver:4; /* Major Version */
  2726. uint32_t rev:4; /* Revision */
  2727. uint32_t lev:2; /* Level */
  2728. uint32_t dist:2; /* Dist Type */
  2729. uint32_t num:4; /* number after dist type */
  2730. #else /* __LITTLE_ENDIAN_BITFIELD */
  2731. uint32_t num:4; /* number after dist type */
  2732. uint32_t dist:2; /* Dist Type */
  2733. uint32_t lev:2; /* Level */
  2734. uint32_t rev:4; /* Revision */
  2735. uint32_t ver:4; /* Major Version */
  2736. uint8_t id;
  2737. uint8_t type;
  2738. #endif
  2739. };
  2740. /* Structure for MB Command UPDATE_CFG (0x1B) */
  2741. struct update_cfg_var {
  2742. #ifdef __BIG_ENDIAN_BITFIELD
  2743. uint32_t rsvd2:16;
  2744. uint32_t type:8;
  2745. uint32_t rsvd:1;
  2746. uint32_t ra:1;
  2747. uint32_t co:1;
  2748. uint32_t cv:1;
  2749. uint32_t req:4;
  2750. uint32_t entry_length:16;
  2751. uint32_t region_id:16;
  2752. #else /* __LITTLE_ENDIAN_BITFIELD */
  2753. uint32_t req:4;
  2754. uint32_t cv:1;
  2755. uint32_t co:1;
  2756. uint32_t ra:1;
  2757. uint32_t rsvd:1;
  2758. uint32_t type:8;
  2759. uint32_t rsvd2:16;
  2760. uint32_t region_id:16;
  2761. uint32_t entry_length:16;
  2762. #endif
  2763. uint32_t resp_info;
  2764. uint32_t byte_cnt;
  2765. uint32_t data_offset;
  2766. };
  2767. struct hbq_mask {
  2768. #ifdef __BIG_ENDIAN_BITFIELD
  2769. uint8_t tmatch;
  2770. uint8_t tmask;
  2771. uint8_t rctlmatch;
  2772. uint8_t rctlmask;
  2773. #else /* __LITTLE_ENDIAN */
  2774. uint8_t rctlmask;
  2775. uint8_t rctlmatch;
  2776. uint8_t tmask;
  2777. uint8_t tmatch;
  2778. #endif
  2779. };
  2780. /* Structure for MB Command CONFIG_HBQ (7c) */
  2781. struct config_hbq_var {
  2782. #ifdef __BIG_ENDIAN_BITFIELD
  2783. uint32_t rsvd1 :7;
  2784. uint32_t recvNotify :1; /* Receive Notification */
  2785. uint32_t numMask :8; /* # Mask Entries */
  2786. uint32_t profile :8; /* Selection Profile */
  2787. uint32_t rsvd2 :8;
  2788. #else /* __LITTLE_ENDIAN */
  2789. uint32_t rsvd2 :8;
  2790. uint32_t profile :8; /* Selection Profile */
  2791. uint32_t numMask :8; /* # Mask Entries */
  2792. uint32_t recvNotify :1; /* Receive Notification */
  2793. uint32_t rsvd1 :7;
  2794. #endif
  2795. #ifdef __BIG_ENDIAN_BITFIELD
  2796. uint32_t hbqId :16;
  2797. uint32_t rsvd3 :12;
  2798. uint32_t ringMask :4;
  2799. #else /* __LITTLE_ENDIAN */
  2800. uint32_t ringMask :4;
  2801. uint32_t rsvd3 :12;
  2802. uint32_t hbqId :16;
  2803. #endif
  2804. #ifdef __BIG_ENDIAN_BITFIELD
  2805. uint32_t entry_count :16;
  2806. uint32_t rsvd4 :8;
  2807. uint32_t headerLen :8;
  2808. #else /* __LITTLE_ENDIAN */
  2809. uint32_t headerLen :8;
  2810. uint32_t rsvd4 :8;
  2811. uint32_t entry_count :16;
  2812. #endif
  2813. uint32_t hbqaddrLow;
  2814. uint32_t hbqaddrHigh;
  2815. #ifdef __BIG_ENDIAN_BITFIELD
  2816. uint32_t rsvd5 :31;
  2817. uint32_t logEntry :1;
  2818. #else /* __LITTLE_ENDIAN */
  2819. uint32_t logEntry :1;
  2820. uint32_t rsvd5 :31;
  2821. #endif
  2822. uint32_t rsvd6; /* w7 */
  2823. uint32_t rsvd7; /* w8 */
  2824. uint32_t rsvd8; /* w9 */
  2825. struct hbq_mask hbqMasks[6];
  2826. union {
  2827. uint32_t allprofiles[12];
  2828. struct {
  2829. #ifdef __BIG_ENDIAN_BITFIELD
  2830. uint32_t seqlenoff :16;
  2831. uint32_t maxlen :16;
  2832. #else /* __LITTLE_ENDIAN */
  2833. uint32_t maxlen :16;
  2834. uint32_t seqlenoff :16;
  2835. #endif
  2836. #ifdef __BIG_ENDIAN_BITFIELD
  2837. uint32_t rsvd1 :28;
  2838. uint32_t seqlenbcnt :4;
  2839. #else /* __LITTLE_ENDIAN */
  2840. uint32_t seqlenbcnt :4;
  2841. uint32_t rsvd1 :28;
  2842. #endif
  2843. uint32_t rsvd[10];
  2844. } profile2;
  2845. struct {
  2846. #ifdef __BIG_ENDIAN_BITFIELD
  2847. uint32_t seqlenoff :16;
  2848. uint32_t maxlen :16;
  2849. #else /* __LITTLE_ENDIAN */
  2850. uint32_t maxlen :16;
  2851. uint32_t seqlenoff :16;
  2852. #endif
  2853. #ifdef __BIG_ENDIAN_BITFIELD
  2854. uint32_t cmdcodeoff :28;
  2855. uint32_t rsvd1 :12;
  2856. uint32_t seqlenbcnt :4;
  2857. #else /* __LITTLE_ENDIAN */
  2858. uint32_t seqlenbcnt :4;
  2859. uint32_t rsvd1 :12;
  2860. uint32_t cmdcodeoff :28;
  2861. #endif
  2862. uint32_t cmdmatch[8];
  2863. uint32_t rsvd[2];
  2864. } profile3;
  2865. struct {
  2866. #ifdef __BIG_ENDIAN_BITFIELD
  2867. uint32_t seqlenoff :16;
  2868. uint32_t maxlen :16;
  2869. #else /* __LITTLE_ENDIAN */
  2870. uint32_t maxlen :16;
  2871. uint32_t seqlenoff :16;
  2872. #endif
  2873. #ifdef __BIG_ENDIAN_BITFIELD
  2874. uint32_t cmdcodeoff :28;
  2875. uint32_t rsvd1 :12;
  2876. uint32_t seqlenbcnt :4;
  2877. #else /* __LITTLE_ENDIAN */
  2878. uint32_t seqlenbcnt :4;
  2879. uint32_t rsvd1 :12;
  2880. uint32_t cmdcodeoff :28;
  2881. #endif
  2882. uint32_t cmdmatch[8];
  2883. uint32_t rsvd[2];
  2884. } profile5;
  2885. } profiles;
  2886. };
  2887. /* Structure for MB Command CONFIG_PORT (0x88) */
  2888. typedef struct {
  2889. #ifdef __BIG_ENDIAN_BITFIELD
  2890. uint32_t cBE : 1;
  2891. uint32_t cET : 1;
  2892. uint32_t cHpcb : 1;
  2893. uint32_t cMA : 1;
  2894. uint32_t sli_mode : 4;
  2895. uint32_t pcbLen : 24; /* bit 23:0 of memory based port
  2896. * config block */
  2897. #else /* __LITTLE_ENDIAN */
  2898. uint32_t pcbLen : 24; /* bit 23:0 of memory based port
  2899. * config block */
  2900. uint32_t sli_mode : 4;
  2901. uint32_t cMA : 1;
  2902. uint32_t cHpcb : 1;
  2903. uint32_t cET : 1;
  2904. uint32_t cBE : 1;
  2905. #endif
  2906. uint32_t pcbLow; /* bit 31:0 of memory based port config block */
  2907. uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
  2908. uint32_t hbainit[5];
  2909. #ifdef __BIG_ENDIAN_BITFIELD
  2910. uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
  2911. uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
  2912. #else /* __LITTLE_ENDIAN */
  2913. uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
  2914. uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
  2915. #endif
  2916. #ifdef __BIG_ENDIAN_BITFIELD
  2917. uint32_t rsvd1 : 19; /* Reserved */
  2918. uint32_t cdss : 1; /* Configure Data Security SLI */
  2919. uint32_t casabt : 1; /* Configure async abts status notice */
  2920. uint32_t rsvd2 : 2; /* Reserved */
  2921. uint32_t cbg : 1; /* Configure BlockGuard */
  2922. uint32_t cmv : 1; /* Configure Max VPIs */
  2923. uint32_t ccrp : 1; /* Config Command Ring Polling */
  2924. uint32_t csah : 1; /* Configure Synchronous Abort Handling */
  2925. uint32_t chbs : 1; /* Cofigure Host Backing store */
  2926. uint32_t cinb : 1; /* Enable Interrupt Notification Block */
  2927. uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
  2928. uint32_t cmx : 1; /* Configure Max XRIs */
  2929. uint32_t cmr : 1; /* Configure Max RPIs */
  2930. #else /* __LITTLE_ENDIAN */
  2931. uint32_t cmr : 1; /* Configure Max RPIs */
  2932. uint32_t cmx : 1; /* Configure Max XRIs */
  2933. uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
  2934. uint32_t cinb : 1; /* Enable Interrupt Notification Block */
  2935. uint32_t chbs : 1; /* Cofigure Host Backing store */
  2936. uint32_t csah : 1; /* Configure Synchronous Abort Handling */
  2937. uint32_t ccrp : 1; /* Config Command Ring Polling */
  2938. uint32_t cmv : 1; /* Configure Max VPIs */
  2939. uint32_t cbg : 1; /* Configure BlockGuard */
  2940. uint32_t rsvd2 : 2; /* Reserved */
  2941. uint32_t casabt : 1; /* Configure async abts status notice */
  2942. uint32_t cdss : 1; /* Configure Data Security SLI */
  2943. uint32_t rsvd1 : 19; /* Reserved */
  2944. #endif
  2945. #ifdef __BIG_ENDIAN_BITFIELD
  2946. uint32_t rsvd3 : 19; /* Reserved */
  2947. uint32_t gdss : 1; /* Configure Data Security SLI */
  2948. uint32_t gasabt : 1; /* Grant async abts status notice */
  2949. uint32_t rsvd4 : 2; /* Reserved */
  2950. uint32_t gbg : 1; /* Grant BlockGuard */
  2951. uint32_t gmv : 1; /* Grant Max VPIs */
  2952. uint32_t gcrp : 1; /* Grant Command Ring Polling */
  2953. uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
  2954. uint32_t ghbs : 1; /* Grant Host Backing Store */
  2955. uint32_t ginb : 1; /* Grant Interrupt Notification Block */
  2956. uint32_t gerbm : 1; /* Grant ERBM Request */
  2957. uint32_t gmx : 1; /* Grant Max XRIs */
  2958. uint32_t gmr : 1; /* Grant Max RPIs */
  2959. #else /* __LITTLE_ENDIAN */
  2960. uint32_t gmr : 1; /* Grant Max RPIs */
  2961. uint32_t gmx : 1; /* Grant Max XRIs */
  2962. uint32_t gerbm : 1; /* Grant ERBM Request */
  2963. uint32_t ginb : 1; /* Grant Interrupt Notification Block */
  2964. uint32_t ghbs : 1; /* Grant Host Backing Store */
  2965. uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
  2966. uint32_t gcrp : 1; /* Grant Command Ring Polling */
  2967. uint32_t gmv : 1; /* Grant Max VPIs */
  2968. uint32_t gbg : 1; /* Grant BlockGuard */
  2969. uint32_t rsvd4 : 2; /* Reserved */
  2970. uint32_t gasabt : 1; /* Grant async abts status notice */
  2971. uint32_t gdss : 1; /* Configure Data Security SLI */
  2972. uint32_t rsvd3 : 19; /* Reserved */
  2973. #endif
  2974. #ifdef __BIG_ENDIAN_BITFIELD
  2975. uint32_t max_rpi : 16; /* Max RPIs Port should configure */
  2976. uint32_t max_xri : 16; /* Max XRIs Port should configure */
  2977. #else /* __LITTLE_ENDIAN */
  2978. uint32_t max_xri : 16; /* Max XRIs Port should configure */
  2979. uint32_t max_rpi : 16; /* Max RPIs Port should configure */
  2980. #endif
  2981. #ifdef __BIG_ENDIAN_BITFIELD
  2982. uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
  2983. uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
  2984. #else /* __LITTLE_ENDIAN */
  2985. uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
  2986. uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
  2987. #endif
  2988. uint32_t rsvd6; /* Reserved */
  2989. #ifdef __BIG_ENDIAN_BITFIELD
  2990. uint32_t fips_rev : 3; /* FIPS Spec Revision */
  2991. uint32_t fips_level : 4; /* FIPS Level */
  2992. uint32_t sec_err : 9; /* security crypto error */
  2993. uint32_t max_vpi : 16; /* Max number of virt N-Ports */
  2994. #else /* __LITTLE_ENDIAN */
  2995. uint32_t max_vpi : 16; /* Max number of virt N-Ports */
  2996. uint32_t sec_err : 9; /* security crypto error */
  2997. uint32_t fips_level : 4; /* FIPS Level */
  2998. uint32_t fips_rev : 3; /* FIPS Spec Revision */
  2999. #endif
  3000. } CONFIG_PORT_VAR;
  3001. /* Structure for MB Command CONFIG_MSI (0x30) */
  3002. struct config_msi_var {
  3003. #ifdef __BIG_ENDIAN_BITFIELD
  3004. uint32_t dfltMsgNum:8; /* Default message number */
  3005. uint32_t rsvd1:11; /* Reserved */
  3006. uint32_t NID:5; /* Number of secondary attention IDs */
  3007. uint32_t rsvd2:5; /* Reserved */
  3008. uint32_t dfltPresent:1; /* Default message number present */
  3009. uint32_t addFlag:1; /* Add association flag */
  3010. uint32_t reportFlag:1; /* Report association flag */
  3011. #else /* __LITTLE_ENDIAN_BITFIELD */
  3012. uint32_t reportFlag:1; /* Report association flag */
  3013. uint32_t addFlag:1; /* Add association flag */
  3014. uint32_t dfltPresent:1; /* Default message number present */
  3015. uint32_t rsvd2:5; /* Reserved */
  3016. uint32_t NID:5; /* Number of secondary attention IDs */
  3017. uint32_t rsvd1:11; /* Reserved */
  3018. uint32_t dfltMsgNum:8; /* Default message number */
  3019. #endif
  3020. uint32_t attentionConditions[2];
  3021. uint8_t attentionId[16];
  3022. uint8_t messageNumberByHA[64];
  3023. uint8_t messageNumberByID[16];
  3024. uint32_t autoClearHA[2];
  3025. #ifdef __BIG_ENDIAN_BITFIELD
  3026. uint32_t rsvd3:16;
  3027. uint32_t autoClearID:16;
  3028. #else /* __LITTLE_ENDIAN_BITFIELD */
  3029. uint32_t autoClearID:16;
  3030. uint32_t rsvd3:16;
  3031. #endif
  3032. uint32_t rsvd4;
  3033. };
  3034. /* SLI-2 Port Control Block */
  3035. /* SLIM POINTER */
  3036. #define SLIMOFF 0x30 /* WORD */
  3037. typedef struct _SLI2_RDSC {
  3038. uint32_t cmdEntries;
  3039. uint32_t cmdAddrLow;
  3040. uint32_t cmdAddrHigh;
  3041. uint32_t rspEntries;
  3042. uint32_t rspAddrLow;
  3043. uint32_t rspAddrHigh;
  3044. } SLI2_RDSC;
  3045. typedef struct _PCB {
  3046. #ifdef __BIG_ENDIAN_BITFIELD
  3047. uint32_t type:8;
  3048. #define TYPE_NATIVE_SLI2 0x01
  3049. uint32_t feature:8;
  3050. #define FEATURE_INITIAL_SLI2 0x01
  3051. uint32_t rsvd:12;
  3052. uint32_t maxRing:4;
  3053. #else /* __LITTLE_ENDIAN_BITFIELD */
  3054. uint32_t maxRing:4;
  3055. uint32_t rsvd:12;
  3056. uint32_t feature:8;
  3057. #define FEATURE_INITIAL_SLI2 0x01
  3058. uint32_t type:8;
  3059. #define TYPE_NATIVE_SLI2 0x01
  3060. #endif
  3061. uint32_t mailBoxSize;
  3062. uint32_t mbAddrLow;
  3063. uint32_t mbAddrHigh;
  3064. uint32_t hgpAddrLow;
  3065. uint32_t hgpAddrHigh;
  3066. uint32_t pgpAddrLow;
  3067. uint32_t pgpAddrHigh;
  3068. SLI2_RDSC rdsc[MAX_SLI3_RINGS];
  3069. } PCB_t;
  3070. /* NEW_FEATURE */
  3071. typedef struct {
  3072. #ifdef __BIG_ENDIAN_BITFIELD
  3073. uint32_t rsvd0:27;
  3074. uint32_t discardFarp:1;
  3075. uint32_t IPEnable:1;
  3076. uint32_t nodeName:1;
  3077. uint32_t portName:1;
  3078. uint32_t filterEnable:1;
  3079. #else /* __LITTLE_ENDIAN_BITFIELD */
  3080. uint32_t filterEnable:1;
  3081. uint32_t portName:1;
  3082. uint32_t nodeName:1;
  3083. uint32_t IPEnable:1;
  3084. uint32_t discardFarp:1;
  3085. uint32_t rsvd:27;
  3086. #endif
  3087. uint8_t portname[8]; /* Used to be struct lpfc_name */
  3088. uint8_t nodename[8];
  3089. uint32_t rsvd1;
  3090. uint32_t rsvd2;
  3091. uint32_t rsvd3;
  3092. uint32_t IPAddress;
  3093. } CONFIG_FARP_VAR;
  3094. /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
  3095. typedef struct {
  3096. #ifdef __BIG_ENDIAN_BITFIELD
  3097. uint32_t rsvd:30;
  3098. uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
  3099. #else /* __LITTLE_ENDIAN */
  3100. uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
  3101. uint32_t rsvd:30;
  3102. #endif
  3103. } ASYNCEVT_ENABLE_VAR;
  3104. /* Union of all Mailbox Command types */
  3105. #define MAILBOX_CMD_WSIZE 32
  3106. #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
  3107. /* ext_wsize times 4 bytes should not be greater than max xmit size */
  3108. #define MAILBOX_EXT_WSIZE 512
  3109. #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
  3110. #define MAILBOX_HBA_EXT_OFFSET 0x100
  3111. /* max mbox xmit size is a page size for sysfs IO operations */
  3112. #define MAILBOX_SYSFS_MAX 4096
  3113. typedef union {
  3114. uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
  3115. * feature/max ring number
  3116. */
  3117. LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
  3118. READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
  3119. WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
  3120. BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
  3121. INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
  3122. DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
  3123. CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
  3124. PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
  3125. CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
  3126. RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
  3127. READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
  3128. READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
  3129. READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
  3130. READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
  3131. READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
  3132. READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
  3133. READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
  3134. READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
  3135. REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
  3136. UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
  3137. CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
  3138. DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
  3139. UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
  3140. CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
  3141. * NEW_FEATURE
  3142. */
  3143. struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
  3144. struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
  3145. CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
  3146. struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
  3147. REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
  3148. UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
  3149. ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
  3150. struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
  3151. * (READ_EVENT_LOG)
  3152. */
  3153. struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
  3154. } MAILVARIANTS;
  3155. /*
  3156. * SLI-2 specific structures
  3157. */
  3158. struct lpfc_hgp {
  3159. __le32 cmdPutInx;
  3160. __le32 rspGetInx;
  3161. };
  3162. struct lpfc_pgp {
  3163. __le32 cmdGetInx;
  3164. __le32 rspPutInx;
  3165. };
  3166. struct sli2_desc {
  3167. uint32_t unused1[16];
  3168. struct lpfc_hgp host[MAX_SLI3_RINGS];
  3169. struct lpfc_pgp port[MAX_SLI3_RINGS];
  3170. };
  3171. struct sli3_desc {
  3172. struct lpfc_hgp host[MAX_SLI3_RINGS];
  3173. uint32_t reserved[8];
  3174. uint32_t hbq_put[16];
  3175. };
  3176. struct sli3_pgp {
  3177. struct lpfc_pgp port[MAX_SLI3_RINGS];
  3178. uint32_t hbq_get[16];
  3179. };
  3180. union sli_var {
  3181. struct sli2_desc s2;
  3182. struct sli3_desc s3;
  3183. struct sli3_pgp s3_pgp;
  3184. };
  3185. typedef struct {
  3186. #ifdef __BIG_ENDIAN_BITFIELD
  3187. uint16_t mbxStatus;
  3188. uint8_t mbxCommand;
  3189. uint8_t mbxReserved:6;
  3190. uint8_t mbxHc:1;
  3191. uint8_t mbxOwner:1; /* Low order bit first word */
  3192. #else /* __LITTLE_ENDIAN_BITFIELD */
  3193. uint8_t mbxOwner:1; /* Low order bit first word */
  3194. uint8_t mbxHc:1;
  3195. uint8_t mbxReserved:6;
  3196. uint8_t mbxCommand;
  3197. uint16_t mbxStatus;
  3198. #endif
  3199. MAILVARIANTS un;
  3200. union sli_var us;
  3201. } MAILBOX_t;
  3202. /*
  3203. * Begin Structure Definitions for IOCB Commands
  3204. */
  3205. typedef struct {
  3206. #ifdef __BIG_ENDIAN_BITFIELD
  3207. uint8_t statAction;
  3208. uint8_t statRsn;
  3209. uint8_t statBaExp;
  3210. uint8_t statLocalError;
  3211. #else /* __LITTLE_ENDIAN_BITFIELD */
  3212. uint8_t statLocalError;
  3213. uint8_t statBaExp;
  3214. uint8_t statRsn;
  3215. uint8_t statAction;
  3216. #endif
  3217. /* statRsn P/F_RJT reason codes */
  3218. #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
  3219. #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
  3220. #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
  3221. #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
  3222. #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
  3223. #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
  3224. #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
  3225. #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
  3226. #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
  3227. #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
  3228. #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
  3229. #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
  3230. #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
  3231. #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
  3232. #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
  3233. #define RJT_BAD_PARM 0x10 /* Param. field invalid */
  3234. #define RJT_XCHG_ERR 0x11 /* Exchange error */
  3235. #define RJT_PROT_ERR 0x12 /* Protocol error */
  3236. #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
  3237. #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
  3238. #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
  3239. #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
  3240. #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
  3241. #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
  3242. #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
  3243. #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
  3244. #define IOERR_SUCCESS 0x00 /* statLocalError */
  3245. #define IOERR_MISSING_CONTINUE 0x01
  3246. #define IOERR_SEQUENCE_TIMEOUT 0x02
  3247. #define IOERR_INTERNAL_ERROR 0x03
  3248. #define IOERR_INVALID_RPI 0x04
  3249. #define IOERR_NO_XRI 0x05
  3250. #define IOERR_ILLEGAL_COMMAND 0x06
  3251. #define IOERR_XCHG_DROPPED 0x07
  3252. #define IOERR_ILLEGAL_FIELD 0x08
  3253. #define IOERR_BAD_CONTINUE 0x09
  3254. #define IOERR_TOO_MANY_BUFFERS 0x0A
  3255. #define IOERR_RCV_BUFFER_WAITING 0x0B
  3256. #define IOERR_NO_CONNECTION 0x0C
  3257. #define IOERR_TX_DMA_FAILED 0x0D
  3258. #define IOERR_RX_DMA_FAILED 0x0E
  3259. #define IOERR_ILLEGAL_FRAME 0x0F
  3260. #define IOERR_EXTRA_DATA 0x10
  3261. #define IOERR_NO_RESOURCES 0x11
  3262. #define IOERR_RESERVED 0x12
  3263. #define IOERR_ILLEGAL_LENGTH 0x13
  3264. #define IOERR_UNSUPPORTED_FEATURE 0x14
  3265. #define IOERR_ABORT_IN_PROGRESS 0x15
  3266. #define IOERR_ABORT_REQUESTED 0x16
  3267. #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
  3268. #define IOERR_LOOP_OPEN_FAILURE 0x18
  3269. #define IOERR_RING_RESET 0x19
  3270. #define IOERR_LINK_DOWN 0x1A
  3271. #define IOERR_CORRUPTED_DATA 0x1B
  3272. #define IOERR_CORRUPTED_RPI 0x1C
  3273. #define IOERR_OUT_OF_ORDER_DATA 0x1D
  3274. #define IOERR_OUT_OF_ORDER_ACK 0x1E
  3275. #define IOERR_DUP_FRAME 0x1F
  3276. #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
  3277. #define IOERR_BAD_HOST_ADDRESS 0x21
  3278. #define IOERR_RCV_HDRBUF_WAITING 0x22
  3279. #define IOERR_MISSING_HDR_BUFFER 0x23
  3280. #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
  3281. #define IOERR_ABORTMULT_REQUESTED 0x25
  3282. #define IOERR_BUFFER_SHORTAGE 0x28
  3283. #define IOERR_DEFAULT 0x29
  3284. #define IOERR_CNT 0x2A
  3285. #define IOERR_SLER_FAILURE 0x46
  3286. #define IOERR_SLER_CMD_RCV_FAILURE 0x47
  3287. #define IOERR_SLER_REC_RJT_ERR 0x48
  3288. #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
  3289. #define IOERR_SLER_SRR_RJT_ERR 0x4A
  3290. #define IOERR_SLER_RRQ_RJT_ERR 0x4C
  3291. #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
  3292. #define IOERR_SLER_ABTS_ERR 0x4E
  3293. #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
  3294. #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
  3295. #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
  3296. #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
  3297. #define IOERR_DRVR_MASK 0x100
  3298. #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
  3299. #define IOERR_SLI_BRESET 0x102
  3300. #define IOERR_SLI_ABORTED 0x103
  3301. #define IOERR_PARAM_MASK 0x1ff
  3302. } PARM_ERR;
  3303. typedef union {
  3304. struct {
  3305. #ifdef __BIG_ENDIAN_BITFIELD
  3306. uint8_t Rctl; /* R_CTL field */
  3307. uint8_t Type; /* TYPE field */
  3308. uint8_t Dfctl; /* DF_CTL field */
  3309. uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
  3310. #else /* __LITTLE_ENDIAN_BITFIELD */
  3311. uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
  3312. uint8_t Dfctl; /* DF_CTL field */
  3313. uint8_t Type; /* TYPE field */
  3314. uint8_t Rctl; /* R_CTL field */
  3315. #endif
  3316. #define BC 0x02 /* Broadcast Received - Fctl */
  3317. #define SI 0x04 /* Sequence Initiative */
  3318. #define LA 0x08 /* Ignore Link Attention state */
  3319. #define LS 0x80 /* Last Sequence */
  3320. } hcsw;
  3321. uint32_t reserved;
  3322. } WORD5;
  3323. /* IOCB Command template for a generic response */
  3324. typedef struct {
  3325. uint32_t reserved[4];
  3326. PARM_ERR perr;
  3327. } GENERIC_RSP;
  3328. /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
  3329. typedef struct {
  3330. struct ulp_bde xrsqbde[2];
  3331. uint32_t xrsqRo; /* Starting Relative Offset */
  3332. WORD5 w5; /* Header control/status word */
  3333. } XR_SEQ_FIELDS;
  3334. /* IOCB Command template for ELS_REQUEST */
  3335. typedef struct {
  3336. struct ulp_bde elsReq;
  3337. struct ulp_bde elsRsp;
  3338. #ifdef __BIG_ENDIAN_BITFIELD
  3339. uint32_t word4Rsvd:7;
  3340. uint32_t fl:1;
  3341. uint32_t myID:24;
  3342. uint32_t word5Rsvd:8;
  3343. uint32_t remoteID:24;
  3344. #else /* __LITTLE_ENDIAN_BITFIELD */
  3345. uint32_t myID:24;
  3346. uint32_t fl:1;
  3347. uint32_t word4Rsvd:7;
  3348. uint32_t remoteID:24;
  3349. uint32_t word5Rsvd:8;
  3350. #endif
  3351. } ELS_REQUEST;
  3352. /* IOCB Command template for RCV_ELS_REQ */
  3353. typedef struct {
  3354. struct ulp_bde elsReq[2];
  3355. uint32_t parmRo;
  3356. #ifdef __BIG_ENDIAN_BITFIELD
  3357. uint32_t word5Rsvd:8;
  3358. uint32_t remoteID:24;
  3359. #else /* __LITTLE_ENDIAN_BITFIELD */
  3360. uint32_t remoteID:24;
  3361. uint32_t word5Rsvd:8;
  3362. #endif
  3363. } RCV_ELS_REQ;
  3364. /* IOCB Command template for ABORT / CLOSE_XRI */
  3365. typedef struct {
  3366. uint32_t rsvd[3];
  3367. uint32_t abortType;
  3368. #define ABORT_TYPE_ABTX 0x00000000
  3369. #define ABORT_TYPE_ABTS 0x00000001
  3370. uint32_t parm;
  3371. #ifdef __BIG_ENDIAN_BITFIELD
  3372. uint16_t abortContextTag; /* ulpContext from command to abort/close */
  3373. uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
  3374. #else /* __LITTLE_ENDIAN_BITFIELD */
  3375. uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
  3376. uint16_t abortContextTag; /* ulpContext from command to abort/close */
  3377. #endif
  3378. } AC_XRI;
  3379. /* IOCB Command template for ABORT_MXRI64 */
  3380. typedef struct {
  3381. uint32_t rsvd[3];
  3382. uint32_t abortType;
  3383. uint32_t parm;
  3384. uint32_t iotag32;
  3385. } A_MXRI64;
  3386. /* IOCB Command template for GET_RPI */
  3387. typedef struct {
  3388. uint32_t rsvd[4];
  3389. uint32_t parmRo;
  3390. #ifdef __BIG_ENDIAN_BITFIELD
  3391. uint32_t word5Rsvd:8;
  3392. uint32_t remoteID:24;
  3393. #else /* __LITTLE_ENDIAN_BITFIELD */
  3394. uint32_t remoteID:24;
  3395. uint32_t word5Rsvd:8;
  3396. #endif
  3397. } GET_RPI;
  3398. /* IOCB Command template for all FCP Initiator commands */
  3399. typedef struct {
  3400. struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
  3401. struct ulp_bde fcpi_rsp; /* Rcv buffer */
  3402. uint32_t fcpi_parm;
  3403. uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
  3404. } FCPI_FIELDS;
  3405. /* IOCB Command template for all FCP Target commands */
  3406. typedef struct {
  3407. struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
  3408. uint32_t fcpt_Offset;
  3409. uint32_t fcpt_Length; /* transfer ready for IWRITE */
  3410. } FCPT_FIELDS;
  3411. /* SLI-2 IOCB structure definitions */
  3412. /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
  3413. typedef struct {
  3414. ULP_BDL bdl;
  3415. uint32_t xrsqRo; /* Starting Relative Offset */
  3416. WORD5 w5; /* Header control/status word */
  3417. } XMT_SEQ_FIELDS64;
  3418. /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
  3419. #define xmit_els_remoteID xrsqRo
  3420. /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
  3421. typedef struct {
  3422. struct ulp_bde64 rcvBde;
  3423. uint32_t rsvd1;
  3424. uint32_t xrsqRo; /* Starting Relative Offset */
  3425. WORD5 w5; /* Header control/status word */
  3426. } RCV_SEQ_FIELDS64;
  3427. /* IOCB Command template for ELS_REQUEST64 */
  3428. typedef struct {
  3429. ULP_BDL bdl;
  3430. #ifdef __BIG_ENDIAN_BITFIELD
  3431. uint32_t word4Rsvd:7;
  3432. uint32_t fl:1;
  3433. uint32_t myID:24;
  3434. uint32_t word5Rsvd:8;
  3435. uint32_t remoteID:24;
  3436. #else /* __LITTLE_ENDIAN_BITFIELD */
  3437. uint32_t myID:24;
  3438. uint32_t fl:1;
  3439. uint32_t word4Rsvd:7;
  3440. uint32_t remoteID:24;
  3441. uint32_t word5Rsvd:8;
  3442. #endif
  3443. } ELS_REQUEST64;
  3444. /* IOCB Command template for GEN_REQUEST64 */
  3445. typedef struct {
  3446. ULP_BDL bdl;
  3447. uint32_t xrsqRo; /* Starting Relative Offset */
  3448. WORD5 w5; /* Header control/status word */
  3449. } GEN_REQUEST64;
  3450. /* IOCB Command template for RCV_ELS_REQ64 */
  3451. typedef struct {
  3452. struct ulp_bde64 elsReq;
  3453. uint32_t rcvd1;
  3454. uint32_t parmRo;
  3455. #ifdef __BIG_ENDIAN_BITFIELD
  3456. uint32_t word5Rsvd:8;
  3457. uint32_t remoteID:24;
  3458. #else /* __LITTLE_ENDIAN_BITFIELD */
  3459. uint32_t remoteID:24;
  3460. uint32_t word5Rsvd:8;
  3461. #endif
  3462. } RCV_ELS_REQ64;
  3463. /* IOCB Command template for RCV_SEQ64 */
  3464. struct rcv_seq64 {
  3465. struct ulp_bde64 elsReq;
  3466. uint32_t hbq_1;
  3467. uint32_t parmRo;
  3468. #ifdef __BIG_ENDIAN_BITFIELD
  3469. uint32_t rctl:8;
  3470. uint32_t type:8;
  3471. uint32_t dfctl:8;
  3472. uint32_t ls:1;
  3473. uint32_t fs:1;
  3474. uint32_t rsvd2:3;
  3475. uint32_t si:1;
  3476. uint32_t bc:1;
  3477. uint32_t rsvd3:1;
  3478. #else /* __LITTLE_ENDIAN_BITFIELD */
  3479. uint32_t rsvd3:1;
  3480. uint32_t bc:1;
  3481. uint32_t si:1;
  3482. uint32_t rsvd2:3;
  3483. uint32_t fs:1;
  3484. uint32_t ls:1;
  3485. uint32_t dfctl:8;
  3486. uint32_t type:8;
  3487. uint32_t rctl:8;
  3488. #endif
  3489. };
  3490. /* IOCB Command template for all 64 bit FCP Initiator commands */
  3491. typedef struct {
  3492. ULP_BDL bdl;
  3493. uint32_t fcpi_parm;
  3494. uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
  3495. } FCPI_FIELDS64;
  3496. /* IOCB Command template for all 64 bit FCP Target commands */
  3497. typedef struct {
  3498. ULP_BDL bdl;
  3499. uint32_t fcpt_Offset;
  3500. uint32_t fcpt_Length; /* transfer ready for IWRITE */
  3501. } FCPT_FIELDS64;
  3502. /* IOCB Command template for Async Status iocb commands */
  3503. typedef struct {
  3504. uint32_t rsvd[4];
  3505. uint32_t param;
  3506. #ifdef __BIG_ENDIAN_BITFIELD
  3507. uint16_t evt_code; /* High order bits word 5 */
  3508. uint16_t sub_ctxt_tag; /* Low order bits word 5 */
  3509. #else /* __LITTLE_ENDIAN_BITFIELD */
  3510. uint16_t sub_ctxt_tag; /* High order bits word 5 */
  3511. uint16_t evt_code; /* Low order bits word 5 */
  3512. #endif
  3513. } ASYNCSTAT_FIELDS;
  3514. #define ASYNC_TEMP_WARN 0x100
  3515. #define ASYNC_TEMP_SAFE 0x101
  3516. #define ASYNC_STATUS_CN 0x102
  3517. /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
  3518. or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
  3519. struct rcv_sli3 {
  3520. #ifdef __BIG_ENDIAN_BITFIELD
  3521. uint16_t ox_id;
  3522. uint16_t seq_cnt;
  3523. uint16_t vpi;
  3524. uint16_t word9Rsvd;
  3525. #else /* __LITTLE_ENDIAN */
  3526. uint16_t seq_cnt;
  3527. uint16_t ox_id;
  3528. uint16_t word9Rsvd;
  3529. uint16_t vpi;
  3530. #endif
  3531. uint32_t word10Rsvd;
  3532. uint32_t acc_len; /* accumulated length */
  3533. struct ulp_bde64 bde2;
  3534. };
  3535. /* Structure used for a single HBQ entry */
  3536. struct lpfc_hbq_entry {
  3537. struct ulp_bde64 bde;
  3538. uint32_t buffer_tag;
  3539. };
  3540. /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
  3541. typedef struct {
  3542. struct lpfc_hbq_entry buff;
  3543. uint32_t rsvd;
  3544. uint32_t rsvd1;
  3545. } QUE_XRI64_CX_FIELDS;
  3546. struct que_xri64cx_ext_fields {
  3547. uint32_t iotag64_low;
  3548. uint32_t iotag64_high;
  3549. uint32_t ebde_count;
  3550. uint32_t rsvd;
  3551. struct lpfc_hbq_entry buff[5];
  3552. };
  3553. struct sli3_bg_fields {
  3554. uint32_t filler[6]; /* word 8-13 in IOCB */
  3555. uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
  3556. /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
  3557. #define BGS_BIDIR_BG_PROF_MASK 0xff000000
  3558. #define BGS_BIDIR_BG_PROF_SHIFT 24
  3559. #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
  3560. #define BGS_BIDIR_ERR_COND_SHIFT 16
  3561. #define BGS_BG_PROFILE_MASK 0x0000ff00
  3562. #define BGS_BG_PROFILE_SHIFT 8
  3563. #define BGS_INVALID_PROF_MASK 0x00000020
  3564. #define BGS_INVALID_PROF_SHIFT 5
  3565. #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
  3566. #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
  3567. #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
  3568. #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
  3569. #define BGS_REFTAG_ERR_MASK 0x00000004
  3570. #define BGS_REFTAG_ERR_SHIFT 2
  3571. #define BGS_APPTAG_ERR_MASK 0x00000002
  3572. #define BGS_APPTAG_ERR_SHIFT 1
  3573. #define BGS_GUARD_ERR_MASK 0x00000001
  3574. #define BGS_GUARD_ERR_SHIFT 0
  3575. uint32_t bgstat; /* word 15 - BlockGuard Status */
  3576. };
  3577. static inline uint32_t
  3578. lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
  3579. {
  3580. return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
  3581. BGS_BIDIR_BG_PROF_SHIFT;
  3582. }
  3583. static inline uint32_t
  3584. lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
  3585. {
  3586. return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
  3587. BGS_BIDIR_ERR_COND_SHIFT;
  3588. }
  3589. static inline uint32_t
  3590. lpfc_bgs_get_bg_prof(uint32_t bgstat)
  3591. {
  3592. return (bgstat & BGS_BG_PROFILE_MASK) >>
  3593. BGS_BG_PROFILE_SHIFT;
  3594. }
  3595. static inline uint32_t
  3596. lpfc_bgs_get_invalid_prof(uint32_t bgstat)
  3597. {
  3598. return (bgstat & BGS_INVALID_PROF_MASK) >>
  3599. BGS_INVALID_PROF_SHIFT;
  3600. }
  3601. static inline uint32_t
  3602. lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
  3603. {
  3604. return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
  3605. BGS_UNINIT_DIF_BLOCK_SHIFT;
  3606. }
  3607. static inline uint32_t
  3608. lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
  3609. {
  3610. return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
  3611. BGS_HI_WATER_MARK_PRESENT_SHIFT;
  3612. }
  3613. static inline uint32_t
  3614. lpfc_bgs_get_reftag_err(uint32_t bgstat)
  3615. {
  3616. return (bgstat & BGS_REFTAG_ERR_MASK) >>
  3617. BGS_REFTAG_ERR_SHIFT;
  3618. }
  3619. static inline uint32_t
  3620. lpfc_bgs_get_apptag_err(uint32_t bgstat)
  3621. {
  3622. return (bgstat & BGS_APPTAG_ERR_MASK) >>
  3623. BGS_APPTAG_ERR_SHIFT;
  3624. }
  3625. static inline uint32_t
  3626. lpfc_bgs_get_guard_err(uint32_t bgstat)
  3627. {
  3628. return (bgstat & BGS_GUARD_ERR_MASK) >>
  3629. BGS_GUARD_ERR_SHIFT;
  3630. }
  3631. #define LPFC_EXT_DATA_BDE_COUNT 3
  3632. struct fcp_irw_ext {
  3633. uint32_t io_tag64_low;
  3634. uint32_t io_tag64_high;
  3635. #ifdef __BIG_ENDIAN_BITFIELD
  3636. uint8_t reserved1;
  3637. uint8_t reserved2;
  3638. uint8_t reserved3;
  3639. uint8_t ebde_count;
  3640. #else /* __LITTLE_ENDIAN */
  3641. uint8_t ebde_count;
  3642. uint8_t reserved3;
  3643. uint8_t reserved2;
  3644. uint8_t reserved1;
  3645. #endif
  3646. uint32_t reserved4;
  3647. struct ulp_bde64 rbde; /* response bde */
  3648. struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
  3649. uint8_t icd[32]; /* immediate command data (32 bytes) */
  3650. };
  3651. typedef struct _IOCB { /* IOCB structure */
  3652. union {
  3653. GENERIC_RSP grsp; /* Generic response */
  3654. XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
  3655. struct ulp_bde cont[3]; /* up to 3 continuation bdes */
  3656. RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
  3657. AC_XRI acxri; /* ABORT / CLOSE_XRI template */
  3658. A_MXRI64 amxri; /* abort multiple xri command overlay */
  3659. GET_RPI getrpi; /* GET_RPI template */
  3660. FCPI_FIELDS fcpi; /* FCP Initiator template */
  3661. FCPT_FIELDS fcpt; /* FCP target template */
  3662. /* SLI-2 structures */
  3663. struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
  3664. * bde_64s */
  3665. ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
  3666. GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
  3667. RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
  3668. XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
  3669. FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
  3670. FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
  3671. ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
  3672. QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
  3673. struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
  3674. struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
  3675. uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
  3676. } un;
  3677. union {
  3678. struct {
  3679. #ifdef __BIG_ENDIAN_BITFIELD
  3680. uint16_t ulpContext; /* High order bits word 6 */
  3681. uint16_t ulpIoTag; /* Low order bits word 6 */
  3682. #else /* __LITTLE_ENDIAN_BITFIELD */
  3683. uint16_t ulpIoTag; /* Low order bits word 6 */
  3684. uint16_t ulpContext; /* High order bits word 6 */
  3685. #endif
  3686. } t1;
  3687. struct {
  3688. #ifdef __BIG_ENDIAN_BITFIELD
  3689. uint16_t ulpContext; /* High order bits word 6 */
  3690. uint16_t ulpIoTag1:2; /* Low order bits word 6 */
  3691. uint16_t ulpIoTag0:14; /* Low order bits word 6 */
  3692. #else /* __LITTLE_ENDIAN_BITFIELD */
  3693. uint16_t ulpIoTag0:14; /* Low order bits word 6 */
  3694. uint16_t ulpIoTag1:2; /* Low order bits word 6 */
  3695. uint16_t ulpContext; /* High order bits word 6 */
  3696. #endif
  3697. } t2;
  3698. } un1;
  3699. #define ulpContext un1.t1.ulpContext
  3700. #define ulpIoTag un1.t1.ulpIoTag
  3701. #define ulpIoTag0 un1.t2.ulpIoTag0
  3702. #ifdef __BIG_ENDIAN_BITFIELD
  3703. uint32_t ulpTimeout:8;
  3704. uint32_t ulpXS:1;
  3705. uint32_t ulpFCP2Rcvy:1;
  3706. uint32_t ulpPU:2;
  3707. uint32_t ulpIr:1;
  3708. uint32_t ulpClass:3;
  3709. uint32_t ulpCommand:8;
  3710. uint32_t ulpStatus:4;
  3711. uint32_t ulpBdeCount:2;
  3712. uint32_t ulpLe:1;
  3713. uint32_t ulpOwner:1; /* Low order bit word 7 */
  3714. #else /* __LITTLE_ENDIAN_BITFIELD */
  3715. uint32_t ulpOwner:1; /* Low order bit word 7 */
  3716. uint32_t ulpLe:1;
  3717. uint32_t ulpBdeCount:2;
  3718. uint32_t ulpStatus:4;
  3719. uint32_t ulpCommand:8;
  3720. uint32_t ulpClass:3;
  3721. uint32_t ulpIr:1;
  3722. uint32_t ulpPU:2;
  3723. uint32_t ulpFCP2Rcvy:1;
  3724. uint32_t ulpXS:1;
  3725. uint32_t ulpTimeout:8;
  3726. #endif
  3727. union {
  3728. struct rcv_sli3 rcvsli3; /* words 8 - 15 */
  3729. /* words 8-31 used for que_xri_cx iocb */
  3730. struct que_xri64cx_ext_fields que_xri64cx_ext_words;
  3731. struct fcp_irw_ext fcp_ext;
  3732. uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
  3733. /* words 8-15 for BlockGuard */
  3734. struct sli3_bg_fields sli3_bg;
  3735. } unsli3;
  3736. #define ulpCt_h ulpXS
  3737. #define ulpCt_l ulpFCP2Rcvy
  3738. #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
  3739. #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
  3740. #define PARM_UNUSED 0 /* PU field (Word 4) not used */
  3741. #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
  3742. #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
  3743. #define PARM_NPIV_DID 3
  3744. #define CLASS1 0 /* Class 1 */
  3745. #define CLASS2 1 /* Class 2 */
  3746. #define CLASS3 2 /* Class 3 */
  3747. #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
  3748. #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
  3749. #define IOSTAT_FCP_RSP_ERROR 0x1
  3750. #define IOSTAT_REMOTE_STOP 0x2
  3751. #define IOSTAT_LOCAL_REJECT 0x3
  3752. #define IOSTAT_NPORT_RJT 0x4
  3753. #define IOSTAT_FABRIC_RJT 0x5
  3754. #define IOSTAT_NPORT_BSY 0x6
  3755. #define IOSTAT_FABRIC_BSY 0x7
  3756. #define IOSTAT_INTERMED_RSP 0x8
  3757. #define IOSTAT_LS_RJT 0x9
  3758. #define IOSTAT_BA_RJT 0xA
  3759. #define IOSTAT_RSVD1 0xB
  3760. #define IOSTAT_RSVD2 0xC
  3761. #define IOSTAT_RSVD3 0xD
  3762. #define IOSTAT_RSVD4 0xE
  3763. #define IOSTAT_NEED_BUFFER 0xF
  3764. #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
  3765. #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
  3766. #define IOSTAT_CNT 0x11
  3767. } IOCB_t;
  3768. #define SLI1_SLIM_SIZE (4 * 1024)
  3769. /* Up to 498 IOCBs will fit into 16k
  3770. * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
  3771. */
  3772. #define SLI2_SLIM_SIZE (64 * 1024)
  3773. /* Maximum IOCBs that will fit in SLI2 slim */
  3774. #define MAX_SLI2_IOCB 498
  3775. #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
  3776. (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
  3777. sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
  3778. /* HBQ entries are 4 words each = 4k */
  3779. #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
  3780. lpfc_sli_hbq_count())
  3781. struct lpfc_sli2_slim {
  3782. MAILBOX_t mbx;
  3783. uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
  3784. PCB_t pcb;
  3785. IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
  3786. };
  3787. /*
  3788. * This function checks PCI device to allow special handling for LC HBAs.
  3789. *
  3790. * Parameters:
  3791. * device : struct pci_dev 's device field
  3792. *
  3793. * return 1 => TRUE
  3794. * 0 => FALSE
  3795. */
  3796. static inline int
  3797. lpfc_is_LC_HBA(unsigned short device)
  3798. {
  3799. if ((device == PCI_DEVICE_ID_TFLY) ||
  3800. (device == PCI_DEVICE_ID_PFLY) ||
  3801. (device == PCI_DEVICE_ID_LP101) ||
  3802. (device == PCI_DEVICE_ID_BMID) ||
  3803. (device == PCI_DEVICE_ID_BSMB) ||
  3804. (device == PCI_DEVICE_ID_ZMID) ||
  3805. (device == PCI_DEVICE_ID_ZSMB) ||
  3806. (device == PCI_DEVICE_ID_SAT_MID) ||
  3807. (device == PCI_DEVICE_ID_SAT_SMB) ||
  3808. (device == PCI_DEVICE_ID_RFLY))
  3809. return 1;
  3810. else
  3811. return 0;
  3812. }
  3813. /*
  3814. * Determine if an IOCB failed because of a link event or firmware reset.
  3815. */
  3816. static inline int
  3817. lpfc_error_lost_link(IOCB_t *iocbp)
  3818. {
  3819. return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
  3820. (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
  3821. iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
  3822. iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
  3823. }
  3824. #define MENLO_TRANSPORT_TYPE 0xfe
  3825. #define MENLO_CONTEXT 0
  3826. #define MENLO_PU 3
  3827. #define MENLO_TIMEOUT 30
  3828. #define SETVAR_MLOMNT 0x103107
  3829. #define SETVAR_MLORST 0x103007
  3830. #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */