gadget.c 134 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Copyright 2008 Openmoko, Inc.
  7. * Copyright 2008 Simtec Electronics
  8. * Ben Dooks <ben@simtec.co.uk>
  9. * http://armlinux.simtec.co.uk/
  10. *
  11. * S3C USB2.0 High-speed / OtG driver
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mutex.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/delay.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/usb/ch9.h>
  26. #include <linux/usb/gadget.h>
  27. #include <linux/usb/phy.h>
  28. #include "core.h"
  29. #include "hw.h"
  30. /* conversion functions */
  31. static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
  32. {
  33. return container_of(req, struct dwc2_hsotg_req, req);
  34. }
  35. static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
  36. {
  37. return container_of(ep, struct dwc2_hsotg_ep, ep);
  38. }
  39. static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
  40. {
  41. return container_of(gadget, struct dwc2_hsotg, gadget);
  42. }
  43. static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
  44. {
  45. dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
  46. }
  47. static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
  48. {
  49. dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
  50. }
  51. static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
  52. u32 ep_index, u32 dir_in)
  53. {
  54. if (dir_in)
  55. return hsotg->eps_in[ep_index];
  56. else
  57. return hsotg->eps_out[ep_index];
  58. }
  59. /* forward declaration of functions */
  60. static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
  61. /**
  62. * using_dma - return the DMA status of the driver.
  63. * @hsotg: The driver state.
  64. *
  65. * Return true if we're using DMA.
  66. *
  67. * Currently, we have the DMA support code worked into everywhere
  68. * that needs it, but the AMBA DMA implementation in the hardware can
  69. * only DMA from 32bit aligned addresses. This means that gadgets such
  70. * as the CDC Ethernet cannot work as they often pass packets which are
  71. * not 32bit aligned.
  72. *
  73. * Unfortunately the choice to use DMA or not is global to the controller
  74. * and seems to be only settable when the controller is being put through
  75. * a core reset. This means we either need to fix the gadgets to take
  76. * account of DMA alignment, or add bounce buffers (yuerk).
  77. *
  78. * g_using_dma is set depending on dts flag.
  79. */
  80. static inline bool using_dma(struct dwc2_hsotg *hsotg)
  81. {
  82. return hsotg->params.g_dma;
  83. }
  84. /*
  85. * using_desc_dma - return the descriptor DMA status of the driver.
  86. * @hsotg: The driver state.
  87. *
  88. * Return true if we're using descriptor DMA.
  89. */
  90. static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
  91. {
  92. return hsotg->params.g_dma_desc;
  93. }
  94. /**
  95. * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
  96. * @hs_ep: The endpoint
  97. *
  98. * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
  99. * If an overrun occurs it will wrap the value and set the frame_overrun flag.
  100. */
  101. static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
  102. {
  103. hs_ep->target_frame += hs_ep->interval;
  104. if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
  105. hs_ep->frame_overrun = true;
  106. hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
  107. } else {
  108. hs_ep->frame_overrun = false;
  109. }
  110. }
  111. /**
  112. * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
  113. * @hsotg: The device state
  114. * @ints: A bitmask of the interrupts to enable
  115. */
  116. static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
  117. {
  118. u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
  119. u32 new_gsintmsk;
  120. new_gsintmsk = gsintmsk | ints;
  121. if (new_gsintmsk != gsintmsk) {
  122. dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
  123. dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
  124. }
  125. }
  126. /**
  127. * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
  128. * @hsotg: The device state
  129. * @ints: A bitmask of the interrupts to enable
  130. */
  131. static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
  132. {
  133. u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
  134. u32 new_gsintmsk;
  135. new_gsintmsk = gsintmsk & ~ints;
  136. if (new_gsintmsk != gsintmsk)
  137. dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
  138. }
  139. /**
  140. * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
  141. * @hsotg: The device state
  142. * @ep: The endpoint index
  143. * @dir_in: True if direction is in.
  144. * @en: The enable value, true to enable
  145. *
  146. * Set or clear the mask for an individual endpoint's interrupt
  147. * request.
  148. */
  149. static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
  150. unsigned int ep, unsigned int dir_in,
  151. unsigned int en)
  152. {
  153. unsigned long flags;
  154. u32 bit = 1 << ep;
  155. u32 daint;
  156. if (!dir_in)
  157. bit <<= 16;
  158. local_irq_save(flags);
  159. daint = dwc2_readl(hsotg, DAINTMSK);
  160. if (en)
  161. daint |= bit;
  162. else
  163. daint &= ~bit;
  164. dwc2_writel(hsotg, daint, DAINTMSK);
  165. local_irq_restore(flags);
  166. }
  167. /**
  168. * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
  169. *
  170. * @hsotg: Programming view of the DWC_otg controller
  171. */
  172. int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
  173. {
  174. if (hsotg->hw_params.en_multiple_tx_fifo)
  175. /* In dedicated FIFO mode we need count of IN EPs */
  176. return hsotg->hw_params.num_dev_in_eps;
  177. else
  178. /* In shared FIFO mode we need count of Periodic IN EPs */
  179. return hsotg->hw_params.num_dev_perio_in_ep;
  180. }
  181. /**
  182. * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
  183. * device mode TX FIFOs
  184. *
  185. * @hsotg: Programming view of the DWC_otg controller
  186. */
  187. int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
  188. {
  189. int addr;
  190. int tx_addr_max;
  191. u32 np_tx_fifo_size;
  192. np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
  193. hsotg->params.g_np_tx_fifo_size);
  194. /* Get Endpoint Info Control block size in DWORDs. */
  195. tx_addr_max = hsotg->hw_params.total_fifo_size;
  196. addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
  197. if (tx_addr_max <= addr)
  198. return 0;
  199. return tx_addr_max - addr;
  200. }
  201. /**
  202. * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
  203. * TX FIFOs
  204. *
  205. * @hsotg: Programming view of the DWC_otg controller
  206. */
  207. int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
  208. {
  209. int tx_fifo_count;
  210. int tx_fifo_depth;
  211. tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
  212. tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
  213. if (!tx_fifo_count)
  214. return tx_fifo_depth;
  215. else
  216. return tx_fifo_depth / tx_fifo_count;
  217. }
  218. /**
  219. * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
  220. * @hsotg: The device instance.
  221. */
  222. static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
  223. {
  224. unsigned int ep;
  225. unsigned int addr;
  226. int timeout;
  227. u32 val;
  228. u32 *txfsz = hsotg->params.g_tx_fifo_size;
  229. /* Reset fifo map if not correctly cleared during previous session */
  230. WARN_ON(hsotg->fifo_map);
  231. hsotg->fifo_map = 0;
  232. /* set RX/NPTX FIFO sizes */
  233. dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
  234. dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
  235. FIFOSIZE_STARTADDR_SHIFT) |
  236. (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
  237. GNPTXFSIZ);
  238. /*
  239. * arange all the rest of the TX FIFOs, as some versions of this
  240. * block have overlapping default addresses. This also ensures
  241. * that if the settings have been changed, then they are set to
  242. * known values.
  243. */
  244. /* start at the end of the GNPTXFSIZ, rounded up */
  245. addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
  246. /*
  247. * Configure fifos sizes from provided configuration and assign
  248. * them to endpoints dynamically according to maxpacket size value of
  249. * given endpoint.
  250. */
  251. for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
  252. if (!txfsz[ep])
  253. continue;
  254. val = addr;
  255. val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
  256. WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
  257. "insufficient fifo memory");
  258. addr += txfsz[ep];
  259. dwc2_writel(hsotg, val, DPTXFSIZN(ep));
  260. val = dwc2_readl(hsotg, DPTXFSIZN(ep));
  261. }
  262. dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
  263. addr << GDFIFOCFG_EPINFOBASE_SHIFT,
  264. GDFIFOCFG);
  265. /*
  266. * according to p428 of the design guide, we need to ensure that
  267. * all fifos are flushed before continuing
  268. */
  269. dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
  270. GRSTCTL_RXFFLSH, GRSTCTL);
  271. /* wait until the fifos are both flushed */
  272. timeout = 100;
  273. while (1) {
  274. val = dwc2_readl(hsotg, GRSTCTL);
  275. if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
  276. break;
  277. if (--timeout == 0) {
  278. dev_err(hsotg->dev,
  279. "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
  280. __func__, val);
  281. break;
  282. }
  283. udelay(1);
  284. }
  285. dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
  286. }
  287. /**
  288. * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
  289. * @ep: USB endpoint to allocate request for.
  290. * @flags: Allocation flags
  291. *
  292. * Allocate a new USB request structure appropriate for the specified endpoint
  293. */
  294. static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
  295. gfp_t flags)
  296. {
  297. struct dwc2_hsotg_req *req;
  298. req = kzalloc(sizeof(*req), flags);
  299. if (!req)
  300. return NULL;
  301. INIT_LIST_HEAD(&req->queue);
  302. return &req->req;
  303. }
  304. /**
  305. * is_ep_periodic - return true if the endpoint is in periodic mode.
  306. * @hs_ep: The endpoint to query.
  307. *
  308. * Returns true if the endpoint is in periodic mode, meaning it is being
  309. * used for an Interrupt or ISO transfer.
  310. */
  311. static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
  312. {
  313. return hs_ep->periodic;
  314. }
  315. /**
  316. * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
  317. * @hsotg: The device state.
  318. * @hs_ep: The endpoint for the request
  319. * @hs_req: The request being processed.
  320. *
  321. * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
  322. * of a request to ensure the buffer is ready for access by the caller.
  323. */
  324. static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
  325. struct dwc2_hsotg_ep *hs_ep,
  326. struct dwc2_hsotg_req *hs_req)
  327. {
  328. struct usb_request *req = &hs_req->req;
  329. usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
  330. }
  331. /*
  332. * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
  333. * for Control endpoint
  334. * @hsotg: The device state.
  335. *
  336. * This function will allocate 4 descriptor chains for EP 0: 2 for
  337. * Setup stage, per one for IN and OUT data/status transactions.
  338. */
  339. static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
  340. {
  341. hsotg->setup_desc[0] =
  342. dmam_alloc_coherent(hsotg->dev,
  343. sizeof(struct dwc2_dma_desc),
  344. &hsotg->setup_desc_dma[0],
  345. GFP_KERNEL);
  346. if (!hsotg->setup_desc[0])
  347. goto fail;
  348. hsotg->setup_desc[1] =
  349. dmam_alloc_coherent(hsotg->dev,
  350. sizeof(struct dwc2_dma_desc),
  351. &hsotg->setup_desc_dma[1],
  352. GFP_KERNEL);
  353. if (!hsotg->setup_desc[1])
  354. goto fail;
  355. hsotg->ctrl_in_desc =
  356. dmam_alloc_coherent(hsotg->dev,
  357. sizeof(struct dwc2_dma_desc),
  358. &hsotg->ctrl_in_desc_dma,
  359. GFP_KERNEL);
  360. if (!hsotg->ctrl_in_desc)
  361. goto fail;
  362. hsotg->ctrl_out_desc =
  363. dmam_alloc_coherent(hsotg->dev,
  364. sizeof(struct dwc2_dma_desc),
  365. &hsotg->ctrl_out_desc_dma,
  366. GFP_KERNEL);
  367. if (!hsotg->ctrl_out_desc)
  368. goto fail;
  369. return 0;
  370. fail:
  371. return -ENOMEM;
  372. }
  373. /**
  374. * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
  375. * @hsotg: The controller state.
  376. * @hs_ep: The endpoint we're going to write for.
  377. * @hs_req: The request to write data for.
  378. *
  379. * This is called when the TxFIFO has some space in it to hold a new
  380. * transmission and we have something to give it. The actual setup of
  381. * the data size is done elsewhere, so all we have to do is to actually
  382. * write the data.
  383. *
  384. * The return value is zero if there is more space (or nothing was done)
  385. * otherwise -ENOSPC is returned if the FIFO space was used up.
  386. *
  387. * This routine is only needed for PIO
  388. */
  389. static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
  390. struct dwc2_hsotg_ep *hs_ep,
  391. struct dwc2_hsotg_req *hs_req)
  392. {
  393. bool periodic = is_ep_periodic(hs_ep);
  394. u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
  395. int buf_pos = hs_req->req.actual;
  396. int to_write = hs_ep->size_loaded;
  397. void *data;
  398. int can_write;
  399. int pkt_round;
  400. int max_transfer;
  401. to_write -= (buf_pos - hs_ep->last_load);
  402. /* if there's nothing to write, get out early */
  403. if (to_write == 0)
  404. return 0;
  405. if (periodic && !hsotg->dedicated_fifos) {
  406. u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
  407. int size_left;
  408. int size_done;
  409. /*
  410. * work out how much data was loaded so we can calculate
  411. * how much data is left in the fifo.
  412. */
  413. size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
  414. /*
  415. * if shared fifo, we cannot write anything until the
  416. * previous data has been completely sent.
  417. */
  418. if (hs_ep->fifo_load != 0) {
  419. dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
  420. return -ENOSPC;
  421. }
  422. dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
  423. __func__, size_left,
  424. hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
  425. /* how much of the data has moved */
  426. size_done = hs_ep->size_loaded - size_left;
  427. /* how much data is left in the fifo */
  428. can_write = hs_ep->fifo_load - size_done;
  429. dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
  430. __func__, can_write);
  431. can_write = hs_ep->fifo_size - can_write;
  432. dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
  433. __func__, can_write);
  434. if (can_write <= 0) {
  435. dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
  436. return -ENOSPC;
  437. }
  438. } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
  439. can_write = dwc2_readl(hsotg,
  440. DTXFSTS(hs_ep->fifo_index));
  441. can_write &= 0xffff;
  442. can_write *= 4;
  443. } else {
  444. if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
  445. dev_dbg(hsotg->dev,
  446. "%s: no queue slots available (0x%08x)\n",
  447. __func__, gnptxsts);
  448. dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
  449. return -ENOSPC;
  450. }
  451. can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
  452. can_write *= 4; /* fifo size is in 32bit quantities. */
  453. }
  454. max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
  455. dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
  456. __func__, gnptxsts, can_write, to_write, max_transfer);
  457. /*
  458. * limit to 512 bytes of data, it seems at least on the non-periodic
  459. * FIFO, requests of >512 cause the endpoint to get stuck with a
  460. * fragment of the end of the transfer in it.
  461. */
  462. if (can_write > 512 && !periodic)
  463. can_write = 512;
  464. /*
  465. * limit the write to one max-packet size worth of data, but allow
  466. * the transfer to return that it did not run out of fifo space
  467. * doing it.
  468. */
  469. if (to_write > max_transfer) {
  470. to_write = max_transfer;
  471. /* it's needed only when we do not use dedicated fifos */
  472. if (!hsotg->dedicated_fifos)
  473. dwc2_hsotg_en_gsint(hsotg,
  474. periodic ? GINTSTS_PTXFEMP :
  475. GINTSTS_NPTXFEMP);
  476. }
  477. /* see if we can write data */
  478. if (to_write > can_write) {
  479. to_write = can_write;
  480. pkt_round = to_write % max_transfer;
  481. /*
  482. * Round the write down to an
  483. * exact number of packets.
  484. *
  485. * Note, we do not currently check to see if we can ever
  486. * write a full packet or not to the FIFO.
  487. */
  488. if (pkt_round)
  489. to_write -= pkt_round;
  490. /*
  491. * enable correct FIFO interrupt to alert us when there
  492. * is more room left.
  493. */
  494. /* it's needed only when we do not use dedicated fifos */
  495. if (!hsotg->dedicated_fifos)
  496. dwc2_hsotg_en_gsint(hsotg,
  497. periodic ? GINTSTS_PTXFEMP :
  498. GINTSTS_NPTXFEMP);
  499. }
  500. dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
  501. to_write, hs_req->req.length, can_write, buf_pos);
  502. if (to_write <= 0)
  503. return -ENOSPC;
  504. hs_req->req.actual = buf_pos + to_write;
  505. hs_ep->total_data += to_write;
  506. if (periodic)
  507. hs_ep->fifo_load += to_write;
  508. to_write = DIV_ROUND_UP(to_write, 4);
  509. data = hs_req->req.buf + buf_pos;
  510. dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
  511. return (to_write >= can_write) ? -ENOSPC : 0;
  512. }
  513. /**
  514. * get_ep_limit - get the maximum data legnth for this endpoint
  515. * @hs_ep: The endpoint
  516. *
  517. * Return the maximum data that can be queued in one go on a given endpoint
  518. * so that transfers that are too long can be split.
  519. */
  520. static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
  521. {
  522. int index = hs_ep->index;
  523. unsigned int maxsize;
  524. unsigned int maxpkt;
  525. if (index != 0) {
  526. maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
  527. maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
  528. } else {
  529. maxsize = 64 + 64;
  530. if (hs_ep->dir_in)
  531. maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
  532. else
  533. maxpkt = 2;
  534. }
  535. /* we made the constant loading easier above by using +1 */
  536. maxpkt--;
  537. maxsize--;
  538. /*
  539. * constrain by packet count if maxpkts*pktsize is greater
  540. * than the length register size.
  541. */
  542. if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
  543. maxsize = maxpkt * hs_ep->ep.maxpacket;
  544. return maxsize;
  545. }
  546. /**
  547. * dwc2_hsotg_read_frameno - read current frame number
  548. * @hsotg: The device instance
  549. *
  550. * Return the current frame number
  551. */
  552. static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
  553. {
  554. u32 dsts;
  555. dsts = dwc2_readl(hsotg, DSTS);
  556. dsts &= DSTS_SOFFN_MASK;
  557. dsts >>= DSTS_SOFFN_SHIFT;
  558. return dsts;
  559. }
  560. /**
  561. * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
  562. * DMA descriptor chain prepared for specific endpoint
  563. * @hs_ep: The endpoint
  564. *
  565. * Return the maximum data that can be queued in one go on a given endpoint
  566. * depending on its descriptor chain capacity so that transfers that
  567. * are too long can be split.
  568. */
  569. static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
  570. {
  571. const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
  572. int is_isoc = hs_ep->isochronous;
  573. unsigned int maxsize;
  574. u32 mps = hs_ep->ep.maxpacket;
  575. int dir_in = hs_ep->dir_in;
  576. if (is_isoc)
  577. maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
  578. DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
  579. MAX_DMA_DESC_NUM_HS_ISOC;
  580. else
  581. maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
  582. /* Interrupt OUT EP with mps not multiple of 4 */
  583. if (hs_ep->index)
  584. if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
  585. maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
  586. return maxsize;
  587. }
  588. /*
  589. * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
  590. * @hs_ep: The endpoint
  591. * @mask: RX/TX bytes mask to be defined
  592. *
  593. * Returns maximum data payload for one descriptor after analyzing endpoint
  594. * characteristics.
  595. * DMA descriptor transfer bytes limit depends on EP type:
  596. * Control out - MPS,
  597. * Isochronous - descriptor rx/tx bytes bitfield limit,
  598. * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
  599. * have concatenations from various descriptors within one packet.
  600. * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
  601. * to a single descriptor.
  602. *
  603. * Selects corresponding mask for RX/TX bytes as well.
  604. */
  605. static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
  606. {
  607. const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
  608. u32 mps = hs_ep->ep.maxpacket;
  609. int dir_in = hs_ep->dir_in;
  610. u32 desc_size = 0;
  611. if (!hs_ep->index && !dir_in) {
  612. desc_size = mps;
  613. *mask = DEV_DMA_NBYTES_MASK;
  614. } else if (hs_ep->isochronous) {
  615. if (dir_in) {
  616. desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
  617. *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
  618. } else {
  619. desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
  620. *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
  621. }
  622. } else {
  623. desc_size = DEV_DMA_NBYTES_LIMIT;
  624. *mask = DEV_DMA_NBYTES_MASK;
  625. /* Round down desc_size to be mps multiple */
  626. desc_size -= desc_size % mps;
  627. }
  628. /* Interrupt OUT EP with mps not multiple of 4 */
  629. if (hs_ep->index)
  630. if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
  631. desc_size = mps;
  632. *mask = DEV_DMA_NBYTES_MASK;
  633. }
  634. return desc_size;
  635. }
  636. /*
  637. * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
  638. * @hs_ep: The endpoint
  639. * @dma_buff: DMA address to use
  640. * @len: Length of the transfer
  641. *
  642. * This function will iterate over descriptor chain and fill its entries
  643. * with corresponding information based on transfer data.
  644. */
  645. static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
  646. dma_addr_t dma_buff,
  647. unsigned int len)
  648. {
  649. struct dwc2_hsotg *hsotg = hs_ep->parent;
  650. int dir_in = hs_ep->dir_in;
  651. struct dwc2_dma_desc *desc = hs_ep->desc_list;
  652. u32 mps = hs_ep->ep.maxpacket;
  653. u32 maxsize = 0;
  654. u32 offset = 0;
  655. u32 mask = 0;
  656. int i;
  657. maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
  658. hs_ep->desc_count = (len / maxsize) +
  659. ((len % maxsize) ? 1 : 0);
  660. if (len == 0)
  661. hs_ep->desc_count = 1;
  662. for (i = 0; i < hs_ep->desc_count; ++i) {
  663. desc->status = 0;
  664. desc->status |= (DEV_DMA_BUFF_STS_HBUSY
  665. << DEV_DMA_BUFF_STS_SHIFT);
  666. if (len > maxsize) {
  667. if (!hs_ep->index && !dir_in)
  668. desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
  669. desc->status |= (maxsize <<
  670. DEV_DMA_NBYTES_SHIFT & mask);
  671. desc->buf = dma_buff + offset;
  672. len -= maxsize;
  673. offset += maxsize;
  674. } else {
  675. desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
  676. if (dir_in)
  677. desc->status |= (len % mps) ? DEV_DMA_SHORT :
  678. ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
  679. if (len > maxsize)
  680. dev_err(hsotg->dev, "wrong len %d\n", len);
  681. desc->status |=
  682. len << DEV_DMA_NBYTES_SHIFT & mask;
  683. desc->buf = dma_buff + offset;
  684. }
  685. desc->status &= ~DEV_DMA_BUFF_STS_MASK;
  686. desc->status |= (DEV_DMA_BUFF_STS_HREADY
  687. << DEV_DMA_BUFF_STS_SHIFT);
  688. desc++;
  689. }
  690. }
  691. /*
  692. * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
  693. * @hs_ep: The isochronous endpoint.
  694. * @dma_buff: usb requests dma buffer.
  695. * @len: usb request transfer length.
  696. *
  697. * Fills next free descriptor with the data of the arrived usb request,
  698. * frame info, sets Last and IOC bits increments next_desc. If filled
  699. * descriptor is not the first one, removes L bit from the previous descriptor
  700. * status.
  701. */
  702. static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
  703. dma_addr_t dma_buff, unsigned int len)
  704. {
  705. struct dwc2_dma_desc *desc;
  706. struct dwc2_hsotg *hsotg = hs_ep->parent;
  707. u32 index;
  708. u32 maxsize = 0;
  709. u32 mask = 0;
  710. u8 pid = 0;
  711. maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
  712. index = hs_ep->next_desc;
  713. desc = &hs_ep->desc_list[index];
  714. /* Check if descriptor chain full */
  715. if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
  716. DEV_DMA_BUFF_STS_HREADY) {
  717. dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
  718. return 1;
  719. }
  720. /* Clear L bit of previous desc if more than one entries in the chain */
  721. if (hs_ep->next_desc)
  722. hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
  723. dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
  724. __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
  725. desc->status = 0;
  726. desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
  727. desc->buf = dma_buff;
  728. desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
  729. ((len << DEV_DMA_NBYTES_SHIFT) & mask));
  730. if (hs_ep->dir_in) {
  731. if (len)
  732. pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
  733. else
  734. pid = 1;
  735. desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
  736. DEV_DMA_ISOC_PID_MASK) |
  737. ((len % hs_ep->ep.maxpacket) ?
  738. DEV_DMA_SHORT : 0) |
  739. ((hs_ep->target_frame <<
  740. DEV_DMA_ISOC_FRNUM_SHIFT) &
  741. DEV_DMA_ISOC_FRNUM_MASK);
  742. }
  743. desc->status &= ~DEV_DMA_BUFF_STS_MASK;
  744. desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
  745. /* Increment frame number by interval for IN */
  746. if (hs_ep->dir_in)
  747. dwc2_gadget_incr_frame_num(hs_ep);
  748. /* Update index of last configured entry in the chain */
  749. hs_ep->next_desc++;
  750. if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
  751. hs_ep->next_desc = 0;
  752. return 0;
  753. }
  754. /*
  755. * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
  756. * @hs_ep: The isochronous endpoint.
  757. *
  758. * Prepare descriptor chain for isochronous endpoints. Afterwards
  759. * write DMA address to HW and enable the endpoint.
  760. */
  761. static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
  762. {
  763. struct dwc2_hsotg *hsotg = hs_ep->parent;
  764. struct dwc2_hsotg_req *hs_req, *treq;
  765. int index = hs_ep->index;
  766. int ret;
  767. int i;
  768. u32 dma_reg;
  769. u32 depctl;
  770. u32 ctrl;
  771. struct dwc2_dma_desc *desc;
  772. if (list_empty(&hs_ep->queue)) {
  773. hs_ep->target_frame = TARGET_FRAME_INITIAL;
  774. dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
  775. return;
  776. }
  777. /* Initialize descriptor chain by Host Busy status */
  778. for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
  779. desc = &hs_ep->desc_list[i];
  780. desc->status = 0;
  781. desc->status |= (DEV_DMA_BUFF_STS_HBUSY
  782. << DEV_DMA_BUFF_STS_SHIFT);
  783. }
  784. hs_ep->next_desc = 0;
  785. list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
  786. ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
  787. hs_req->req.length);
  788. if (ret)
  789. break;
  790. }
  791. hs_ep->compl_desc = 0;
  792. depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
  793. dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
  794. /* write descriptor chain address to control register */
  795. dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
  796. ctrl = dwc2_readl(hsotg, depctl);
  797. ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
  798. dwc2_writel(hsotg, ctrl, depctl);
  799. }
  800. /**
  801. * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
  802. * @hsotg: The controller state.
  803. * @hs_ep: The endpoint to process a request for
  804. * @hs_req: The request to start.
  805. * @continuing: True if we are doing more for the current request.
  806. *
  807. * Start the given request running by setting the endpoint registers
  808. * appropriately, and writing any data to the FIFOs.
  809. */
  810. static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
  811. struct dwc2_hsotg_ep *hs_ep,
  812. struct dwc2_hsotg_req *hs_req,
  813. bool continuing)
  814. {
  815. struct usb_request *ureq = &hs_req->req;
  816. int index = hs_ep->index;
  817. int dir_in = hs_ep->dir_in;
  818. u32 epctrl_reg;
  819. u32 epsize_reg;
  820. u32 epsize;
  821. u32 ctrl;
  822. unsigned int length;
  823. unsigned int packets;
  824. unsigned int maxreq;
  825. unsigned int dma_reg;
  826. if (index != 0) {
  827. if (hs_ep->req && !continuing) {
  828. dev_err(hsotg->dev, "%s: active request\n", __func__);
  829. WARN_ON(1);
  830. return;
  831. } else if (hs_ep->req != hs_req && continuing) {
  832. dev_err(hsotg->dev,
  833. "%s: continue different req\n", __func__);
  834. WARN_ON(1);
  835. return;
  836. }
  837. }
  838. dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
  839. epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
  840. epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
  841. dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
  842. __func__, dwc2_readl(hsotg, epctrl_reg), index,
  843. hs_ep->dir_in ? "in" : "out");
  844. /* If endpoint is stalled, we will restart request later */
  845. ctrl = dwc2_readl(hsotg, epctrl_reg);
  846. if (index && ctrl & DXEPCTL_STALL) {
  847. dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
  848. return;
  849. }
  850. length = ureq->length - ureq->actual;
  851. dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
  852. ureq->length, ureq->actual);
  853. if (!using_desc_dma(hsotg))
  854. maxreq = get_ep_limit(hs_ep);
  855. else
  856. maxreq = dwc2_gadget_get_chain_limit(hs_ep);
  857. if (length > maxreq) {
  858. int round = maxreq % hs_ep->ep.maxpacket;
  859. dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
  860. __func__, length, maxreq, round);
  861. /* round down to multiple of packets */
  862. if (round)
  863. maxreq -= round;
  864. length = maxreq;
  865. }
  866. if (length)
  867. packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
  868. else
  869. packets = 1; /* send one packet if length is zero. */
  870. if (dir_in && index != 0)
  871. if (hs_ep->isochronous)
  872. epsize = DXEPTSIZ_MC(packets);
  873. else
  874. epsize = DXEPTSIZ_MC(1);
  875. else
  876. epsize = 0;
  877. /*
  878. * zero length packet should be programmed on its own and should not
  879. * be counted in DIEPTSIZ.PktCnt with other packets.
  880. */
  881. if (dir_in && ureq->zero && !continuing) {
  882. /* Test if zlp is actually required. */
  883. if ((ureq->length >= hs_ep->ep.maxpacket) &&
  884. !(ureq->length % hs_ep->ep.maxpacket))
  885. hs_ep->send_zlp = 1;
  886. }
  887. epsize |= DXEPTSIZ_PKTCNT(packets);
  888. epsize |= DXEPTSIZ_XFERSIZE(length);
  889. dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
  890. __func__, packets, length, ureq->length, epsize, epsize_reg);
  891. /* store the request as the current one we're doing */
  892. hs_ep->req = hs_req;
  893. if (using_desc_dma(hsotg)) {
  894. u32 offset = 0;
  895. u32 mps = hs_ep->ep.maxpacket;
  896. /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
  897. if (!dir_in) {
  898. if (!index)
  899. length = mps;
  900. else if (length % mps)
  901. length += (mps - (length % mps));
  902. }
  903. if (continuing)
  904. offset = ureq->actual;
  905. /* Fill DDMA chain entries */
  906. dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
  907. length);
  908. /* write descriptor chain address to control register */
  909. dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
  910. dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
  911. __func__, (u32)hs_ep->desc_list_dma, dma_reg);
  912. } else {
  913. /* write size / packets */
  914. dwc2_writel(hsotg, epsize, epsize_reg);
  915. if (using_dma(hsotg) && !continuing && (length != 0)) {
  916. /*
  917. * write DMA address to control register, buffer
  918. * already synced by dwc2_hsotg_ep_queue().
  919. */
  920. dwc2_writel(hsotg, ureq->dma, dma_reg);
  921. dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
  922. __func__, &ureq->dma, dma_reg);
  923. }
  924. }
  925. if (hs_ep->isochronous && hs_ep->interval == 1) {
  926. hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
  927. dwc2_gadget_incr_frame_num(hs_ep);
  928. if (hs_ep->target_frame & 0x1)
  929. ctrl |= DXEPCTL_SETODDFR;
  930. else
  931. ctrl |= DXEPCTL_SETEVENFR;
  932. }
  933. ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
  934. dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
  935. /* For Setup request do not clear NAK */
  936. if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
  937. ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
  938. dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
  939. dwc2_writel(hsotg, ctrl, epctrl_reg);
  940. /*
  941. * set these, it seems that DMA support increments past the end
  942. * of the packet buffer so we need to calculate the length from
  943. * this information.
  944. */
  945. hs_ep->size_loaded = length;
  946. hs_ep->last_load = ureq->actual;
  947. if (dir_in && !using_dma(hsotg)) {
  948. /* set these anyway, we may need them for non-periodic in */
  949. hs_ep->fifo_load = 0;
  950. dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
  951. }
  952. /*
  953. * Note, trying to clear the NAK here causes problems with transmit
  954. * on the S3C6400 ending up with the TXFIFO becoming full.
  955. */
  956. /* check ep is enabled */
  957. if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
  958. dev_dbg(hsotg->dev,
  959. "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
  960. index, dwc2_readl(hsotg, epctrl_reg));
  961. dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
  962. __func__, dwc2_readl(hsotg, epctrl_reg));
  963. /* enable ep interrupts */
  964. dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
  965. }
  966. /**
  967. * dwc2_hsotg_map_dma - map the DMA memory being used for the request
  968. * @hsotg: The device state.
  969. * @hs_ep: The endpoint the request is on.
  970. * @req: The request being processed.
  971. *
  972. * We've been asked to queue a request, so ensure that the memory buffer
  973. * is correctly setup for DMA. If we've been passed an extant DMA address
  974. * then ensure the buffer has been synced to memory. If our buffer has no
  975. * DMA memory, then we map the memory and mark our request to allow us to
  976. * cleanup on completion.
  977. */
  978. static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
  979. struct dwc2_hsotg_ep *hs_ep,
  980. struct usb_request *req)
  981. {
  982. int ret;
  983. hs_ep->map_dir = hs_ep->dir_in;
  984. ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
  985. if (ret)
  986. goto dma_error;
  987. return 0;
  988. dma_error:
  989. dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
  990. __func__, req->buf, req->length);
  991. return -EIO;
  992. }
  993. static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
  994. struct dwc2_hsotg_ep *hs_ep,
  995. struct dwc2_hsotg_req *hs_req)
  996. {
  997. void *req_buf = hs_req->req.buf;
  998. /* If dma is not being used or buffer is aligned */
  999. if (!using_dma(hsotg) || !((long)req_buf & 3))
  1000. return 0;
  1001. WARN_ON(hs_req->saved_req_buf);
  1002. dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
  1003. hs_ep->ep.name, req_buf, hs_req->req.length);
  1004. hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
  1005. if (!hs_req->req.buf) {
  1006. hs_req->req.buf = req_buf;
  1007. dev_err(hsotg->dev,
  1008. "%s: unable to allocate memory for bounce buffer\n",
  1009. __func__);
  1010. return -ENOMEM;
  1011. }
  1012. /* Save actual buffer */
  1013. hs_req->saved_req_buf = req_buf;
  1014. if (hs_ep->dir_in)
  1015. memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
  1016. return 0;
  1017. }
  1018. static void
  1019. dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
  1020. struct dwc2_hsotg_ep *hs_ep,
  1021. struct dwc2_hsotg_req *hs_req)
  1022. {
  1023. /* If dma is not being used or buffer was aligned */
  1024. if (!using_dma(hsotg) || !hs_req->saved_req_buf)
  1025. return;
  1026. dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
  1027. hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
  1028. /* Copy data from bounce buffer on successful out transfer */
  1029. if (!hs_ep->dir_in && !hs_req->req.status)
  1030. memcpy(hs_req->saved_req_buf, hs_req->req.buf,
  1031. hs_req->req.actual);
  1032. /* Free bounce buffer */
  1033. kfree(hs_req->req.buf);
  1034. hs_req->req.buf = hs_req->saved_req_buf;
  1035. hs_req->saved_req_buf = NULL;
  1036. }
  1037. /**
  1038. * dwc2_gadget_target_frame_elapsed - Checks target frame
  1039. * @hs_ep: The driver endpoint to check
  1040. *
  1041. * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
  1042. * corresponding transfer.
  1043. */
  1044. static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
  1045. {
  1046. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1047. u32 target_frame = hs_ep->target_frame;
  1048. u32 current_frame = hsotg->frame_number;
  1049. bool frame_overrun = hs_ep->frame_overrun;
  1050. if (!frame_overrun && current_frame >= target_frame)
  1051. return true;
  1052. if (frame_overrun && current_frame >= target_frame &&
  1053. ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
  1054. return true;
  1055. return false;
  1056. }
  1057. /*
  1058. * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
  1059. * @hsotg: The driver state
  1060. * @hs_ep: the ep descriptor chain is for
  1061. *
  1062. * Called to update EP0 structure's pointers depend on stage of
  1063. * control transfer.
  1064. */
  1065. static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
  1066. struct dwc2_hsotg_ep *hs_ep)
  1067. {
  1068. switch (hsotg->ep0_state) {
  1069. case DWC2_EP0_SETUP:
  1070. case DWC2_EP0_STATUS_OUT:
  1071. hs_ep->desc_list = hsotg->setup_desc[0];
  1072. hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
  1073. break;
  1074. case DWC2_EP0_DATA_IN:
  1075. case DWC2_EP0_STATUS_IN:
  1076. hs_ep->desc_list = hsotg->ctrl_in_desc;
  1077. hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
  1078. break;
  1079. case DWC2_EP0_DATA_OUT:
  1080. hs_ep->desc_list = hsotg->ctrl_out_desc;
  1081. hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
  1082. break;
  1083. default:
  1084. dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
  1085. hsotg->ep0_state);
  1086. return -EINVAL;
  1087. }
  1088. return 0;
  1089. }
  1090. static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
  1091. gfp_t gfp_flags)
  1092. {
  1093. struct dwc2_hsotg_req *hs_req = our_req(req);
  1094. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  1095. struct dwc2_hsotg *hs = hs_ep->parent;
  1096. bool first;
  1097. int ret;
  1098. u32 maxsize = 0;
  1099. u32 mask = 0;
  1100. dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
  1101. ep->name, req, req->length, req->buf, req->no_interrupt,
  1102. req->zero, req->short_not_ok);
  1103. /* Prevent new request submission when controller is suspended */
  1104. if (hs->lx_state != DWC2_L0) {
  1105. dev_dbg(hs->dev, "%s: submit request only in active state\n",
  1106. __func__);
  1107. return -EAGAIN;
  1108. }
  1109. /* initialise status of the request */
  1110. INIT_LIST_HEAD(&hs_req->queue);
  1111. req->actual = 0;
  1112. req->status = -EINPROGRESS;
  1113. /* Don't queue ISOC request if length greater than mps*mc */
  1114. if (hs_ep->isochronous &&
  1115. req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
  1116. dev_err(hs->dev, "req length > maxpacket*mc\n");
  1117. return -EINVAL;
  1118. }
  1119. /* In DDMA mode for ISOC's don't queue request if length greater
  1120. * than descriptor limits.
  1121. */
  1122. if (using_desc_dma(hs) && hs_ep->isochronous) {
  1123. maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
  1124. if (hs_ep->dir_in && req->length > maxsize) {
  1125. dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
  1126. req->length, maxsize);
  1127. return -EINVAL;
  1128. }
  1129. if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
  1130. dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
  1131. req->length, hs_ep->ep.maxpacket);
  1132. return -EINVAL;
  1133. }
  1134. }
  1135. ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
  1136. if (ret)
  1137. return ret;
  1138. /* if we're using DMA, sync the buffers as necessary */
  1139. if (using_dma(hs)) {
  1140. ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
  1141. if (ret)
  1142. return ret;
  1143. }
  1144. /* If using descriptor DMA configure EP0 descriptor chain pointers */
  1145. if (using_desc_dma(hs) && !hs_ep->index) {
  1146. ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
  1147. if (ret)
  1148. return ret;
  1149. }
  1150. first = list_empty(&hs_ep->queue);
  1151. list_add_tail(&hs_req->queue, &hs_ep->queue);
  1152. /*
  1153. * Handle DDMA isochronous transfers separately - just add new entry
  1154. * to the descriptor chain.
  1155. * Transfer will be started once SW gets either one of NAK or
  1156. * OutTknEpDis interrupts.
  1157. */
  1158. if (using_desc_dma(hs) && hs_ep->isochronous) {
  1159. if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
  1160. dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
  1161. hs_req->req.length);
  1162. }
  1163. return 0;
  1164. }
  1165. if (first) {
  1166. if (!hs_ep->isochronous) {
  1167. dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
  1168. return 0;
  1169. }
  1170. /* Update current frame number value. */
  1171. hs->frame_number = dwc2_hsotg_read_frameno(hs);
  1172. while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
  1173. dwc2_gadget_incr_frame_num(hs_ep);
  1174. /* Update current frame number value once more as it
  1175. * changes here.
  1176. */
  1177. hs->frame_number = dwc2_hsotg_read_frameno(hs);
  1178. }
  1179. if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
  1180. dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
  1181. }
  1182. return 0;
  1183. }
  1184. static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
  1185. gfp_t gfp_flags)
  1186. {
  1187. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  1188. struct dwc2_hsotg *hs = hs_ep->parent;
  1189. unsigned long flags = 0;
  1190. int ret = 0;
  1191. spin_lock_irqsave(&hs->lock, flags);
  1192. ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
  1193. spin_unlock_irqrestore(&hs->lock, flags);
  1194. return ret;
  1195. }
  1196. static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
  1197. struct usb_request *req)
  1198. {
  1199. struct dwc2_hsotg_req *hs_req = our_req(req);
  1200. kfree(hs_req);
  1201. }
  1202. /**
  1203. * dwc2_hsotg_complete_oursetup - setup completion callback
  1204. * @ep: The endpoint the request was on.
  1205. * @req: The request completed.
  1206. *
  1207. * Called on completion of any requests the driver itself
  1208. * submitted that need cleaning up.
  1209. */
  1210. static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
  1211. struct usb_request *req)
  1212. {
  1213. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  1214. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1215. dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
  1216. dwc2_hsotg_ep_free_request(ep, req);
  1217. }
  1218. /**
  1219. * ep_from_windex - convert control wIndex value to endpoint
  1220. * @hsotg: The driver state.
  1221. * @windex: The control request wIndex field (in host order).
  1222. *
  1223. * Convert the given wIndex into a pointer to an driver endpoint
  1224. * structure, or return NULL if it is not a valid endpoint.
  1225. */
  1226. static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
  1227. u32 windex)
  1228. {
  1229. int dir = (windex & USB_DIR_IN) ? 1 : 0;
  1230. int idx = windex & 0x7F;
  1231. if (windex >= 0x100)
  1232. return NULL;
  1233. if (idx > hsotg->num_of_eps)
  1234. return NULL;
  1235. return index_to_ep(hsotg, idx, dir);
  1236. }
  1237. /**
  1238. * dwc2_hsotg_set_test_mode - Enable usb Test Modes
  1239. * @hsotg: The driver state.
  1240. * @testmode: requested usb test mode
  1241. * Enable usb Test Mode requested by the Host.
  1242. */
  1243. int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
  1244. {
  1245. int dctl = dwc2_readl(hsotg, DCTL);
  1246. dctl &= ~DCTL_TSTCTL_MASK;
  1247. switch (testmode) {
  1248. case TEST_J:
  1249. case TEST_K:
  1250. case TEST_SE0_NAK:
  1251. case TEST_PACKET:
  1252. case TEST_FORCE_EN:
  1253. dctl |= testmode << DCTL_TSTCTL_SHIFT;
  1254. break;
  1255. default:
  1256. return -EINVAL;
  1257. }
  1258. dwc2_writel(hsotg, dctl, DCTL);
  1259. return 0;
  1260. }
  1261. /**
  1262. * dwc2_hsotg_send_reply - send reply to control request
  1263. * @hsotg: The device state
  1264. * @ep: Endpoint 0
  1265. * @buff: Buffer for request
  1266. * @length: Length of reply.
  1267. *
  1268. * Create a request and queue it on the given endpoint. This is useful as
  1269. * an internal method of sending replies to certain control requests, etc.
  1270. */
  1271. static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
  1272. struct dwc2_hsotg_ep *ep,
  1273. void *buff,
  1274. int length)
  1275. {
  1276. struct usb_request *req;
  1277. int ret;
  1278. dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
  1279. req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
  1280. hsotg->ep0_reply = req;
  1281. if (!req) {
  1282. dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
  1283. return -ENOMEM;
  1284. }
  1285. req->buf = hsotg->ep0_buff;
  1286. req->length = length;
  1287. /*
  1288. * zero flag is for sending zlp in DATA IN stage. It has no impact on
  1289. * STATUS stage.
  1290. */
  1291. req->zero = 0;
  1292. req->complete = dwc2_hsotg_complete_oursetup;
  1293. if (length)
  1294. memcpy(req->buf, buff, length);
  1295. ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
  1296. if (ret) {
  1297. dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
  1298. return ret;
  1299. }
  1300. return 0;
  1301. }
  1302. /**
  1303. * dwc2_hsotg_process_req_status - process request GET_STATUS
  1304. * @hsotg: The device state
  1305. * @ctrl: USB control request
  1306. */
  1307. static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
  1308. struct usb_ctrlrequest *ctrl)
  1309. {
  1310. struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
  1311. struct dwc2_hsotg_ep *ep;
  1312. __le16 reply;
  1313. u16 status;
  1314. int ret;
  1315. dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
  1316. if (!ep0->dir_in) {
  1317. dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
  1318. return -EINVAL;
  1319. }
  1320. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  1321. case USB_RECIP_DEVICE:
  1322. status = 1 << USB_DEVICE_SELF_POWERED;
  1323. status |= hsotg->remote_wakeup_allowed <<
  1324. USB_DEVICE_REMOTE_WAKEUP;
  1325. reply = cpu_to_le16(status);
  1326. break;
  1327. case USB_RECIP_INTERFACE:
  1328. /* currently, the data result should be zero */
  1329. reply = cpu_to_le16(0);
  1330. break;
  1331. case USB_RECIP_ENDPOINT:
  1332. ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
  1333. if (!ep)
  1334. return -ENOENT;
  1335. reply = cpu_to_le16(ep->halted ? 1 : 0);
  1336. break;
  1337. default:
  1338. return 0;
  1339. }
  1340. if (le16_to_cpu(ctrl->wLength) != 2)
  1341. return -EINVAL;
  1342. ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
  1343. if (ret) {
  1344. dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
  1345. return ret;
  1346. }
  1347. return 1;
  1348. }
  1349. static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
  1350. /**
  1351. * get_ep_head - return the first request on the endpoint
  1352. * @hs_ep: The controller endpoint to get
  1353. *
  1354. * Get the first request on the endpoint.
  1355. */
  1356. static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
  1357. {
  1358. return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
  1359. queue);
  1360. }
  1361. /**
  1362. * dwc2_gadget_start_next_request - Starts next request from ep queue
  1363. * @hs_ep: Endpoint structure
  1364. *
  1365. * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
  1366. * in its handler. Hence we need to unmask it here to be able to do
  1367. * resynchronization.
  1368. */
  1369. static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
  1370. {
  1371. u32 mask;
  1372. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1373. int dir_in = hs_ep->dir_in;
  1374. struct dwc2_hsotg_req *hs_req;
  1375. u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
  1376. if (!list_empty(&hs_ep->queue)) {
  1377. hs_req = get_ep_head(hs_ep);
  1378. dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
  1379. return;
  1380. }
  1381. if (!hs_ep->isochronous)
  1382. return;
  1383. if (dir_in) {
  1384. dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
  1385. __func__);
  1386. } else {
  1387. dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
  1388. __func__);
  1389. mask = dwc2_readl(hsotg, epmsk_reg);
  1390. mask |= DOEPMSK_OUTTKNEPDISMSK;
  1391. dwc2_writel(hsotg, mask, epmsk_reg);
  1392. }
  1393. }
  1394. /**
  1395. * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
  1396. * @hsotg: The device state
  1397. * @ctrl: USB control request
  1398. */
  1399. static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
  1400. struct usb_ctrlrequest *ctrl)
  1401. {
  1402. struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
  1403. struct dwc2_hsotg_req *hs_req;
  1404. bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
  1405. struct dwc2_hsotg_ep *ep;
  1406. int ret;
  1407. bool halted;
  1408. u32 recip;
  1409. u32 wValue;
  1410. u32 wIndex;
  1411. dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
  1412. __func__, set ? "SET" : "CLEAR");
  1413. wValue = le16_to_cpu(ctrl->wValue);
  1414. wIndex = le16_to_cpu(ctrl->wIndex);
  1415. recip = ctrl->bRequestType & USB_RECIP_MASK;
  1416. switch (recip) {
  1417. case USB_RECIP_DEVICE:
  1418. switch (wValue) {
  1419. case USB_DEVICE_REMOTE_WAKEUP:
  1420. if (set)
  1421. hsotg->remote_wakeup_allowed = 1;
  1422. else
  1423. hsotg->remote_wakeup_allowed = 0;
  1424. break;
  1425. case USB_DEVICE_TEST_MODE:
  1426. if ((wIndex & 0xff) != 0)
  1427. return -EINVAL;
  1428. if (!set)
  1429. return -EINVAL;
  1430. hsotg->test_mode = wIndex >> 8;
  1431. break;
  1432. default:
  1433. return -ENOENT;
  1434. }
  1435. ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
  1436. if (ret) {
  1437. dev_err(hsotg->dev,
  1438. "%s: failed to send reply\n", __func__);
  1439. return ret;
  1440. }
  1441. break;
  1442. case USB_RECIP_ENDPOINT:
  1443. ep = ep_from_windex(hsotg, wIndex);
  1444. if (!ep) {
  1445. dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
  1446. __func__, wIndex);
  1447. return -ENOENT;
  1448. }
  1449. switch (wValue) {
  1450. case USB_ENDPOINT_HALT:
  1451. halted = ep->halted;
  1452. dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
  1453. ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
  1454. if (ret) {
  1455. dev_err(hsotg->dev,
  1456. "%s: failed to send reply\n", __func__);
  1457. return ret;
  1458. }
  1459. /*
  1460. * we have to complete all requests for ep if it was
  1461. * halted, and the halt was cleared by CLEAR_FEATURE
  1462. */
  1463. if (!set && halted) {
  1464. /*
  1465. * If we have request in progress,
  1466. * then complete it
  1467. */
  1468. if (ep->req) {
  1469. hs_req = ep->req;
  1470. ep->req = NULL;
  1471. list_del_init(&hs_req->queue);
  1472. if (hs_req->req.complete) {
  1473. spin_unlock(&hsotg->lock);
  1474. usb_gadget_giveback_request(
  1475. &ep->ep, &hs_req->req);
  1476. spin_lock(&hsotg->lock);
  1477. }
  1478. }
  1479. /* If we have pending request, then start it */
  1480. if (!ep->req)
  1481. dwc2_gadget_start_next_request(ep);
  1482. }
  1483. break;
  1484. default:
  1485. return -ENOENT;
  1486. }
  1487. break;
  1488. default:
  1489. return -ENOENT;
  1490. }
  1491. return 1;
  1492. }
  1493. static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
  1494. /**
  1495. * dwc2_hsotg_stall_ep0 - stall ep0
  1496. * @hsotg: The device state
  1497. *
  1498. * Set stall for ep0 as response for setup request.
  1499. */
  1500. static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
  1501. {
  1502. struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
  1503. u32 reg;
  1504. u32 ctrl;
  1505. dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
  1506. reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
  1507. /*
  1508. * DxEPCTL_Stall will be cleared by EP once it has
  1509. * taken effect, so no need to clear later.
  1510. */
  1511. ctrl = dwc2_readl(hsotg, reg);
  1512. ctrl |= DXEPCTL_STALL;
  1513. ctrl |= DXEPCTL_CNAK;
  1514. dwc2_writel(hsotg, ctrl, reg);
  1515. dev_dbg(hsotg->dev,
  1516. "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
  1517. ctrl, reg, dwc2_readl(hsotg, reg));
  1518. /*
  1519. * complete won't be called, so we enqueue
  1520. * setup request here
  1521. */
  1522. dwc2_hsotg_enqueue_setup(hsotg);
  1523. }
  1524. /**
  1525. * dwc2_hsotg_process_control - process a control request
  1526. * @hsotg: The device state
  1527. * @ctrl: The control request received
  1528. *
  1529. * The controller has received the SETUP phase of a control request, and
  1530. * needs to work out what to do next (and whether to pass it on to the
  1531. * gadget driver).
  1532. */
  1533. static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
  1534. struct usb_ctrlrequest *ctrl)
  1535. {
  1536. struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
  1537. int ret = 0;
  1538. u32 dcfg;
  1539. dev_dbg(hsotg->dev,
  1540. "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
  1541. ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
  1542. ctrl->wIndex, ctrl->wLength);
  1543. if (ctrl->wLength == 0) {
  1544. ep0->dir_in = 1;
  1545. hsotg->ep0_state = DWC2_EP0_STATUS_IN;
  1546. } else if (ctrl->bRequestType & USB_DIR_IN) {
  1547. ep0->dir_in = 1;
  1548. hsotg->ep0_state = DWC2_EP0_DATA_IN;
  1549. } else {
  1550. ep0->dir_in = 0;
  1551. hsotg->ep0_state = DWC2_EP0_DATA_OUT;
  1552. }
  1553. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1554. switch (ctrl->bRequest) {
  1555. case USB_REQ_SET_ADDRESS:
  1556. hsotg->connected = 1;
  1557. dcfg = dwc2_readl(hsotg, DCFG);
  1558. dcfg &= ~DCFG_DEVADDR_MASK;
  1559. dcfg |= (le16_to_cpu(ctrl->wValue) <<
  1560. DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
  1561. dwc2_writel(hsotg, dcfg, DCFG);
  1562. dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
  1563. ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
  1564. return;
  1565. case USB_REQ_GET_STATUS:
  1566. ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
  1567. break;
  1568. case USB_REQ_CLEAR_FEATURE:
  1569. case USB_REQ_SET_FEATURE:
  1570. ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
  1571. break;
  1572. }
  1573. }
  1574. /* as a fallback, try delivering it to the driver to deal with */
  1575. if (ret == 0 && hsotg->driver) {
  1576. spin_unlock(&hsotg->lock);
  1577. ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
  1578. spin_lock(&hsotg->lock);
  1579. if (ret < 0)
  1580. dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
  1581. }
  1582. /*
  1583. * the request is either unhandlable, or is not formatted correctly
  1584. * so respond with a STALL for the status stage to indicate failure.
  1585. */
  1586. if (ret < 0)
  1587. dwc2_hsotg_stall_ep0(hsotg);
  1588. }
  1589. /**
  1590. * dwc2_hsotg_complete_setup - completion of a setup transfer
  1591. * @ep: The endpoint the request was on.
  1592. * @req: The request completed.
  1593. *
  1594. * Called on completion of any requests the driver itself submitted for
  1595. * EP0 setup packets
  1596. */
  1597. static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
  1598. struct usb_request *req)
  1599. {
  1600. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  1601. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1602. if (req->status < 0) {
  1603. dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
  1604. return;
  1605. }
  1606. spin_lock(&hsotg->lock);
  1607. if (req->actual == 0)
  1608. dwc2_hsotg_enqueue_setup(hsotg);
  1609. else
  1610. dwc2_hsotg_process_control(hsotg, req->buf);
  1611. spin_unlock(&hsotg->lock);
  1612. }
  1613. /**
  1614. * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
  1615. * @hsotg: The device state.
  1616. *
  1617. * Enqueue a request on EP0 if necessary to received any SETUP packets
  1618. * received from the host.
  1619. */
  1620. static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
  1621. {
  1622. struct usb_request *req = hsotg->ctrl_req;
  1623. struct dwc2_hsotg_req *hs_req = our_req(req);
  1624. int ret;
  1625. dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
  1626. req->zero = 0;
  1627. req->length = 8;
  1628. req->buf = hsotg->ctrl_buff;
  1629. req->complete = dwc2_hsotg_complete_setup;
  1630. if (!list_empty(&hs_req->queue)) {
  1631. dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
  1632. return;
  1633. }
  1634. hsotg->eps_out[0]->dir_in = 0;
  1635. hsotg->eps_out[0]->send_zlp = 0;
  1636. hsotg->ep0_state = DWC2_EP0_SETUP;
  1637. ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
  1638. if (ret < 0) {
  1639. dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
  1640. /*
  1641. * Don't think there's much we can do other than watch the
  1642. * driver fail.
  1643. */
  1644. }
  1645. }
  1646. static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
  1647. struct dwc2_hsotg_ep *hs_ep)
  1648. {
  1649. u32 ctrl;
  1650. u8 index = hs_ep->index;
  1651. u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
  1652. u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
  1653. if (hs_ep->dir_in)
  1654. dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
  1655. index);
  1656. else
  1657. dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
  1658. index);
  1659. if (using_desc_dma(hsotg)) {
  1660. /* Not specific buffer needed for ep0 ZLP */
  1661. dma_addr_t dma = hs_ep->desc_list_dma;
  1662. if (!index)
  1663. dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
  1664. dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
  1665. } else {
  1666. dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
  1667. DXEPTSIZ_XFERSIZE(0),
  1668. epsiz_reg);
  1669. }
  1670. ctrl = dwc2_readl(hsotg, epctl_reg);
  1671. ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
  1672. ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
  1673. ctrl |= DXEPCTL_USBACTEP;
  1674. dwc2_writel(hsotg, ctrl, epctl_reg);
  1675. }
  1676. /**
  1677. * dwc2_hsotg_complete_request - complete a request given to us
  1678. * @hsotg: The device state.
  1679. * @hs_ep: The endpoint the request was on.
  1680. * @hs_req: The request to complete.
  1681. * @result: The result code (0 => Ok, otherwise errno)
  1682. *
  1683. * The given request has finished, so call the necessary completion
  1684. * if it has one and then look to see if we can start a new request
  1685. * on the endpoint.
  1686. *
  1687. * Note, expects the ep to already be locked as appropriate.
  1688. */
  1689. static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
  1690. struct dwc2_hsotg_ep *hs_ep,
  1691. struct dwc2_hsotg_req *hs_req,
  1692. int result)
  1693. {
  1694. if (!hs_req) {
  1695. dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
  1696. return;
  1697. }
  1698. dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
  1699. hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
  1700. /*
  1701. * only replace the status if we've not already set an error
  1702. * from a previous transaction
  1703. */
  1704. if (hs_req->req.status == -EINPROGRESS)
  1705. hs_req->req.status = result;
  1706. if (using_dma(hsotg))
  1707. dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
  1708. dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
  1709. hs_ep->req = NULL;
  1710. list_del_init(&hs_req->queue);
  1711. /*
  1712. * call the complete request with the locks off, just in case the
  1713. * request tries to queue more work for this endpoint.
  1714. */
  1715. if (hs_req->req.complete) {
  1716. spin_unlock(&hsotg->lock);
  1717. usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
  1718. spin_lock(&hsotg->lock);
  1719. }
  1720. /* In DDMA don't need to proceed to starting of next ISOC request */
  1721. if (using_desc_dma(hsotg) && hs_ep->isochronous)
  1722. return;
  1723. /*
  1724. * Look to see if there is anything else to do. Note, the completion
  1725. * of the previous request may have caused a new request to be started
  1726. * so be careful when doing this.
  1727. */
  1728. if (!hs_ep->req && result >= 0)
  1729. dwc2_gadget_start_next_request(hs_ep);
  1730. }
  1731. /*
  1732. * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
  1733. * @hs_ep: The endpoint the request was on.
  1734. *
  1735. * Get first request from the ep queue, determine descriptor on which complete
  1736. * happened. SW discovers which descriptor currently in use by HW, adjusts
  1737. * dma_address and calculates index of completed descriptor based on the value
  1738. * of DEPDMA register. Update actual length of request, giveback to gadget.
  1739. */
  1740. static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
  1741. {
  1742. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1743. struct dwc2_hsotg_req *hs_req;
  1744. struct usb_request *ureq;
  1745. u32 desc_sts;
  1746. u32 mask;
  1747. desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
  1748. /* Process only descriptors with buffer status set to DMA done */
  1749. while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
  1750. DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
  1751. hs_req = get_ep_head(hs_ep);
  1752. if (!hs_req) {
  1753. dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
  1754. return;
  1755. }
  1756. ureq = &hs_req->req;
  1757. /* Check completion status */
  1758. if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
  1759. DEV_DMA_STS_SUCC) {
  1760. mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
  1761. DEV_DMA_ISOC_RX_NBYTES_MASK;
  1762. ureq->actual = ureq->length - ((desc_sts & mask) >>
  1763. DEV_DMA_ISOC_NBYTES_SHIFT);
  1764. /* Adjust actual len for ISOC Out if len is
  1765. * not align of 4
  1766. */
  1767. if (!hs_ep->dir_in && ureq->length & 0x3)
  1768. ureq->actual += 4 - (ureq->length & 0x3);
  1769. }
  1770. dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
  1771. hs_ep->compl_desc++;
  1772. if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
  1773. hs_ep->compl_desc = 0;
  1774. desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
  1775. }
  1776. }
  1777. /*
  1778. * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
  1779. * @hs_ep: The isochronous endpoint.
  1780. *
  1781. * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
  1782. * interrupt. Reset target frame and next_desc to allow to start
  1783. * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
  1784. * interrupt for OUT direction.
  1785. */
  1786. static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
  1787. {
  1788. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1789. if (!hs_ep->dir_in)
  1790. dwc2_flush_rx_fifo(hsotg);
  1791. dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
  1792. hs_ep->target_frame = TARGET_FRAME_INITIAL;
  1793. hs_ep->next_desc = 0;
  1794. hs_ep->compl_desc = 0;
  1795. }
  1796. /**
  1797. * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
  1798. * @hsotg: The device state.
  1799. * @ep_idx: The endpoint index for the data
  1800. * @size: The size of data in the fifo, in bytes
  1801. *
  1802. * The FIFO status shows there is data to read from the FIFO for a given
  1803. * endpoint, so sort out whether we need to read the data into a request
  1804. * that has been made for that endpoint.
  1805. */
  1806. static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
  1807. {
  1808. struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
  1809. struct dwc2_hsotg_req *hs_req = hs_ep->req;
  1810. int to_read;
  1811. int max_req;
  1812. int read_ptr;
  1813. if (!hs_req) {
  1814. u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
  1815. int ptr;
  1816. dev_dbg(hsotg->dev,
  1817. "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
  1818. __func__, size, ep_idx, epctl);
  1819. /* dump the data from the FIFO, we've nothing we can do */
  1820. for (ptr = 0; ptr < size; ptr += 4)
  1821. (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
  1822. return;
  1823. }
  1824. to_read = size;
  1825. read_ptr = hs_req->req.actual;
  1826. max_req = hs_req->req.length - read_ptr;
  1827. dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
  1828. __func__, to_read, max_req, read_ptr, hs_req->req.length);
  1829. if (to_read > max_req) {
  1830. /*
  1831. * more data appeared than we where willing
  1832. * to deal with in this request.
  1833. */
  1834. /* currently we don't deal this */
  1835. WARN_ON_ONCE(1);
  1836. }
  1837. hs_ep->total_data += to_read;
  1838. hs_req->req.actual += to_read;
  1839. to_read = DIV_ROUND_UP(to_read, 4);
  1840. /*
  1841. * note, we might over-write the buffer end by 3 bytes depending on
  1842. * alignment of the data.
  1843. */
  1844. dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
  1845. hs_req->req.buf + read_ptr, to_read);
  1846. }
  1847. /**
  1848. * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
  1849. * @hsotg: The device instance
  1850. * @dir_in: If IN zlp
  1851. *
  1852. * Generate a zero-length IN packet request for terminating a SETUP
  1853. * transaction.
  1854. *
  1855. * Note, since we don't write any data to the TxFIFO, then it is
  1856. * currently believed that we do not need to wait for any space in
  1857. * the TxFIFO.
  1858. */
  1859. static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
  1860. {
  1861. /* eps_out[0] is used in both directions */
  1862. hsotg->eps_out[0]->dir_in = dir_in;
  1863. hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
  1864. dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
  1865. }
  1866. static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
  1867. u32 epctl_reg)
  1868. {
  1869. u32 ctrl;
  1870. ctrl = dwc2_readl(hsotg, epctl_reg);
  1871. if (ctrl & DXEPCTL_EOFRNUM)
  1872. ctrl |= DXEPCTL_SETEVENFR;
  1873. else
  1874. ctrl |= DXEPCTL_SETODDFR;
  1875. dwc2_writel(hsotg, ctrl, epctl_reg);
  1876. }
  1877. /*
  1878. * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
  1879. * @hs_ep - The endpoint on which transfer went
  1880. *
  1881. * Iterate over endpoints descriptor chain and get info on bytes remained
  1882. * in DMA descriptors after transfer has completed. Used for non isoc EPs.
  1883. */
  1884. static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
  1885. {
  1886. const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
  1887. struct dwc2_hsotg *hsotg = hs_ep->parent;
  1888. unsigned int bytes_rem = 0;
  1889. unsigned int bytes_rem_correction = 0;
  1890. struct dwc2_dma_desc *desc = hs_ep->desc_list;
  1891. int i;
  1892. u32 status;
  1893. u32 mps = hs_ep->ep.maxpacket;
  1894. int dir_in = hs_ep->dir_in;
  1895. if (!desc)
  1896. return -EINVAL;
  1897. /* Interrupt OUT EP with mps not multiple of 4 */
  1898. if (hs_ep->index)
  1899. if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
  1900. bytes_rem_correction = 4 - (mps % 4);
  1901. for (i = 0; i < hs_ep->desc_count; ++i) {
  1902. status = desc->status;
  1903. bytes_rem += status & DEV_DMA_NBYTES_MASK;
  1904. bytes_rem -= bytes_rem_correction;
  1905. if (status & DEV_DMA_STS_MASK)
  1906. dev_err(hsotg->dev, "descriptor %d closed with %x\n",
  1907. i, status & DEV_DMA_STS_MASK);
  1908. if (status & DEV_DMA_L)
  1909. break;
  1910. desc++;
  1911. }
  1912. return bytes_rem;
  1913. }
  1914. /**
  1915. * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
  1916. * @hsotg: The device instance
  1917. * @epnum: The endpoint received from
  1918. *
  1919. * The RXFIFO has delivered an OutDone event, which means that the data
  1920. * transfer for an OUT endpoint has been completed, either by a short
  1921. * packet or by the finish of a transfer.
  1922. */
  1923. static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
  1924. {
  1925. u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
  1926. struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
  1927. struct dwc2_hsotg_req *hs_req = hs_ep->req;
  1928. struct usb_request *req = &hs_req->req;
  1929. unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
  1930. int result = 0;
  1931. if (!hs_req) {
  1932. dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
  1933. return;
  1934. }
  1935. if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
  1936. dev_dbg(hsotg->dev, "zlp packet received\n");
  1937. dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
  1938. dwc2_hsotg_enqueue_setup(hsotg);
  1939. return;
  1940. }
  1941. if (using_desc_dma(hsotg))
  1942. size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
  1943. if (using_dma(hsotg)) {
  1944. unsigned int size_done;
  1945. /*
  1946. * Calculate the size of the transfer by checking how much
  1947. * is left in the endpoint size register and then working it
  1948. * out from the amount we loaded for the transfer.
  1949. *
  1950. * We need to do this as DMA pointers are always 32bit aligned
  1951. * so may overshoot/undershoot the transfer.
  1952. */
  1953. size_done = hs_ep->size_loaded - size_left;
  1954. size_done += hs_ep->last_load;
  1955. req->actual = size_done;
  1956. }
  1957. /* if there is more request to do, schedule new transfer */
  1958. if (req->actual < req->length && size_left == 0) {
  1959. dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
  1960. return;
  1961. }
  1962. if (req->actual < req->length && req->short_not_ok) {
  1963. dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
  1964. __func__, req->actual, req->length);
  1965. /*
  1966. * todo - what should we return here? there's no one else
  1967. * even bothering to check the status.
  1968. */
  1969. }
  1970. /* DDMA IN status phase will start from StsPhseRcvd interrupt */
  1971. if (!using_desc_dma(hsotg) && epnum == 0 &&
  1972. hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
  1973. /* Move to STATUS IN */
  1974. dwc2_hsotg_ep0_zlp(hsotg, true);
  1975. return;
  1976. }
  1977. /*
  1978. * Slave mode OUT transfers do not go through XferComplete so
  1979. * adjust the ISOC parity here.
  1980. */
  1981. if (!using_dma(hsotg)) {
  1982. if (hs_ep->isochronous && hs_ep->interval == 1)
  1983. dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
  1984. else if (hs_ep->isochronous && hs_ep->interval > 1)
  1985. dwc2_gadget_incr_frame_num(hs_ep);
  1986. }
  1987. dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
  1988. }
  1989. /**
  1990. * dwc2_hsotg_handle_rx - RX FIFO has data
  1991. * @hsotg: The device instance
  1992. *
  1993. * The IRQ handler has detected that the RX FIFO has some data in it
  1994. * that requires processing, so find out what is in there and do the
  1995. * appropriate read.
  1996. *
  1997. * The RXFIFO is a true FIFO, the packets coming out are still in packet
  1998. * chunks, so if you have x packets received on an endpoint you'll get x
  1999. * FIFO events delivered, each with a packet's worth of data in it.
  2000. *
  2001. * When using DMA, we should not be processing events from the RXFIFO
  2002. * as the actual data should be sent to the memory directly and we turn
  2003. * on the completion interrupts to get notifications of transfer completion.
  2004. */
  2005. static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
  2006. {
  2007. u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
  2008. u32 epnum, status, size;
  2009. WARN_ON(using_dma(hsotg));
  2010. epnum = grxstsr & GRXSTS_EPNUM_MASK;
  2011. status = grxstsr & GRXSTS_PKTSTS_MASK;
  2012. size = grxstsr & GRXSTS_BYTECNT_MASK;
  2013. size >>= GRXSTS_BYTECNT_SHIFT;
  2014. dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
  2015. __func__, grxstsr, size, epnum);
  2016. switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
  2017. case GRXSTS_PKTSTS_GLOBALOUTNAK:
  2018. dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
  2019. break;
  2020. case GRXSTS_PKTSTS_OUTDONE:
  2021. dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
  2022. dwc2_hsotg_read_frameno(hsotg));
  2023. if (!using_dma(hsotg))
  2024. dwc2_hsotg_handle_outdone(hsotg, epnum);
  2025. break;
  2026. case GRXSTS_PKTSTS_SETUPDONE:
  2027. dev_dbg(hsotg->dev,
  2028. "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
  2029. dwc2_hsotg_read_frameno(hsotg),
  2030. dwc2_readl(hsotg, DOEPCTL(0)));
  2031. /*
  2032. * Call dwc2_hsotg_handle_outdone here if it was not called from
  2033. * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
  2034. * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
  2035. */
  2036. if (hsotg->ep0_state == DWC2_EP0_SETUP)
  2037. dwc2_hsotg_handle_outdone(hsotg, epnum);
  2038. break;
  2039. case GRXSTS_PKTSTS_OUTRX:
  2040. dwc2_hsotg_rx_data(hsotg, epnum, size);
  2041. break;
  2042. case GRXSTS_PKTSTS_SETUPRX:
  2043. dev_dbg(hsotg->dev,
  2044. "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
  2045. dwc2_hsotg_read_frameno(hsotg),
  2046. dwc2_readl(hsotg, DOEPCTL(0)));
  2047. WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
  2048. dwc2_hsotg_rx_data(hsotg, epnum, size);
  2049. break;
  2050. default:
  2051. dev_warn(hsotg->dev, "%s: unknown status %08x\n",
  2052. __func__, grxstsr);
  2053. dwc2_hsotg_dump(hsotg);
  2054. break;
  2055. }
  2056. }
  2057. /**
  2058. * dwc2_hsotg_ep0_mps - turn max packet size into register setting
  2059. * @mps: The maximum packet size in bytes.
  2060. */
  2061. static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
  2062. {
  2063. switch (mps) {
  2064. case 64:
  2065. return D0EPCTL_MPS_64;
  2066. case 32:
  2067. return D0EPCTL_MPS_32;
  2068. case 16:
  2069. return D0EPCTL_MPS_16;
  2070. case 8:
  2071. return D0EPCTL_MPS_8;
  2072. }
  2073. /* bad max packet size, warn and return invalid result */
  2074. WARN_ON(1);
  2075. return (u32)-1;
  2076. }
  2077. /**
  2078. * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
  2079. * @hsotg: The driver state.
  2080. * @ep: The index number of the endpoint
  2081. * @mps: The maximum packet size in bytes
  2082. * @mc: The multicount value
  2083. * @dir_in: True if direction is in.
  2084. *
  2085. * Configure the maximum packet size for the given endpoint, updating
  2086. * the hardware control registers to reflect this.
  2087. */
  2088. static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
  2089. unsigned int ep, unsigned int mps,
  2090. unsigned int mc, unsigned int dir_in)
  2091. {
  2092. struct dwc2_hsotg_ep *hs_ep;
  2093. u32 reg;
  2094. hs_ep = index_to_ep(hsotg, ep, dir_in);
  2095. if (!hs_ep)
  2096. return;
  2097. if (ep == 0) {
  2098. u32 mps_bytes = mps;
  2099. /* EP0 is a special case */
  2100. mps = dwc2_hsotg_ep0_mps(mps_bytes);
  2101. if (mps > 3)
  2102. goto bad_mps;
  2103. hs_ep->ep.maxpacket = mps_bytes;
  2104. hs_ep->mc = 1;
  2105. } else {
  2106. if (mps > 1024)
  2107. goto bad_mps;
  2108. hs_ep->mc = mc;
  2109. if (mc > 3)
  2110. goto bad_mps;
  2111. hs_ep->ep.maxpacket = mps;
  2112. }
  2113. if (dir_in) {
  2114. reg = dwc2_readl(hsotg, DIEPCTL(ep));
  2115. reg &= ~DXEPCTL_MPS_MASK;
  2116. reg |= mps;
  2117. dwc2_writel(hsotg, reg, DIEPCTL(ep));
  2118. } else {
  2119. reg = dwc2_readl(hsotg, DOEPCTL(ep));
  2120. reg &= ~DXEPCTL_MPS_MASK;
  2121. reg |= mps;
  2122. dwc2_writel(hsotg, reg, DOEPCTL(ep));
  2123. }
  2124. return;
  2125. bad_mps:
  2126. dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
  2127. }
  2128. /**
  2129. * dwc2_hsotg_txfifo_flush - flush Tx FIFO
  2130. * @hsotg: The driver state
  2131. * @idx: The index for the endpoint (0..15)
  2132. */
  2133. static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
  2134. {
  2135. dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
  2136. GRSTCTL);
  2137. /* wait until the fifo is flushed */
  2138. if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
  2139. dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
  2140. __func__);
  2141. }
  2142. /**
  2143. * dwc2_hsotg_trytx - check to see if anything needs transmitting
  2144. * @hsotg: The driver state
  2145. * @hs_ep: The driver endpoint to check.
  2146. *
  2147. * Check to see if there is a request that has data to send, and if so
  2148. * make an attempt to write data into the FIFO.
  2149. */
  2150. static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
  2151. struct dwc2_hsotg_ep *hs_ep)
  2152. {
  2153. struct dwc2_hsotg_req *hs_req = hs_ep->req;
  2154. if (!hs_ep->dir_in || !hs_req) {
  2155. /**
  2156. * if request is not enqueued, we disable interrupts
  2157. * for endpoints, excepting ep0
  2158. */
  2159. if (hs_ep->index != 0)
  2160. dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
  2161. hs_ep->dir_in, 0);
  2162. return 0;
  2163. }
  2164. if (hs_req->req.actual < hs_req->req.length) {
  2165. dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
  2166. hs_ep->index);
  2167. return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
  2168. }
  2169. return 0;
  2170. }
  2171. /**
  2172. * dwc2_hsotg_complete_in - complete IN transfer
  2173. * @hsotg: The device state.
  2174. * @hs_ep: The endpoint that has just completed.
  2175. *
  2176. * An IN transfer has been completed, update the transfer's state and then
  2177. * call the relevant completion routines.
  2178. */
  2179. static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
  2180. struct dwc2_hsotg_ep *hs_ep)
  2181. {
  2182. struct dwc2_hsotg_req *hs_req = hs_ep->req;
  2183. u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
  2184. int size_left, size_done;
  2185. if (!hs_req) {
  2186. dev_dbg(hsotg->dev, "XferCompl but no req\n");
  2187. return;
  2188. }
  2189. /* Finish ZLP handling for IN EP0 transactions */
  2190. if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
  2191. dev_dbg(hsotg->dev, "zlp packet sent\n");
  2192. /*
  2193. * While send zlp for DWC2_EP0_STATUS_IN EP direction was
  2194. * changed to IN. Change back to complete OUT transfer request
  2195. */
  2196. hs_ep->dir_in = 0;
  2197. dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
  2198. if (hsotg->test_mode) {
  2199. int ret;
  2200. ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
  2201. if (ret < 0) {
  2202. dev_dbg(hsotg->dev, "Invalid Test #%d\n",
  2203. hsotg->test_mode);
  2204. dwc2_hsotg_stall_ep0(hsotg);
  2205. return;
  2206. }
  2207. }
  2208. dwc2_hsotg_enqueue_setup(hsotg);
  2209. return;
  2210. }
  2211. /*
  2212. * Calculate the size of the transfer by checking how much is left
  2213. * in the endpoint size register and then working it out from
  2214. * the amount we loaded for the transfer.
  2215. *
  2216. * We do this even for DMA, as the transfer may have incremented
  2217. * past the end of the buffer (DMA transfers are always 32bit
  2218. * aligned).
  2219. */
  2220. if (using_desc_dma(hsotg)) {
  2221. size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
  2222. if (size_left < 0)
  2223. dev_err(hsotg->dev, "error parsing DDMA results %d\n",
  2224. size_left);
  2225. } else {
  2226. size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
  2227. }
  2228. size_done = hs_ep->size_loaded - size_left;
  2229. size_done += hs_ep->last_load;
  2230. if (hs_req->req.actual != size_done)
  2231. dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
  2232. __func__, hs_req->req.actual, size_done);
  2233. hs_req->req.actual = size_done;
  2234. dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
  2235. hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
  2236. if (!size_left && hs_req->req.actual < hs_req->req.length) {
  2237. dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
  2238. dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
  2239. return;
  2240. }
  2241. /* Zlp for all endpoints, for ep0 only in DATA IN stage */
  2242. if (hs_ep->send_zlp) {
  2243. dwc2_hsotg_program_zlp(hsotg, hs_ep);
  2244. hs_ep->send_zlp = 0;
  2245. /* transfer will be completed on next complete interrupt */
  2246. return;
  2247. }
  2248. if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
  2249. /* Move to STATUS OUT */
  2250. dwc2_hsotg_ep0_zlp(hsotg, false);
  2251. return;
  2252. }
  2253. dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
  2254. }
  2255. /**
  2256. * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
  2257. * @hsotg: The device state.
  2258. * @idx: Index of ep.
  2259. * @dir_in: Endpoint direction 1-in 0-out.
  2260. *
  2261. * Reads for endpoint with given index and direction, by masking
  2262. * epint_reg with coresponding mask.
  2263. */
  2264. static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
  2265. unsigned int idx, int dir_in)
  2266. {
  2267. u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
  2268. u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
  2269. u32 ints;
  2270. u32 mask;
  2271. u32 diepempmsk;
  2272. mask = dwc2_readl(hsotg, epmsk_reg);
  2273. diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
  2274. mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
  2275. mask |= DXEPINT_SETUP_RCVD;
  2276. ints = dwc2_readl(hsotg, epint_reg);
  2277. ints &= mask;
  2278. return ints;
  2279. }
  2280. /**
  2281. * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
  2282. * @hs_ep: The endpoint on which interrupt is asserted.
  2283. *
  2284. * This interrupt indicates that the endpoint has been disabled per the
  2285. * application's request.
  2286. *
  2287. * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
  2288. * in case of ISOC completes current request.
  2289. *
  2290. * For ISOC-OUT endpoints completes expired requests. If there is remaining
  2291. * request starts it.
  2292. */
  2293. static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
  2294. {
  2295. struct dwc2_hsotg *hsotg = hs_ep->parent;
  2296. struct dwc2_hsotg_req *hs_req;
  2297. unsigned char idx = hs_ep->index;
  2298. int dir_in = hs_ep->dir_in;
  2299. u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
  2300. int dctl = dwc2_readl(hsotg, DCTL);
  2301. dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
  2302. if (dir_in) {
  2303. int epctl = dwc2_readl(hsotg, epctl_reg);
  2304. dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
  2305. if (hs_ep->isochronous) {
  2306. dwc2_hsotg_complete_in(hsotg, hs_ep);
  2307. return;
  2308. }
  2309. if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
  2310. int dctl = dwc2_readl(hsotg, DCTL);
  2311. dctl |= DCTL_CGNPINNAK;
  2312. dwc2_writel(hsotg, dctl, DCTL);
  2313. }
  2314. return;
  2315. }
  2316. if (dctl & DCTL_GOUTNAKSTS) {
  2317. dctl |= DCTL_CGOUTNAK;
  2318. dwc2_writel(hsotg, dctl, DCTL);
  2319. }
  2320. if (!hs_ep->isochronous)
  2321. return;
  2322. if (list_empty(&hs_ep->queue)) {
  2323. dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
  2324. __func__, hs_ep);
  2325. return;
  2326. }
  2327. do {
  2328. hs_req = get_ep_head(hs_ep);
  2329. if (hs_req)
  2330. dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
  2331. -ENODATA);
  2332. dwc2_gadget_incr_frame_num(hs_ep);
  2333. /* Update current frame number value. */
  2334. hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
  2335. } while (dwc2_gadget_target_frame_elapsed(hs_ep));
  2336. dwc2_gadget_start_next_request(hs_ep);
  2337. }
  2338. /**
  2339. * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
  2340. * @ep: The endpoint on which interrupt is asserted.
  2341. *
  2342. * This is starting point for ISOC-OUT transfer, synchronization done with
  2343. * first out token received from host while corresponding EP is disabled.
  2344. *
  2345. * Device does not know initial frame in which out token will come. For this
  2346. * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
  2347. * getting this interrupt SW starts calculation for next transfer frame.
  2348. */
  2349. static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
  2350. {
  2351. struct dwc2_hsotg *hsotg = ep->parent;
  2352. int dir_in = ep->dir_in;
  2353. u32 doepmsk;
  2354. if (dir_in || !ep->isochronous)
  2355. return;
  2356. if (using_desc_dma(hsotg)) {
  2357. if (ep->target_frame == TARGET_FRAME_INITIAL) {
  2358. /* Start first ISO Out */
  2359. ep->target_frame = hsotg->frame_number;
  2360. dwc2_gadget_start_isoc_ddma(ep);
  2361. }
  2362. return;
  2363. }
  2364. if (ep->interval > 1 &&
  2365. ep->target_frame == TARGET_FRAME_INITIAL) {
  2366. u32 ctrl;
  2367. ep->target_frame = hsotg->frame_number;
  2368. dwc2_gadget_incr_frame_num(ep);
  2369. ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
  2370. if (ep->target_frame & 0x1)
  2371. ctrl |= DXEPCTL_SETODDFR;
  2372. else
  2373. ctrl |= DXEPCTL_SETEVENFR;
  2374. dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
  2375. }
  2376. dwc2_gadget_start_next_request(ep);
  2377. doepmsk = dwc2_readl(hsotg, DOEPMSK);
  2378. doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
  2379. dwc2_writel(hsotg, doepmsk, DOEPMSK);
  2380. }
  2381. /**
  2382. * dwc2_gadget_handle_nak - handle NAK interrupt
  2383. * @hs_ep: The endpoint on which interrupt is asserted.
  2384. *
  2385. * This is starting point for ISOC-IN transfer, synchronization done with
  2386. * first IN token received from host while corresponding EP is disabled.
  2387. *
  2388. * Device does not know when first one token will arrive from host. On first
  2389. * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
  2390. * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
  2391. * sent in response to that as there was no data in FIFO. SW is basing on this
  2392. * interrupt to obtain frame in which token has come and then based on the
  2393. * interval calculates next frame for transfer.
  2394. */
  2395. static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
  2396. {
  2397. struct dwc2_hsotg *hsotg = hs_ep->parent;
  2398. int dir_in = hs_ep->dir_in;
  2399. if (!dir_in || !hs_ep->isochronous)
  2400. return;
  2401. if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
  2402. if (using_desc_dma(hsotg)) {
  2403. hs_ep->target_frame = hsotg->frame_number;
  2404. dwc2_gadget_incr_frame_num(hs_ep);
  2405. dwc2_gadget_start_isoc_ddma(hs_ep);
  2406. return;
  2407. }
  2408. hs_ep->target_frame = hsotg->frame_number;
  2409. if (hs_ep->interval > 1) {
  2410. u32 ctrl = dwc2_readl(hsotg,
  2411. DIEPCTL(hs_ep->index));
  2412. if (hs_ep->target_frame & 0x1)
  2413. ctrl |= DXEPCTL_SETODDFR;
  2414. else
  2415. ctrl |= DXEPCTL_SETEVENFR;
  2416. dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
  2417. }
  2418. dwc2_hsotg_complete_request(hsotg, hs_ep,
  2419. get_ep_head(hs_ep), 0);
  2420. }
  2421. if (!using_desc_dma(hsotg))
  2422. dwc2_gadget_incr_frame_num(hs_ep);
  2423. }
  2424. /**
  2425. * dwc2_hsotg_epint - handle an in/out endpoint interrupt
  2426. * @hsotg: The driver state
  2427. * @idx: The index for the endpoint (0..15)
  2428. * @dir_in: Set if this is an IN endpoint
  2429. *
  2430. * Process and clear any interrupt pending for an individual endpoint
  2431. */
  2432. static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
  2433. int dir_in)
  2434. {
  2435. struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
  2436. u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
  2437. u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
  2438. u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
  2439. u32 ints;
  2440. u32 ctrl;
  2441. ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
  2442. ctrl = dwc2_readl(hsotg, epctl_reg);
  2443. /* Clear endpoint interrupts */
  2444. dwc2_writel(hsotg, ints, epint_reg);
  2445. if (!hs_ep) {
  2446. dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
  2447. __func__, idx, dir_in ? "in" : "out");
  2448. return;
  2449. }
  2450. dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
  2451. __func__, idx, dir_in ? "in" : "out", ints);
  2452. /* Don't process XferCompl interrupt if it is a setup packet */
  2453. if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
  2454. ints &= ~DXEPINT_XFERCOMPL;
  2455. /*
  2456. * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
  2457. * stage and xfercomplete was generated without SETUP phase done
  2458. * interrupt. SW should parse received setup packet only after host's
  2459. * exit from setup phase of control transfer.
  2460. */
  2461. if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
  2462. hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
  2463. ints &= ~DXEPINT_XFERCOMPL;
  2464. if (ints & DXEPINT_XFERCOMPL) {
  2465. dev_dbg(hsotg->dev,
  2466. "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
  2467. __func__, dwc2_readl(hsotg, epctl_reg),
  2468. dwc2_readl(hsotg, epsiz_reg));
  2469. /* In DDMA handle isochronous requests separately */
  2470. if (using_desc_dma(hsotg) && hs_ep->isochronous) {
  2471. /* XferCompl set along with BNA */
  2472. if (!(ints & DXEPINT_BNAINTR))
  2473. dwc2_gadget_complete_isoc_request_ddma(hs_ep);
  2474. } else if (dir_in) {
  2475. /*
  2476. * We get OutDone from the FIFO, so we only
  2477. * need to look at completing IN requests here
  2478. * if operating slave mode
  2479. */
  2480. if (hs_ep->isochronous && hs_ep->interval > 1)
  2481. dwc2_gadget_incr_frame_num(hs_ep);
  2482. dwc2_hsotg_complete_in(hsotg, hs_ep);
  2483. if (ints & DXEPINT_NAKINTRPT)
  2484. ints &= ~DXEPINT_NAKINTRPT;
  2485. if (idx == 0 && !hs_ep->req)
  2486. dwc2_hsotg_enqueue_setup(hsotg);
  2487. } else if (using_dma(hsotg)) {
  2488. /*
  2489. * We're using DMA, we need to fire an OutDone here
  2490. * as we ignore the RXFIFO.
  2491. */
  2492. if (hs_ep->isochronous && hs_ep->interval > 1)
  2493. dwc2_gadget_incr_frame_num(hs_ep);
  2494. dwc2_hsotg_handle_outdone(hsotg, idx);
  2495. }
  2496. }
  2497. if (ints & DXEPINT_EPDISBLD)
  2498. dwc2_gadget_handle_ep_disabled(hs_ep);
  2499. if (ints & DXEPINT_OUTTKNEPDIS)
  2500. dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
  2501. if (ints & DXEPINT_NAKINTRPT)
  2502. dwc2_gadget_handle_nak(hs_ep);
  2503. if (ints & DXEPINT_AHBERR)
  2504. dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
  2505. if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
  2506. dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
  2507. if (using_dma(hsotg) && idx == 0) {
  2508. /*
  2509. * this is the notification we've received a
  2510. * setup packet. In non-DMA mode we'd get this
  2511. * from the RXFIFO, instead we need to process
  2512. * the setup here.
  2513. */
  2514. if (dir_in)
  2515. WARN_ON_ONCE(1);
  2516. else
  2517. dwc2_hsotg_handle_outdone(hsotg, 0);
  2518. }
  2519. }
  2520. if (ints & DXEPINT_STSPHSERCVD) {
  2521. dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
  2522. /* Safety check EP0 state when STSPHSERCVD asserted */
  2523. if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
  2524. /* Move to STATUS IN for DDMA */
  2525. if (using_desc_dma(hsotg))
  2526. dwc2_hsotg_ep0_zlp(hsotg, true);
  2527. }
  2528. }
  2529. if (ints & DXEPINT_BACK2BACKSETUP)
  2530. dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
  2531. if (ints & DXEPINT_BNAINTR) {
  2532. dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
  2533. if (hs_ep->isochronous)
  2534. dwc2_gadget_handle_isoc_bna(hs_ep);
  2535. }
  2536. if (dir_in && !hs_ep->isochronous) {
  2537. /* not sure if this is important, but we'll clear it anyway */
  2538. if (ints & DXEPINT_INTKNTXFEMP) {
  2539. dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
  2540. __func__, idx);
  2541. }
  2542. /* this probably means something bad is happening */
  2543. if (ints & DXEPINT_INTKNEPMIS) {
  2544. dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
  2545. __func__, idx);
  2546. }
  2547. /* FIFO has space or is empty (see GAHBCFG) */
  2548. if (hsotg->dedicated_fifos &&
  2549. ints & DXEPINT_TXFEMP) {
  2550. dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
  2551. __func__, idx);
  2552. if (!using_dma(hsotg))
  2553. dwc2_hsotg_trytx(hsotg, hs_ep);
  2554. }
  2555. }
  2556. }
  2557. /**
  2558. * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
  2559. * @hsotg: The device state.
  2560. *
  2561. * Handle updating the device settings after the enumeration phase has
  2562. * been completed.
  2563. */
  2564. static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
  2565. {
  2566. u32 dsts = dwc2_readl(hsotg, DSTS);
  2567. int ep0_mps = 0, ep_mps = 8;
  2568. /*
  2569. * This should signal the finish of the enumeration phase
  2570. * of the USB handshaking, so we should now know what rate
  2571. * we connected at.
  2572. */
  2573. dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
  2574. /*
  2575. * note, since we're limited by the size of transfer on EP0, and
  2576. * it seems IN transfers must be a even number of packets we do
  2577. * not advertise a 64byte MPS on EP0.
  2578. */
  2579. /* catch both EnumSpd_FS and EnumSpd_FS48 */
  2580. switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
  2581. case DSTS_ENUMSPD_FS:
  2582. case DSTS_ENUMSPD_FS48:
  2583. hsotg->gadget.speed = USB_SPEED_FULL;
  2584. ep0_mps = EP0_MPS_LIMIT;
  2585. ep_mps = 1023;
  2586. break;
  2587. case DSTS_ENUMSPD_HS:
  2588. hsotg->gadget.speed = USB_SPEED_HIGH;
  2589. ep0_mps = EP0_MPS_LIMIT;
  2590. ep_mps = 1024;
  2591. break;
  2592. case DSTS_ENUMSPD_LS:
  2593. hsotg->gadget.speed = USB_SPEED_LOW;
  2594. ep0_mps = 8;
  2595. ep_mps = 8;
  2596. /*
  2597. * note, we don't actually support LS in this driver at the
  2598. * moment, and the documentation seems to imply that it isn't
  2599. * supported by the PHYs on some of the devices.
  2600. */
  2601. break;
  2602. }
  2603. dev_info(hsotg->dev, "new device is %s\n",
  2604. usb_speed_string(hsotg->gadget.speed));
  2605. /*
  2606. * we should now know the maximum packet size for an
  2607. * endpoint, so set the endpoints to a default value.
  2608. */
  2609. if (ep0_mps) {
  2610. int i;
  2611. /* Initialize ep0 for both in and out directions */
  2612. dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
  2613. dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
  2614. for (i = 1; i < hsotg->num_of_eps; i++) {
  2615. if (hsotg->eps_in[i])
  2616. dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
  2617. 0, 1);
  2618. if (hsotg->eps_out[i])
  2619. dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
  2620. 0, 0);
  2621. }
  2622. }
  2623. /* ensure after enumeration our EP0 is active */
  2624. dwc2_hsotg_enqueue_setup(hsotg);
  2625. dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
  2626. dwc2_readl(hsotg, DIEPCTL0),
  2627. dwc2_readl(hsotg, DOEPCTL0));
  2628. }
  2629. /**
  2630. * kill_all_requests - remove all requests from the endpoint's queue
  2631. * @hsotg: The device state.
  2632. * @ep: The endpoint the requests may be on.
  2633. * @result: The result code to use.
  2634. *
  2635. * Go through the requests on the given endpoint and mark them
  2636. * completed with the given result code.
  2637. */
  2638. static void kill_all_requests(struct dwc2_hsotg *hsotg,
  2639. struct dwc2_hsotg_ep *ep,
  2640. int result)
  2641. {
  2642. struct dwc2_hsotg_req *req, *treq;
  2643. unsigned int size;
  2644. ep->req = NULL;
  2645. list_for_each_entry_safe(req, treq, &ep->queue, queue)
  2646. dwc2_hsotg_complete_request(hsotg, ep, req,
  2647. result);
  2648. if (!hsotg->dedicated_fifos)
  2649. return;
  2650. size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
  2651. if (size < ep->fifo_size)
  2652. dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
  2653. }
  2654. /**
  2655. * dwc2_hsotg_disconnect - disconnect service
  2656. * @hsotg: The device state.
  2657. *
  2658. * The device has been disconnected. Remove all current
  2659. * transactions and signal the gadget driver that this
  2660. * has happened.
  2661. */
  2662. void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
  2663. {
  2664. unsigned int ep;
  2665. if (!hsotg->connected)
  2666. return;
  2667. hsotg->connected = 0;
  2668. hsotg->test_mode = 0;
  2669. /* all endpoints should be shutdown */
  2670. for (ep = 0; ep < hsotg->num_of_eps; ep++) {
  2671. if (hsotg->eps_in[ep])
  2672. kill_all_requests(hsotg, hsotg->eps_in[ep],
  2673. -ESHUTDOWN);
  2674. if (hsotg->eps_out[ep])
  2675. kill_all_requests(hsotg, hsotg->eps_out[ep],
  2676. -ESHUTDOWN);
  2677. }
  2678. call_gadget(hsotg, disconnect);
  2679. hsotg->lx_state = DWC2_L3;
  2680. usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
  2681. }
  2682. /**
  2683. * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
  2684. * @hsotg: The device state:
  2685. * @periodic: True if this is a periodic FIFO interrupt
  2686. */
  2687. static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
  2688. {
  2689. struct dwc2_hsotg_ep *ep;
  2690. int epno, ret;
  2691. /* look through for any more data to transmit */
  2692. for (epno = 0; epno < hsotg->num_of_eps; epno++) {
  2693. ep = index_to_ep(hsotg, epno, 1);
  2694. if (!ep)
  2695. continue;
  2696. if (!ep->dir_in)
  2697. continue;
  2698. if ((periodic && !ep->periodic) ||
  2699. (!periodic && ep->periodic))
  2700. continue;
  2701. ret = dwc2_hsotg_trytx(hsotg, ep);
  2702. if (ret < 0)
  2703. break;
  2704. }
  2705. }
  2706. /* IRQ flags which will trigger a retry around the IRQ loop */
  2707. #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
  2708. GINTSTS_PTXFEMP | \
  2709. GINTSTS_RXFLVL)
  2710. static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
  2711. /**
  2712. * dwc2_hsotg_core_init - issue softreset to the core
  2713. * @hsotg: The device state
  2714. * @is_usb_reset: Usb resetting flag
  2715. *
  2716. * Issue a soft reset to the core, and await the core finishing it.
  2717. */
  2718. void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
  2719. bool is_usb_reset)
  2720. {
  2721. u32 intmsk;
  2722. u32 val;
  2723. u32 usbcfg;
  2724. u32 dcfg = 0;
  2725. int ep;
  2726. /* Kill any ep0 requests as controller will be reinitialized */
  2727. kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
  2728. if (!is_usb_reset) {
  2729. if (dwc2_core_reset(hsotg, true))
  2730. return;
  2731. } else {
  2732. /* all endpoints should be shutdown */
  2733. for (ep = 1; ep < hsotg->num_of_eps; ep++) {
  2734. if (hsotg->eps_in[ep])
  2735. dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
  2736. if (hsotg->eps_out[ep])
  2737. dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
  2738. }
  2739. }
  2740. /*
  2741. * we must now enable ep0 ready for host detection and then
  2742. * set configuration.
  2743. */
  2744. /* keep other bits untouched (so e.g. forced modes are not lost) */
  2745. usbcfg = dwc2_readl(hsotg, GUSBCFG);
  2746. usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
  2747. GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
  2748. if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
  2749. (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
  2750. hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
  2751. /* FS/LS Dedicated Transceiver Interface */
  2752. usbcfg |= GUSBCFG_PHYSEL;
  2753. } else {
  2754. /* set the PLL on, remove the HNP/SRP and set the PHY */
  2755. val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
  2756. usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
  2757. (val << GUSBCFG_USBTRDTIM_SHIFT);
  2758. }
  2759. dwc2_writel(hsotg, usbcfg, GUSBCFG);
  2760. dwc2_hsotg_init_fifo(hsotg);
  2761. if (!is_usb_reset)
  2762. dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
  2763. dcfg |= DCFG_EPMISCNT(1);
  2764. switch (hsotg->params.speed) {
  2765. case DWC2_SPEED_PARAM_LOW:
  2766. dcfg |= DCFG_DEVSPD_LS;
  2767. break;
  2768. case DWC2_SPEED_PARAM_FULL:
  2769. if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
  2770. dcfg |= DCFG_DEVSPD_FS48;
  2771. else
  2772. dcfg |= DCFG_DEVSPD_FS;
  2773. break;
  2774. default:
  2775. dcfg |= DCFG_DEVSPD_HS;
  2776. }
  2777. if (hsotg->params.ipg_isoc_en)
  2778. dcfg |= DCFG_IPG_ISOC_SUPPORDED;
  2779. dwc2_writel(hsotg, dcfg, DCFG);
  2780. /* Clear any pending OTG interrupts */
  2781. dwc2_writel(hsotg, 0xffffffff, GOTGINT);
  2782. /* Clear any pending interrupts */
  2783. dwc2_writel(hsotg, 0xffffffff, GINTSTS);
  2784. intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
  2785. GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
  2786. GINTSTS_USBRST | GINTSTS_RESETDET |
  2787. GINTSTS_ENUMDONE | GINTSTS_OTGINT |
  2788. GINTSTS_USBSUSP | GINTSTS_WKUPINT |
  2789. GINTSTS_LPMTRANRCVD;
  2790. if (!using_desc_dma(hsotg))
  2791. intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
  2792. if (!hsotg->params.external_id_pin_ctl)
  2793. intmsk |= GINTSTS_CONIDSTSCHNG;
  2794. dwc2_writel(hsotg, intmsk, GINTMSK);
  2795. if (using_dma(hsotg)) {
  2796. dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
  2797. hsotg->params.ahbcfg,
  2798. GAHBCFG);
  2799. /* Set DDMA mode support in the core if needed */
  2800. if (using_desc_dma(hsotg))
  2801. dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
  2802. } else {
  2803. dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
  2804. (GAHBCFG_NP_TXF_EMP_LVL |
  2805. GAHBCFG_P_TXF_EMP_LVL) : 0) |
  2806. GAHBCFG_GLBL_INTR_EN, GAHBCFG);
  2807. }
  2808. /*
  2809. * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
  2810. * when we have no data to transfer. Otherwise we get being flooded by
  2811. * interrupts.
  2812. */
  2813. dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
  2814. DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
  2815. DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
  2816. DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
  2817. DIEPMSK);
  2818. /*
  2819. * don't need XferCompl, we get that from RXFIFO in slave mode. In
  2820. * DMA mode we may need this and StsPhseRcvd.
  2821. */
  2822. dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
  2823. DOEPMSK_STSPHSERCVDMSK) : 0) |
  2824. DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
  2825. DOEPMSK_SETUPMSK,
  2826. DOEPMSK);
  2827. /* Enable BNA interrupt for DDMA */
  2828. if (using_desc_dma(hsotg)) {
  2829. dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
  2830. dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
  2831. }
  2832. dwc2_writel(hsotg, 0, DAINTMSK);
  2833. dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
  2834. dwc2_readl(hsotg, DIEPCTL0),
  2835. dwc2_readl(hsotg, DOEPCTL0));
  2836. /* enable in and out endpoint interrupts */
  2837. dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
  2838. /*
  2839. * Enable the RXFIFO when in slave mode, as this is how we collect
  2840. * the data. In DMA mode, we get events from the FIFO but also
  2841. * things we cannot process, so do not use it.
  2842. */
  2843. if (!using_dma(hsotg))
  2844. dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
  2845. /* Enable interrupts for EP0 in and out */
  2846. dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
  2847. dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
  2848. if (!is_usb_reset) {
  2849. dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
  2850. udelay(10); /* see openiboot */
  2851. dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
  2852. }
  2853. dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
  2854. /*
  2855. * DxEPCTL_USBActEp says RO in manual, but seems to be set by
  2856. * writing to the EPCTL register..
  2857. */
  2858. /* set to read 1 8byte packet */
  2859. dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
  2860. DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
  2861. dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
  2862. DXEPCTL_CNAK | DXEPCTL_EPENA |
  2863. DXEPCTL_USBACTEP,
  2864. DOEPCTL0);
  2865. /* enable, but don't activate EP0in */
  2866. dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
  2867. DXEPCTL_USBACTEP, DIEPCTL0);
  2868. /* clear global NAKs */
  2869. val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
  2870. if (!is_usb_reset)
  2871. val |= DCTL_SFTDISCON;
  2872. dwc2_set_bit(hsotg, DCTL, val);
  2873. /* configure the core to support LPM */
  2874. dwc2_gadget_init_lpm(hsotg);
  2875. /* must be at-least 3ms to allow bus to see disconnect */
  2876. mdelay(3);
  2877. hsotg->lx_state = DWC2_L0;
  2878. dwc2_hsotg_enqueue_setup(hsotg);
  2879. dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
  2880. dwc2_readl(hsotg, DIEPCTL0),
  2881. dwc2_readl(hsotg, DOEPCTL0));
  2882. }
  2883. static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
  2884. {
  2885. /* set the soft-disconnect bit */
  2886. dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
  2887. }
  2888. void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
  2889. {
  2890. /* remove the soft-disconnect and let's go */
  2891. dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
  2892. }
  2893. /**
  2894. * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
  2895. * @hsotg: The device state:
  2896. *
  2897. * This interrupt indicates one of the following conditions occurred while
  2898. * transmitting an ISOC transaction.
  2899. * - Corrupted IN Token for ISOC EP.
  2900. * - Packet not complete in FIFO.
  2901. *
  2902. * The following actions will be taken:
  2903. * - Determine the EP
  2904. * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
  2905. */
  2906. static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
  2907. {
  2908. struct dwc2_hsotg_ep *hs_ep;
  2909. u32 epctrl;
  2910. u32 daintmsk;
  2911. u32 idx;
  2912. dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
  2913. daintmsk = dwc2_readl(hsotg, DAINTMSK);
  2914. for (idx = 1; idx < hsotg->num_of_eps; idx++) {
  2915. hs_ep = hsotg->eps_in[idx];
  2916. /* Proceed only unmasked ISOC EPs */
  2917. if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
  2918. continue;
  2919. epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
  2920. if ((epctrl & DXEPCTL_EPENA) &&
  2921. dwc2_gadget_target_frame_elapsed(hs_ep)) {
  2922. epctrl |= DXEPCTL_SNAK;
  2923. epctrl |= DXEPCTL_EPDIS;
  2924. dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
  2925. }
  2926. }
  2927. /* Clear interrupt */
  2928. dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
  2929. }
  2930. /**
  2931. * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
  2932. * @hsotg: The device state:
  2933. *
  2934. * This interrupt indicates one of the following conditions occurred while
  2935. * transmitting an ISOC transaction.
  2936. * - Corrupted OUT Token for ISOC EP.
  2937. * - Packet not complete in FIFO.
  2938. *
  2939. * The following actions will be taken:
  2940. * - Determine the EP
  2941. * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
  2942. */
  2943. static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
  2944. {
  2945. u32 gintsts;
  2946. u32 gintmsk;
  2947. u32 daintmsk;
  2948. u32 epctrl;
  2949. struct dwc2_hsotg_ep *hs_ep;
  2950. int idx;
  2951. dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
  2952. daintmsk = dwc2_readl(hsotg, DAINTMSK);
  2953. daintmsk >>= DAINT_OUTEP_SHIFT;
  2954. for (idx = 1; idx < hsotg->num_of_eps; idx++) {
  2955. hs_ep = hsotg->eps_out[idx];
  2956. /* Proceed only unmasked ISOC EPs */
  2957. if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
  2958. continue;
  2959. epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
  2960. if ((epctrl & DXEPCTL_EPENA) &&
  2961. dwc2_gadget_target_frame_elapsed(hs_ep)) {
  2962. /* Unmask GOUTNAKEFF interrupt */
  2963. gintmsk = dwc2_readl(hsotg, GINTMSK);
  2964. gintmsk |= GINTSTS_GOUTNAKEFF;
  2965. dwc2_writel(hsotg, gintmsk, GINTMSK);
  2966. gintsts = dwc2_readl(hsotg, GINTSTS);
  2967. if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
  2968. dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
  2969. break;
  2970. }
  2971. }
  2972. }
  2973. /* Clear interrupt */
  2974. dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
  2975. }
  2976. /**
  2977. * dwc2_hsotg_irq - handle device interrupt
  2978. * @irq: The IRQ number triggered
  2979. * @pw: The pw value when registered the handler.
  2980. */
  2981. static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
  2982. {
  2983. struct dwc2_hsotg *hsotg = pw;
  2984. int retry_count = 8;
  2985. u32 gintsts;
  2986. u32 gintmsk;
  2987. if (!dwc2_is_device_mode(hsotg))
  2988. return IRQ_NONE;
  2989. spin_lock(&hsotg->lock);
  2990. irq_retry:
  2991. gintsts = dwc2_readl(hsotg, GINTSTS);
  2992. gintmsk = dwc2_readl(hsotg, GINTMSK);
  2993. dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
  2994. __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
  2995. gintsts &= gintmsk;
  2996. if (gintsts & GINTSTS_RESETDET) {
  2997. dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
  2998. dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
  2999. /* This event must be used only if controller is suspended */
  3000. if (hsotg->lx_state == DWC2_L2) {
  3001. dwc2_exit_partial_power_down(hsotg, true);
  3002. hsotg->lx_state = DWC2_L0;
  3003. }
  3004. }
  3005. if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
  3006. u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
  3007. u32 connected = hsotg->connected;
  3008. dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
  3009. dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
  3010. dwc2_readl(hsotg, GNPTXSTS));
  3011. dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
  3012. /* Report disconnection if it is not already done. */
  3013. dwc2_hsotg_disconnect(hsotg);
  3014. /* Reset device address to zero */
  3015. dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
  3016. if (usb_status & GOTGCTL_BSESVLD && connected)
  3017. dwc2_hsotg_core_init_disconnected(hsotg, true);
  3018. }
  3019. if (gintsts & GINTSTS_ENUMDONE) {
  3020. dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
  3021. dwc2_hsotg_irq_enumdone(hsotg);
  3022. }
  3023. if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
  3024. u32 daint = dwc2_readl(hsotg, DAINT);
  3025. u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
  3026. u32 daint_out, daint_in;
  3027. int ep;
  3028. daint &= daintmsk;
  3029. daint_out = daint >> DAINT_OUTEP_SHIFT;
  3030. daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
  3031. dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
  3032. for (ep = 0; ep < hsotg->num_of_eps && daint_out;
  3033. ep++, daint_out >>= 1) {
  3034. if (daint_out & 1)
  3035. dwc2_hsotg_epint(hsotg, ep, 0);
  3036. }
  3037. for (ep = 0; ep < hsotg->num_of_eps && daint_in;
  3038. ep++, daint_in >>= 1) {
  3039. if (daint_in & 1)
  3040. dwc2_hsotg_epint(hsotg, ep, 1);
  3041. }
  3042. }
  3043. /* check both FIFOs */
  3044. if (gintsts & GINTSTS_NPTXFEMP) {
  3045. dev_dbg(hsotg->dev, "NPTxFEmp\n");
  3046. /*
  3047. * Disable the interrupt to stop it happening again
  3048. * unless one of these endpoint routines decides that
  3049. * it needs re-enabling
  3050. */
  3051. dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
  3052. dwc2_hsotg_irq_fifoempty(hsotg, false);
  3053. }
  3054. if (gintsts & GINTSTS_PTXFEMP) {
  3055. dev_dbg(hsotg->dev, "PTxFEmp\n");
  3056. /* See note in GINTSTS_NPTxFEmp */
  3057. dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
  3058. dwc2_hsotg_irq_fifoempty(hsotg, true);
  3059. }
  3060. if (gintsts & GINTSTS_RXFLVL) {
  3061. /*
  3062. * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
  3063. * we need to retry dwc2_hsotg_handle_rx if this is still
  3064. * set.
  3065. */
  3066. dwc2_hsotg_handle_rx(hsotg);
  3067. }
  3068. if (gintsts & GINTSTS_ERLYSUSP) {
  3069. dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
  3070. dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
  3071. }
  3072. /*
  3073. * these next two seem to crop-up occasionally causing the core
  3074. * to shutdown the USB transfer, so try clearing them and logging
  3075. * the occurrence.
  3076. */
  3077. if (gintsts & GINTSTS_GOUTNAKEFF) {
  3078. u8 idx;
  3079. u32 epctrl;
  3080. u32 gintmsk;
  3081. u32 daintmsk;
  3082. struct dwc2_hsotg_ep *hs_ep;
  3083. daintmsk = dwc2_readl(hsotg, DAINTMSK);
  3084. daintmsk >>= DAINT_OUTEP_SHIFT;
  3085. /* Mask this interrupt */
  3086. gintmsk = dwc2_readl(hsotg, GINTMSK);
  3087. gintmsk &= ~GINTSTS_GOUTNAKEFF;
  3088. dwc2_writel(hsotg, gintmsk, GINTMSK);
  3089. dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
  3090. for (idx = 1; idx < hsotg->num_of_eps; idx++) {
  3091. hs_ep = hsotg->eps_out[idx];
  3092. /* Proceed only unmasked ISOC EPs */
  3093. if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
  3094. continue;
  3095. epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
  3096. if (epctrl & DXEPCTL_EPENA) {
  3097. epctrl |= DXEPCTL_SNAK;
  3098. epctrl |= DXEPCTL_EPDIS;
  3099. dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
  3100. }
  3101. }
  3102. /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
  3103. }
  3104. if (gintsts & GINTSTS_GINNAKEFF) {
  3105. dev_info(hsotg->dev, "GINNakEff triggered\n");
  3106. dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
  3107. dwc2_hsotg_dump(hsotg);
  3108. }
  3109. if (gintsts & GINTSTS_INCOMPL_SOIN)
  3110. dwc2_gadget_handle_incomplete_isoc_in(hsotg);
  3111. if (gintsts & GINTSTS_INCOMPL_SOOUT)
  3112. dwc2_gadget_handle_incomplete_isoc_out(hsotg);
  3113. /*
  3114. * if we've had fifo events, we should try and go around the
  3115. * loop again to see if there's any point in returning yet.
  3116. */
  3117. if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
  3118. goto irq_retry;
  3119. spin_unlock(&hsotg->lock);
  3120. return IRQ_HANDLED;
  3121. }
  3122. static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
  3123. struct dwc2_hsotg_ep *hs_ep)
  3124. {
  3125. u32 epctrl_reg;
  3126. u32 epint_reg;
  3127. epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
  3128. DOEPCTL(hs_ep->index);
  3129. epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
  3130. DOEPINT(hs_ep->index);
  3131. dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
  3132. hs_ep->name);
  3133. if (hs_ep->dir_in) {
  3134. if (hsotg->dedicated_fifos || hs_ep->periodic) {
  3135. dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
  3136. /* Wait for Nak effect */
  3137. if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
  3138. DXEPINT_INEPNAKEFF, 100))
  3139. dev_warn(hsotg->dev,
  3140. "%s: timeout DIEPINT.NAKEFF\n",
  3141. __func__);
  3142. } else {
  3143. dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
  3144. /* Wait for Nak effect */
  3145. if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
  3146. GINTSTS_GINNAKEFF, 100))
  3147. dev_warn(hsotg->dev,
  3148. "%s: timeout GINTSTS.GINNAKEFF\n",
  3149. __func__);
  3150. }
  3151. } else {
  3152. if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
  3153. dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
  3154. /* Wait for global nak to take effect */
  3155. if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
  3156. GINTSTS_GOUTNAKEFF, 100))
  3157. dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
  3158. __func__);
  3159. }
  3160. /* Disable ep */
  3161. dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
  3162. /* Wait for ep to be disabled */
  3163. if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
  3164. dev_warn(hsotg->dev,
  3165. "%s: timeout DOEPCTL.EPDisable\n", __func__);
  3166. /* Clear EPDISBLD interrupt */
  3167. dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
  3168. if (hs_ep->dir_in) {
  3169. unsigned short fifo_index;
  3170. if (hsotg->dedicated_fifos || hs_ep->periodic)
  3171. fifo_index = hs_ep->fifo_index;
  3172. else
  3173. fifo_index = 0;
  3174. /* Flush TX FIFO */
  3175. dwc2_flush_tx_fifo(hsotg, fifo_index);
  3176. /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
  3177. if (!hsotg->dedicated_fifos && !hs_ep->periodic)
  3178. dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
  3179. } else {
  3180. /* Remove global NAKs */
  3181. dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
  3182. }
  3183. }
  3184. /**
  3185. * dwc2_hsotg_ep_enable - enable the given endpoint
  3186. * @ep: The USB endpint to configure
  3187. * @desc: The USB endpoint descriptor to configure with.
  3188. *
  3189. * This is called from the USB gadget code's usb_ep_enable().
  3190. */
  3191. static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
  3192. const struct usb_endpoint_descriptor *desc)
  3193. {
  3194. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  3195. struct dwc2_hsotg *hsotg = hs_ep->parent;
  3196. unsigned long flags;
  3197. unsigned int index = hs_ep->index;
  3198. u32 epctrl_reg;
  3199. u32 epctrl;
  3200. u32 mps;
  3201. u32 mc;
  3202. u32 mask;
  3203. unsigned int dir_in;
  3204. unsigned int i, val, size;
  3205. int ret = 0;
  3206. unsigned char ep_type;
  3207. int desc_num;
  3208. dev_dbg(hsotg->dev,
  3209. "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
  3210. __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
  3211. desc->wMaxPacketSize, desc->bInterval);
  3212. /* not to be called for EP0 */
  3213. if (index == 0) {
  3214. dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
  3215. return -EINVAL;
  3216. }
  3217. dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
  3218. if (dir_in != hs_ep->dir_in) {
  3219. dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
  3220. return -EINVAL;
  3221. }
  3222. ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  3223. mps = usb_endpoint_maxp(desc);
  3224. mc = usb_endpoint_maxp_mult(desc);
  3225. /* ISOC IN in DDMA supported bInterval up to 10 */
  3226. if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
  3227. dir_in && desc->bInterval > 10) {
  3228. dev_err(hsotg->dev,
  3229. "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
  3230. return -EINVAL;
  3231. }
  3232. /* High bandwidth ISOC OUT in DDMA not supported */
  3233. if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
  3234. !dir_in && mc > 1) {
  3235. dev_err(hsotg->dev,
  3236. "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
  3237. return -EINVAL;
  3238. }
  3239. /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
  3240. epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
  3241. epctrl = dwc2_readl(hsotg, epctrl_reg);
  3242. dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
  3243. __func__, epctrl, epctrl_reg);
  3244. if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
  3245. desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
  3246. else
  3247. desc_num = MAX_DMA_DESC_NUM_GENERIC;
  3248. /* Allocate DMA descriptor chain for non-ctrl endpoints */
  3249. if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
  3250. hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
  3251. desc_num * sizeof(struct dwc2_dma_desc),
  3252. &hs_ep->desc_list_dma, GFP_ATOMIC);
  3253. if (!hs_ep->desc_list) {
  3254. ret = -ENOMEM;
  3255. goto error2;
  3256. }
  3257. }
  3258. spin_lock_irqsave(&hsotg->lock, flags);
  3259. epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
  3260. epctrl |= DXEPCTL_MPS(mps);
  3261. /*
  3262. * mark the endpoint as active, otherwise the core may ignore
  3263. * transactions entirely for this endpoint
  3264. */
  3265. epctrl |= DXEPCTL_USBACTEP;
  3266. /* update the endpoint state */
  3267. dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
  3268. /* default, set to non-periodic */
  3269. hs_ep->isochronous = 0;
  3270. hs_ep->periodic = 0;
  3271. hs_ep->halted = 0;
  3272. hs_ep->interval = desc->bInterval;
  3273. switch (ep_type) {
  3274. case USB_ENDPOINT_XFER_ISOC:
  3275. epctrl |= DXEPCTL_EPTYPE_ISO;
  3276. epctrl |= DXEPCTL_SETEVENFR;
  3277. hs_ep->isochronous = 1;
  3278. hs_ep->interval = 1 << (desc->bInterval - 1);
  3279. hs_ep->target_frame = TARGET_FRAME_INITIAL;
  3280. hs_ep->next_desc = 0;
  3281. hs_ep->compl_desc = 0;
  3282. if (dir_in) {
  3283. hs_ep->periodic = 1;
  3284. mask = dwc2_readl(hsotg, DIEPMSK);
  3285. mask |= DIEPMSK_NAKMSK;
  3286. dwc2_writel(hsotg, mask, DIEPMSK);
  3287. } else {
  3288. mask = dwc2_readl(hsotg, DOEPMSK);
  3289. mask |= DOEPMSK_OUTTKNEPDISMSK;
  3290. dwc2_writel(hsotg, mask, DOEPMSK);
  3291. }
  3292. break;
  3293. case USB_ENDPOINT_XFER_BULK:
  3294. epctrl |= DXEPCTL_EPTYPE_BULK;
  3295. break;
  3296. case USB_ENDPOINT_XFER_INT:
  3297. if (dir_in)
  3298. hs_ep->periodic = 1;
  3299. if (hsotg->gadget.speed == USB_SPEED_HIGH)
  3300. hs_ep->interval = 1 << (desc->bInterval - 1);
  3301. epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
  3302. break;
  3303. case USB_ENDPOINT_XFER_CONTROL:
  3304. epctrl |= DXEPCTL_EPTYPE_CONTROL;
  3305. break;
  3306. }
  3307. /*
  3308. * if the hardware has dedicated fifos, we must give each IN EP
  3309. * a unique tx-fifo even if it is non-periodic.
  3310. */
  3311. if (dir_in && hsotg->dedicated_fifos) {
  3312. unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
  3313. u32 fifo_index = 0;
  3314. u32 fifo_size = UINT_MAX;
  3315. size = hs_ep->ep.maxpacket * hs_ep->mc;
  3316. for (i = 1; i <= fifo_count; ++i) {
  3317. if (hsotg->fifo_map & (1 << i))
  3318. continue;
  3319. val = dwc2_readl(hsotg, DPTXFSIZN(i));
  3320. val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
  3321. if (val < size)
  3322. continue;
  3323. /* Search for smallest acceptable fifo */
  3324. if (val < fifo_size) {
  3325. fifo_size = val;
  3326. fifo_index = i;
  3327. }
  3328. }
  3329. if (!fifo_index) {
  3330. dev_err(hsotg->dev,
  3331. "%s: No suitable fifo found\n", __func__);
  3332. ret = -ENOMEM;
  3333. goto error1;
  3334. }
  3335. hsotg->fifo_map |= 1 << fifo_index;
  3336. epctrl |= DXEPCTL_TXFNUM(fifo_index);
  3337. hs_ep->fifo_index = fifo_index;
  3338. hs_ep->fifo_size = fifo_size;
  3339. }
  3340. /* for non control endpoints, set PID to D0 */
  3341. if (index && !hs_ep->isochronous)
  3342. epctrl |= DXEPCTL_SETD0PID;
  3343. /* WA for Full speed ISOC IN in DDMA mode.
  3344. * By Clear NAK status of EP, core will send ZLP
  3345. * to IN token and assert NAK interrupt relying
  3346. * on TxFIFO status only
  3347. */
  3348. if (hsotg->gadget.speed == USB_SPEED_FULL &&
  3349. hs_ep->isochronous && dir_in) {
  3350. /* The WA applies only to core versions from 2.72a
  3351. * to 4.00a (including both). Also for FS_IOT_1.00a
  3352. * and HS_IOT_1.00a.
  3353. */
  3354. u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
  3355. if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
  3356. gsnpsid <= DWC2_CORE_REV_4_00a) ||
  3357. gsnpsid == DWC2_FS_IOT_REV_1_00a ||
  3358. gsnpsid == DWC2_HS_IOT_REV_1_00a)
  3359. epctrl |= DXEPCTL_CNAK;
  3360. }
  3361. dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
  3362. __func__, epctrl);
  3363. dwc2_writel(hsotg, epctrl, epctrl_reg);
  3364. dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
  3365. __func__, dwc2_readl(hsotg, epctrl_reg));
  3366. /* enable the endpoint interrupt */
  3367. dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
  3368. error1:
  3369. spin_unlock_irqrestore(&hsotg->lock, flags);
  3370. error2:
  3371. if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
  3372. dmam_free_coherent(hsotg->dev, desc_num *
  3373. sizeof(struct dwc2_dma_desc),
  3374. hs_ep->desc_list, hs_ep->desc_list_dma);
  3375. hs_ep->desc_list = NULL;
  3376. }
  3377. return ret;
  3378. }
  3379. /**
  3380. * dwc2_hsotg_ep_disable - disable given endpoint
  3381. * @ep: The endpoint to disable.
  3382. */
  3383. static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
  3384. {
  3385. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  3386. struct dwc2_hsotg *hsotg = hs_ep->parent;
  3387. int dir_in = hs_ep->dir_in;
  3388. int index = hs_ep->index;
  3389. u32 epctrl_reg;
  3390. u32 ctrl;
  3391. dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
  3392. if (ep == &hsotg->eps_out[0]->ep) {
  3393. dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
  3394. return -EINVAL;
  3395. }
  3396. if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
  3397. dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
  3398. return -EINVAL;
  3399. }
  3400. epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
  3401. ctrl = dwc2_readl(hsotg, epctrl_reg);
  3402. if (ctrl & DXEPCTL_EPENA)
  3403. dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
  3404. ctrl &= ~DXEPCTL_EPENA;
  3405. ctrl &= ~DXEPCTL_USBACTEP;
  3406. ctrl |= DXEPCTL_SNAK;
  3407. dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
  3408. dwc2_writel(hsotg, ctrl, epctrl_reg);
  3409. /* disable endpoint interrupts */
  3410. dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
  3411. /* terminate all requests with shutdown */
  3412. kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
  3413. hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
  3414. hs_ep->fifo_index = 0;
  3415. hs_ep->fifo_size = 0;
  3416. return 0;
  3417. }
  3418. static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
  3419. {
  3420. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  3421. struct dwc2_hsotg *hsotg = hs_ep->parent;
  3422. unsigned long flags;
  3423. int ret;
  3424. spin_lock_irqsave(&hsotg->lock, flags);
  3425. ret = dwc2_hsotg_ep_disable(ep);
  3426. spin_unlock_irqrestore(&hsotg->lock, flags);
  3427. return ret;
  3428. }
  3429. /**
  3430. * on_list - check request is on the given endpoint
  3431. * @ep: The endpoint to check.
  3432. * @test: The request to test if it is on the endpoint.
  3433. */
  3434. static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
  3435. {
  3436. struct dwc2_hsotg_req *req, *treq;
  3437. list_for_each_entry_safe(req, treq, &ep->queue, queue) {
  3438. if (req == test)
  3439. return true;
  3440. }
  3441. return false;
  3442. }
  3443. /**
  3444. * dwc2_hsotg_ep_dequeue - dequeue given endpoint
  3445. * @ep: The endpoint to dequeue.
  3446. * @req: The request to be removed from a queue.
  3447. */
  3448. static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  3449. {
  3450. struct dwc2_hsotg_req *hs_req = our_req(req);
  3451. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  3452. struct dwc2_hsotg *hs = hs_ep->parent;
  3453. unsigned long flags;
  3454. dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
  3455. spin_lock_irqsave(&hs->lock, flags);
  3456. if (!on_list(hs_ep, hs_req)) {
  3457. spin_unlock_irqrestore(&hs->lock, flags);
  3458. return -EINVAL;
  3459. }
  3460. /* Dequeue already started request */
  3461. if (req == &hs_ep->req->req)
  3462. dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
  3463. dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
  3464. spin_unlock_irqrestore(&hs->lock, flags);
  3465. return 0;
  3466. }
  3467. /**
  3468. * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
  3469. * @ep: The endpoint to set halt.
  3470. * @value: Set or unset the halt.
  3471. * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
  3472. * the endpoint is busy processing requests.
  3473. *
  3474. * We need to stall the endpoint immediately if request comes from set_feature
  3475. * protocol command handler.
  3476. */
  3477. static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
  3478. {
  3479. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  3480. struct dwc2_hsotg *hs = hs_ep->parent;
  3481. int index = hs_ep->index;
  3482. u32 epreg;
  3483. u32 epctl;
  3484. u32 xfertype;
  3485. dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
  3486. if (index == 0) {
  3487. if (value)
  3488. dwc2_hsotg_stall_ep0(hs);
  3489. else
  3490. dev_warn(hs->dev,
  3491. "%s: can't clear halt on ep0\n", __func__);
  3492. return 0;
  3493. }
  3494. if (hs_ep->isochronous) {
  3495. dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
  3496. return -EINVAL;
  3497. }
  3498. if (!now && value && !list_empty(&hs_ep->queue)) {
  3499. dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
  3500. ep->name);
  3501. return -EAGAIN;
  3502. }
  3503. if (hs_ep->dir_in) {
  3504. epreg = DIEPCTL(index);
  3505. epctl = dwc2_readl(hs, epreg);
  3506. if (value) {
  3507. epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
  3508. if (epctl & DXEPCTL_EPENA)
  3509. epctl |= DXEPCTL_EPDIS;
  3510. } else {
  3511. epctl &= ~DXEPCTL_STALL;
  3512. xfertype = epctl & DXEPCTL_EPTYPE_MASK;
  3513. if (xfertype == DXEPCTL_EPTYPE_BULK ||
  3514. xfertype == DXEPCTL_EPTYPE_INTERRUPT)
  3515. epctl |= DXEPCTL_SETD0PID;
  3516. }
  3517. dwc2_writel(hs, epctl, epreg);
  3518. } else {
  3519. epreg = DOEPCTL(index);
  3520. epctl = dwc2_readl(hs, epreg);
  3521. if (value) {
  3522. epctl |= DXEPCTL_STALL;
  3523. } else {
  3524. epctl &= ~DXEPCTL_STALL;
  3525. xfertype = epctl & DXEPCTL_EPTYPE_MASK;
  3526. if (xfertype == DXEPCTL_EPTYPE_BULK ||
  3527. xfertype == DXEPCTL_EPTYPE_INTERRUPT)
  3528. epctl |= DXEPCTL_SETD0PID;
  3529. }
  3530. dwc2_writel(hs, epctl, epreg);
  3531. }
  3532. hs_ep->halted = value;
  3533. return 0;
  3534. }
  3535. /**
  3536. * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
  3537. * @ep: The endpoint to set halt.
  3538. * @value: Set or unset the halt.
  3539. */
  3540. static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
  3541. {
  3542. struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
  3543. struct dwc2_hsotg *hs = hs_ep->parent;
  3544. unsigned long flags = 0;
  3545. int ret = 0;
  3546. spin_lock_irqsave(&hs->lock, flags);
  3547. ret = dwc2_hsotg_ep_sethalt(ep, value, false);
  3548. spin_unlock_irqrestore(&hs->lock, flags);
  3549. return ret;
  3550. }
  3551. static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
  3552. .enable = dwc2_hsotg_ep_enable,
  3553. .disable = dwc2_hsotg_ep_disable_lock,
  3554. .alloc_request = dwc2_hsotg_ep_alloc_request,
  3555. .free_request = dwc2_hsotg_ep_free_request,
  3556. .queue = dwc2_hsotg_ep_queue_lock,
  3557. .dequeue = dwc2_hsotg_ep_dequeue,
  3558. .set_halt = dwc2_hsotg_ep_sethalt_lock,
  3559. /* note, don't believe we have any call for the fifo routines */
  3560. };
  3561. /**
  3562. * dwc2_hsotg_init - initialize the usb core
  3563. * @hsotg: The driver state
  3564. */
  3565. static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
  3566. {
  3567. u32 trdtim;
  3568. u32 usbcfg;
  3569. /* unmask subset of endpoint interrupts */
  3570. dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
  3571. DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
  3572. DIEPMSK);
  3573. dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
  3574. DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
  3575. DOEPMSK);
  3576. dwc2_writel(hsotg, 0, DAINTMSK);
  3577. /* Be in disconnected state until gadget is registered */
  3578. dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
  3579. /* setup fifos */
  3580. dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
  3581. dwc2_readl(hsotg, GRXFSIZ),
  3582. dwc2_readl(hsotg, GNPTXFSIZ));
  3583. dwc2_hsotg_init_fifo(hsotg);
  3584. /* keep other bits untouched (so e.g. forced modes are not lost) */
  3585. usbcfg = dwc2_readl(hsotg, GUSBCFG);
  3586. usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
  3587. GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
  3588. /* set the PLL on, remove the HNP/SRP and set the PHY */
  3589. trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
  3590. usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
  3591. (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
  3592. dwc2_writel(hsotg, usbcfg, GUSBCFG);
  3593. if (using_dma(hsotg))
  3594. dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
  3595. }
  3596. /**
  3597. * dwc2_hsotg_udc_start - prepare the udc for work
  3598. * @gadget: The usb gadget state
  3599. * @driver: The usb gadget driver
  3600. *
  3601. * Perform initialization to prepare udc device and driver
  3602. * to work.
  3603. */
  3604. static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
  3605. struct usb_gadget_driver *driver)
  3606. {
  3607. struct dwc2_hsotg *hsotg = to_hsotg(gadget);
  3608. unsigned long flags;
  3609. int ret;
  3610. if (!hsotg) {
  3611. pr_err("%s: called with no device\n", __func__);
  3612. return -ENODEV;
  3613. }
  3614. if (!driver) {
  3615. dev_err(hsotg->dev, "%s: no driver\n", __func__);
  3616. return -EINVAL;
  3617. }
  3618. if (driver->max_speed < USB_SPEED_FULL)
  3619. dev_err(hsotg->dev, "%s: bad speed\n", __func__);
  3620. if (!driver->setup) {
  3621. dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
  3622. return -EINVAL;
  3623. }
  3624. WARN_ON(hsotg->driver);
  3625. driver->driver.bus = NULL;
  3626. hsotg->driver = driver;
  3627. hsotg->gadget.dev.of_node = hsotg->dev->of_node;
  3628. hsotg->gadget.speed = USB_SPEED_UNKNOWN;
  3629. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
  3630. ret = dwc2_lowlevel_hw_enable(hsotg);
  3631. if (ret)
  3632. goto err;
  3633. }
  3634. if (!IS_ERR_OR_NULL(hsotg->uphy))
  3635. otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
  3636. spin_lock_irqsave(&hsotg->lock, flags);
  3637. if (dwc2_hw_is_device(hsotg)) {
  3638. dwc2_hsotg_init(hsotg);
  3639. dwc2_hsotg_core_init_disconnected(hsotg, false);
  3640. }
  3641. hsotg->enabled = 0;
  3642. spin_unlock_irqrestore(&hsotg->lock, flags);
  3643. dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
  3644. return 0;
  3645. err:
  3646. hsotg->driver = NULL;
  3647. return ret;
  3648. }
  3649. /**
  3650. * dwc2_hsotg_udc_stop - stop the udc
  3651. * @gadget: The usb gadget state
  3652. *
  3653. * Stop udc hw block and stay tunned for future transmissions
  3654. */
  3655. static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
  3656. {
  3657. struct dwc2_hsotg *hsotg = to_hsotg(gadget);
  3658. unsigned long flags = 0;
  3659. int ep;
  3660. if (!hsotg)
  3661. return -ENODEV;
  3662. /* all endpoints should be shutdown */
  3663. for (ep = 1; ep < hsotg->num_of_eps; ep++) {
  3664. if (hsotg->eps_in[ep])
  3665. dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
  3666. if (hsotg->eps_out[ep])
  3667. dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
  3668. }
  3669. spin_lock_irqsave(&hsotg->lock, flags);
  3670. hsotg->driver = NULL;
  3671. hsotg->gadget.speed = USB_SPEED_UNKNOWN;
  3672. hsotg->enabled = 0;
  3673. spin_unlock_irqrestore(&hsotg->lock, flags);
  3674. if (!IS_ERR_OR_NULL(hsotg->uphy))
  3675. otg_set_peripheral(hsotg->uphy->otg, NULL);
  3676. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  3677. dwc2_lowlevel_hw_disable(hsotg);
  3678. return 0;
  3679. }
  3680. /**
  3681. * dwc2_hsotg_gadget_getframe - read the frame number
  3682. * @gadget: The usb gadget state
  3683. *
  3684. * Read the {micro} frame number
  3685. */
  3686. static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
  3687. {
  3688. return dwc2_hsotg_read_frameno(to_hsotg(gadget));
  3689. }
  3690. /**
  3691. * dwc2_hsotg_pullup - connect/disconnect the USB PHY
  3692. * @gadget: The usb gadget state
  3693. * @is_on: Current state of the USB PHY
  3694. *
  3695. * Connect/Disconnect the USB PHY pullup
  3696. */
  3697. static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
  3698. {
  3699. struct dwc2_hsotg *hsotg = to_hsotg(gadget);
  3700. unsigned long flags = 0;
  3701. dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
  3702. hsotg->op_state);
  3703. /* Don't modify pullup state while in host mode */
  3704. if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
  3705. hsotg->enabled = is_on;
  3706. return 0;
  3707. }
  3708. spin_lock_irqsave(&hsotg->lock, flags);
  3709. if (is_on) {
  3710. hsotg->enabled = 1;
  3711. dwc2_hsotg_core_init_disconnected(hsotg, false);
  3712. /* Enable ACG feature in device mode,if supported */
  3713. dwc2_enable_acg(hsotg);
  3714. dwc2_hsotg_core_connect(hsotg);
  3715. } else {
  3716. dwc2_hsotg_core_disconnect(hsotg);
  3717. dwc2_hsotg_disconnect(hsotg);
  3718. hsotg->enabled = 0;
  3719. }
  3720. hsotg->gadget.speed = USB_SPEED_UNKNOWN;
  3721. spin_unlock_irqrestore(&hsotg->lock, flags);
  3722. return 0;
  3723. }
  3724. static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
  3725. {
  3726. struct dwc2_hsotg *hsotg = to_hsotg(gadget);
  3727. unsigned long flags;
  3728. dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
  3729. spin_lock_irqsave(&hsotg->lock, flags);
  3730. /*
  3731. * If controller is hibernated, it must exit from power_down
  3732. * before being initialized / de-initialized
  3733. */
  3734. if (hsotg->lx_state == DWC2_L2)
  3735. dwc2_exit_partial_power_down(hsotg, false);
  3736. if (is_active) {
  3737. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  3738. dwc2_hsotg_core_init_disconnected(hsotg, false);
  3739. if (hsotg->enabled) {
  3740. /* Enable ACG feature in device mode,if supported */
  3741. dwc2_enable_acg(hsotg);
  3742. dwc2_hsotg_core_connect(hsotg);
  3743. }
  3744. } else {
  3745. dwc2_hsotg_core_disconnect(hsotg);
  3746. dwc2_hsotg_disconnect(hsotg);
  3747. }
  3748. spin_unlock_irqrestore(&hsotg->lock, flags);
  3749. return 0;
  3750. }
  3751. /**
  3752. * dwc2_hsotg_vbus_draw - report bMaxPower field
  3753. * @gadget: The usb gadget state
  3754. * @mA: Amount of current
  3755. *
  3756. * Report how much power the device may consume to the phy.
  3757. */
  3758. static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
  3759. {
  3760. struct dwc2_hsotg *hsotg = to_hsotg(gadget);
  3761. if (IS_ERR_OR_NULL(hsotg->uphy))
  3762. return -ENOTSUPP;
  3763. return usb_phy_set_power(hsotg->uphy, mA);
  3764. }
  3765. static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
  3766. .get_frame = dwc2_hsotg_gadget_getframe,
  3767. .udc_start = dwc2_hsotg_udc_start,
  3768. .udc_stop = dwc2_hsotg_udc_stop,
  3769. .pullup = dwc2_hsotg_pullup,
  3770. .vbus_session = dwc2_hsotg_vbus_session,
  3771. .vbus_draw = dwc2_hsotg_vbus_draw,
  3772. };
  3773. /**
  3774. * dwc2_hsotg_initep - initialise a single endpoint
  3775. * @hsotg: The device state.
  3776. * @hs_ep: The endpoint to be initialised.
  3777. * @epnum: The endpoint number
  3778. * @dir_in: True if direction is in.
  3779. *
  3780. * Initialise the given endpoint (as part of the probe and device state
  3781. * creation) to give to the gadget driver. Setup the endpoint name, any
  3782. * direction information and other state that may be required.
  3783. */
  3784. static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
  3785. struct dwc2_hsotg_ep *hs_ep,
  3786. int epnum,
  3787. bool dir_in)
  3788. {
  3789. char *dir;
  3790. if (epnum == 0)
  3791. dir = "";
  3792. else if (dir_in)
  3793. dir = "in";
  3794. else
  3795. dir = "out";
  3796. hs_ep->dir_in = dir_in;
  3797. hs_ep->index = epnum;
  3798. snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
  3799. INIT_LIST_HEAD(&hs_ep->queue);
  3800. INIT_LIST_HEAD(&hs_ep->ep.ep_list);
  3801. /* add to the list of endpoints known by the gadget driver */
  3802. if (epnum)
  3803. list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
  3804. hs_ep->parent = hsotg;
  3805. hs_ep->ep.name = hs_ep->name;
  3806. if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
  3807. usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
  3808. else
  3809. usb_ep_set_maxpacket_limit(&hs_ep->ep,
  3810. epnum ? 1024 : EP0_MPS_LIMIT);
  3811. hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
  3812. if (epnum == 0) {
  3813. hs_ep->ep.caps.type_control = true;
  3814. } else {
  3815. if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
  3816. hs_ep->ep.caps.type_iso = true;
  3817. hs_ep->ep.caps.type_bulk = true;
  3818. }
  3819. hs_ep->ep.caps.type_int = true;
  3820. }
  3821. if (dir_in)
  3822. hs_ep->ep.caps.dir_in = true;
  3823. else
  3824. hs_ep->ep.caps.dir_out = true;
  3825. /*
  3826. * if we're using dma, we need to set the next-endpoint pointer
  3827. * to be something valid.
  3828. */
  3829. if (using_dma(hsotg)) {
  3830. u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
  3831. if (dir_in)
  3832. dwc2_writel(hsotg, next, DIEPCTL(epnum));
  3833. else
  3834. dwc2_writel(hsotg, next, DOEPCTL(epnum));
  3835. }
  3836. }
  3837. /**
  3838. * dwc2_hsotg_hw_cfg - read HW configuration registers
  3839. * @hsotg: Programming view of the DWC_otg controller
  3840. *
  3841. * Read the USB core HW configuration registers
  3842. */
  3843. static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
  3844. {
  3845. u32 cfg;
  3846. u32 ep_type;
  3847. u32 i;
  3848. /* check hardware configuration */
  3849. hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
  3850. /* Add ep0 */
  3851. hsotg->num_of_eps++;
  3852. hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
  3853. sizeof(struct dwc2_hsotg_ep),
  3854. GFP_KERNEL);
  3855. if (!hsotg->eps_in[0])
  3856. return -ENOMEM;
  3857. /* Same dwc2_hsotg_ep is used in both directions for ep0 */
  3858. hsotg->eps_out[0] = hsotg->eps_in[0];
  3859. cfg = hsotg->hw_params.dev_ep_dirs;
  3860. for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
  3861. ep_type = cfg & 3;
  3862. /* Direction in or both */
  3863. if (!(ep_type & 2)) {
  3864. hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
  3865. sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
  3866. if (!hsotg->eps_in[i])
  3867. return -ENOMEM;
  3868. }
  3869. /* Direction out or both */
  3870. if (!(ep_type & 1)) {
  3871. hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
  3872. sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
  3873. if (!hsotg->eps_out[i])
  3874. return -ENOMEM;
  3875. }
  3876. }
  3877. hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
  3878. hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
  3879. dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
  3880. hsotg->num_of_eps,
  3881. hsotg->dedicated_fifos ? "dedicated" : "shared",
  3882. hsotg->fifo_mem);
  3883. return 0;
  3884. }
  3885. /**
  3886. * dwc2_hsotg_dump - dump state of the udc
  3887. * @hsotg: Programming view of the DWC_otg controller
  3888. *
  3889. */
  3890. static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
  3891. {
  3892. #ifdef DEBUG
  3893. struct device *dev = hsotg->dev;
  3894. u32 val;
  3895. int idx;
  3896. dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
  3897. dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
  3898. dwc2_readl(hsotg, DIEPMSK));
  3899. dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
  3900. dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
  3901. dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
  3902. dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
  3903. /* show periodic fifo settings */
  3904. for (idx = 1; idx < hsotg->num_of_eps; idx++) {
  3905. val = dwc2_readl(hsotg, DPTXFSIZN(idx));
  3906. dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
  3907. val >> FIFOSIZE_DEPTH_SHIFT,
  3908. val & FIFOSIZE_STARTADDR_MASK);
  3909. }
  3910. for (idx = 0; idx < hsotg->num_of_eps; idx++) {
  3911. dev_info(dev,
  3912. "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
  3913. dwc2_readl(hsotg, DIEPCTL(idx)),
  3914. dwc2_readl(hsotg, DIEPTSIZ(idx)),
  3915. dwc2_readl(hsotg, DIEPDMA(idx)));
  3916. val = dwc2_readl(hsotg, DOEPCTL(idx));
  3917. dev_info(dev,
  3918. "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
  3919. idx, dwc2_readl(hsotg, DOEPCTL(idx)),
  3920. dwc2_readl(hsotg, DOEPTSIZ(idx)),
  3921. dwc2_readl(hsotg, DOEPDMA(idx)));
  3922. }
  3923. dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
  3924. dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
  3925. #endif
  3926. }
  3927. /**
  3928. * dwc2_gadget_init - init function for gadget
  3929. * @hsotg: Programming view of the DWC_otg controller
  3930. *
  3931. */
  3932. int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
  3933. {
  3934. struct device *dev = hsotg->dev;
  3935. int epnum;
  3936. int ret;
  3937. /* Dump fifo information */
  3938. dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
  3939. hsotg->params.g_np_tx_fifo_size);
  3940. dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
  3941. hsotg->gadget.max_speed = USB_SPEED_HIGH;
  3942. hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
  3943. hsotg->gadget.name = dev_name(dev);
  3944. hsotg->remote_wakeup_allowed = 0;
  3945. if (hsotg->params.lpm)
  3946. hsotg->gadget.lpm_capable = true;
  3947. if (hsotg->dr_mode == USB_DR_MODE_OTG)
  3948. hsotg->gadget.is_otg = 1;
  3949. else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  3950. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  3951. ret = dwc2_hsotg_hw_cfg(hsotg);
  3952. if (ret) {
  3953. dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
  3954. return ret;
  3955. }
  3956. hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
  3957. DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
  3958. if (!hsotg->ctrl_buff)
  3959. return -ENOMEM;
  3960. hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
  3961. DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
  3962. if (!hsotg->ep0_buff)
  3963. return -ENOMEM;
  3964. if (using_desc_dma(hsotg)) {
  3965. ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
  3966. if (ret < 0)
  3967. return ret;
  3968. }
  3969. ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
  3970. IRQF_SHARED, dev_name(hsotg->dev), hsotg);
  3971. if (ret < 0) {
  3972. dev_err(dev, "cannot claim IRQ for gadget\n");
  3973. return ret;
  3974. }
  3975. /* hsotg->num_of_eps holds number of EPs other than ep0 */
  3976. if (hsotg->num_of_eps == 0) {
  3977. dev_err(dev, "wrong number of EPs (zero)\n");
  3978. return -EINVAL;
  3979. }
  3980. /* setup endpoint information */
  3981. INIT_LIST_HEAD(&hsotg->gadget.ep_list);
  3982. hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
  3983. /* allocate EP0 request */
  3984. hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
  3985. GFP_KERNEL);
  3986. if (!hsotg->ctrl_req) {
  3987. dev_err(dev, "failed to allocate ctrl req\n");
  3988. return -ENOMEM;
  3989. }
  3990. /* initialise the endpoints now the core has been initialised */
  3991. for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
  3992. if (hsotg->eps_in[epnum])
  3993. dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
  3994. epnum, 1);
  3995. if (hsotg->eps_out[epnum])
  3996. dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
  3997. epnum, 0);
  3998. }
  3999. dwc2_hsotg_dump(hsotg);
  4000. return 0;
  4001. }
  4002. /**
  4003. * dwc2_hsotg_remove - remove function for hsotg driver
  4004. * @hsotg: Programming view of the DWC_otg controller
  4005. *
  4006. */
  4007. int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
  4008. {
  4009. usb_del_gadget_udc(&hsotg->gadget);
  4010. dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
  4011. return 0;
  4012. }
  4013. int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
  4014. {
  4015. unsigned long flags;
  4016. if (hsotg->lx_state != DWC2_L0)
  4017. return 0;
  4018. if (hsotg->driver) {
  4019. int ep;
  4020. dev_info(hsotg->dev, "suspending usb gadget %s\n",
  4021. hsotg->driver->driver.name);
  4022. spin_lock_irqsave(&hsotg->lock, flags);
  4023. if (hsotg->enabled)
  4024. dwc2_hsotg_core_disconnect(hsotg);
  4025. dwc2_hsotg_disconnect(hsotg);
  4026. hsotg->gadget.speed = USB_SPEED_UNKNOWN;
  4027. spin_unlock_irqrestore(&hsotg->lock, flags);
  4028. for (ep = 0; ep < hsotg->num_of_eps; ep++) {
  4029. if (hsotg->eps_in[ep])
  4030. dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
  4031. if (hsotg->eps_out[ep])
  4032. dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
  4033. }
  4034. }
  4035. return 0;
  4036. }
  4037. int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
  4038. {
  4039. unsigned long flags;
  4040. if (hsotg->lx_state == DWC2_L2)
  4041. return 0;
  4042. if (hsotg->driver) {
  4043. dev_info(hsotg->dev, "resuming usb gadget %s\n",
  4044. hsotg->driver->driver.name);
  4045. spin_lock_irqsave(&hsotg->lock, flags);
  4046. dwc2_hsotg_core_init_disconnected(hsotg, false);
  4047. if (hsotg->enabled) {
  4048. /* Enable ACG feature in device mode,if supported */
  4049. dwc2_enable_acg(hsotg);
  4050. dwc2_hsotg_core_connect(hsotg);
  4051. }
  4052. spin_unlock_irqrestore(&hsotg->lock, flags);
  4053. }
  4054. return 0;
  4055. }
  4056. /**
  4057. * dwc2_backup_device_registers() - Backup controller device registers.
  4058. * When suspending usb bus, registers needs to be backuped
  4059. * if controller power is disabled once suspended.
  4060. *
  4061. * @hsotg: Programming view of the DWC_otg controller
  4062. */
  4063. int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
  4064. {
  4065. struct dwc2_dregs_backup *dr;
  4066. int i;
  4067. dev_dbg(hsotg->dev, "%s\n", __func__);
  4068. /* Backup dev regs */
  4069. dr = &hsotg->dr_backup;
  4070. dr->dcfg = dwc2_readl(hsotg, DCFG);
  4071. dr->dctl = dwc2_readl(hsotg, DCTL);
  4072. dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
  4073. dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
  4074. dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
  4075. for (i = 0; i < hsotg->num_of_eps; i++) {
  4076. /* Backup IN EPs */
  4077. dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
  4078. /* Ensure DATA PID is correctly configured */
  4079. if (dr->diepctl[i] & DXEPCTL_DPID)
  4080. dr->diepctl[i] |= DXEPCTL_SETD1PID;
  4081. else
  4082. dr->diepctl[i] |= DXEPCTL_SETD0PID;
  4083. dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
  4084. dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
  4085. /* Backup OUT EPs */
  4086. dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
  4087. /* Ensure DATA PID is correctly configured */
  4088. if (dr->doepctl[i] & DXEPCTL_DPID)
  4089. dr->doepctl[i] |= DXEPCTL_SETD1PID;
  4090. else
  4091. dr->doepctl[i] |= DXEPCTL_SETD0PID;
  4092. dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
  4093. dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
  4094. dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
  4095. }
  4096. dr->valid = true;
  4097. return 0;
  4098. }
  4099. /**
  4100. * dwc2_restore_device_registers() - Restore controller device registers.
  4101. * When resuming usb bus, device registers needs to be restored
  4102. * if controller power were disabled.
  4103. *
  4104. * @hsotg: Programming view of the DWC_otg controller
  4105. * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
  4106. *
  4107. * Return: 0 if successful, negative error code otherwise
  4108. */
  4109. int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
  4110. {
  4111. struct dwc2_dregs_backup *dr;
  4112. int i;
  4113. dev_dbg(hsotg->dev, "%s\n", __func__);
  4114. /* Restore dev regs */
  4115. dr = &hsotg->dr_backup;
  4116. if (!dr->valid) {
  4117. dev_err(hsotg->dev, "%s: no device registers to restore\n",
  4118. __func__);
  4119. return -EINVAL;
  4120. }
  4121. dr->valid = false;
  4122. if (!remote_wakeup)
  4123. dwc2_writel(hsotg, dr->dctl, DCTL);
  4124. dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
  4125. dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
  4126. dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
  4127. for (i = 0; i < hsotg->num_of_eps; i++) {
  4128. /* Restore IN EPs */
  4129. dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
  4130. dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
  4131. dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
  4132. /** WA for enabled EPx's IN in DDMA mode. On entering to
  4133. * hibernation wrong value read and saved from DIEPDMAx,
  4134. * as result BNA interrupt asserted on hibernation exit
  4135. * by restoring from saved area.
  4136. */
  4137. if (hsotg->params.g_dma_desc &&
  4138. (dr->diepctl[i] & DXEPCTL_EPENA))
  4139. dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
  4140. dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
  4141. dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
  4142. /* Restore OUT EPs */
  4143. dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
  4144. /* WA for enabled EPx's OUT in DDMA mode. On entering to
  4145. * hibernation wrong value read and saved from DOEPDMAx,
  4146. * as result BNA interrupt asserted on hibernation exit
  4147. * by restoring from saved area.
  4148. */
  4149. if (hsotg->params.g_dma_desc &&
  4150. (dr->doepctl[i] & DXEPCTL_EPENA))
  4151. dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
  4152. dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
  4153. dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
  4154. }
  4155. return 0;
  4156. }
  4157. /**
  4158. * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
  4159. *
  4160. * @hsotg: Programming view of DWC_otg controller
  4161. *
  4162. */
  4163. void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
  4164. {
  4165. u32 val;
  4166. if (!hsotg->params.lpm)
  4167. return;
  4168. val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
  4169. val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
  4170. val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
  4171. val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
  4172. val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
  4173. dwc2_writel(hsotg, val, GLPMCFG);
  4174. dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
  4175. }
  4176. /**
  4177. * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
  4178. *
  4179. * @hsotg: Programming view of the DWC_otg controller
  4180. *
  4181. * Return non-zero if failed to enter to hibernation.
  4182. */
  4183. int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
  4184. {
  4185. u32 gpwrdn;
  4186. int ret = 0;
  4187. /* Change to L2(suspend) state */
  4188. hsotg->lx_state = DWC2_L2;
  4189. dev_dbg(hsotg->dev, "Start of hibernation completed\n");
  4190. ret = dwc2_backup_global_registers(hsotg);
  4191. if (ret) {
  4192. dev_err(hsotg->dev, "%s: failed to backup global registers\n",
  4193. __func__);
  4194. return ret;
  4195. }
  4196. ret = dwc2_backup_device_registers(hsotg);
  4197. if (ret) {
  4198. dev_err(hsotg->dev, "%s: failed to backup device registers\n",
  4199. __func__);
  4200. return ret;
  4201. }
  4202. gpwrdn = GPWRDN_PWRDNRSTN;
  4203. gpwrdn |= GPWRDN_PMUACTV;
  4204. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4205. udelay(10);
  4206. /* Set flag to indicate that we are in hibernation */
  4207. hsotg->hibernated = 1;
  4208. /* Enable interrupts from wake up logic */
  4209. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4210. gpwrdn |= GPWRDN_PMUINTSEL;
  4211. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4212. udelay(10);
  4213. /* Unmask device mode interrupts in GPWRDN */
  4214. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4215. gpwrdn |= GPWRDN_RST_DET_MSK;
  4216. gpwrdn |= GPWRDN_LNSTSCHG_MSK;
  4217. gpwrdn |= GPWRDN_STS_CHGINT_MSK;
  4218. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4219. udelay(10);
  4220. /* Enable Power Down Clamp */
  4221. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4222. gpwrdn |= GPWRDN_PWRDNCLMP;
  4223. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4224. udelay(10);
  4225. /* Switch off VDD */
  4226. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4227. gpwrdn |= GPWRDN_PWRDNSWTCH;
  4228. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4229. udelay(10);
  4230. /* Save gpwrdn register for further usage if stschng interrupt */
  4231. hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4232. dev_dbg(hsotg->dev, "Hibernation completed\n");
  4233. return ret;
  4234. }
  4235. /**
  4236. * dwc2_gadget_exit_hibernation()
  4237. * This function is for exiting from Device mode hibernation by host initiated
  4238. * resume/reset and device initiated remote-wakeup.
  4239. *
  4240. * @hsotg: Programming view of the DWC_otg controller
  4241. * @rem_wakeup: indicates whether resume is initiated by Device or Host.
  4242. * @reset: indicates whether resume is initiated by Reset.
  4243. *
  4244. * Return non-zero if failed to exit from hibernation.
  4245. */
  4246. int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
  4247. int rem_wakeup, int reset)
  4248. {
  4249. u32 pcgcctl;
  4250. u32 gpwrdn;
  4251. u32 dctl;
  4252. int ret = 0;
  4253. struct dwc2_gregs_backup *gr;
  4254. struct dwc2_dregs_backup *dr;
  4255. gr = &hsotg->gr_backup;
  4256. dr = &hsotg->dr_backup;
  4257. if (!hsotg->hibernated) {
  4258. dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
  4259. return 1;
  4260. }
  4261. dev_dbg(hsotg->dev,
  4262. "%s: called with rem_wakeup = %d reset = %d\n",
  4263. __func__, rem_wakeup, reset);
  4264. dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
  4265. if (!reset) {
  4266. /* Clear all pending interupts */
  4267. dwc2_writel(hsotg, 0xffffffff, GINTSTS);
  4268. }
  4269. /* De-assert Restore */
  4270. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4271. gpwrdn &= ~GPWRDN_RESTORE;
  4272. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4273. udelay(10);
  4274. if (!rem_wakeup) {
  4275. pcgcctl = dwc2_readl(hsotg, PCGCTL);
  4276. pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
  4277. dwc2_writel(hsotg, pcgcctl, PCGCTL);
  4278. }
  4279. /* Restore GUSBCFG, DCFG and DCTL */
  4280. dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
  4281. dwc2_writel(hsotg, dr->dcfg, DCFG);
  4282. dwc2_writel(hsotg, dr->dctl, DCTL);
  4283. /* De-assert Wakeup Logic */
  4284. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  4285. gpwrdn &= ~GPWRDN_PMUACTV;
  4286. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  4287. if (rem_wakeup) {
  4288. udelay(10);
  4289. /* Start Remote Wakeup Signaling */
  4290. dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
  4291. } else {
  4292. udelay(50);
  4293. /* Set Device programming done bit */
  4294. dctl = dwc2_readl(hsotg, DCTL);
  4295. dctl |= DCTL_PWRONPRGDONE;
  4296. dwc2_writel(hsotg, dctl, DCTL);
  4297. }
  4298. /* Wait for interrupts which must be cleared */
  4299. mdelay(2);
  4300. /* Clear all pending interupts */
  4301. dwc2_writel(hsotg, 0xffffffff, GINTSTS);
  4302. /* Restore global registers */
  4303. ret = dwc2_restore_global_registers(hsotg);
  4304. if (ret) {
  4305. dev_err(hsotg->dev, "%s: failed to restore registers\n",
  4306. __func__);
  4307. return ret;
  4308. }
  4309. /* Restore device registers */
  4310. ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
  4311. if (ret) {
  4312. dev_err(hsotg->dev, "%s: failed to restore device registers\n",
  4313. __func__);
  4314. return ret;
  4315. }
  4316. if (rem_wakeup) {
  4317. mdelay(10);
  4318. dctl = dwc2_readl(hsotg, DCTL);
  4319. dctl &= ~DCTL_RMTWKUPSIG;
  4320. dwc2_writel(hsotg, dctl, DCTL);
  4321. }
  4322. hsotg->hibernated = 0;
  4323. hsotg->lx_state = DWC2_L0;
  4324. dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
  4325. return ret;
  4326. }