lpc32xx_udc.c 83 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB Gadget driver for LPC32xx
  4. *
  5. * Authors:
  6. * Kevin Wells <kevin.wells@nxp.com>
  7. * Mike James
  8. * Roland Stigge <stigge@antcom.de>
  9. *
  10. * Copyright (C) 2006 Philips Semiconductors
  11. * Copyright (C) 2009 NXP Semiconductors
  12. * Copyright (C) 2012 Roland Stigge
  13. *
  14. * Note: This driver is based on original work done by Mike James for
  15. * the LPC3180.
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/delay.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/dmapool.h>
  21. #include <linux/i2c.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/module.h>
  24. #include <linux/of.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/proc_fs.h>
  27. #include <linux/slab.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include <linux/usb/isp1301.h>
  31. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  32. #include <linux/debugfs.h>
  33. #include <linux/seq_file.h>
  34. #endif
  35. #include <mach/hardware.h>
  36. /*
  37. * USB device configuration structure
  38. */
  39. typedef void (*usc_chg_event)(int);
  40. struct lpc32xx_usbd_cfg {
  41. int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
  42. usc_chg_event conn_chgb; /* Connection change event (optional) */
  43. usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
  44. usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
  45. };
  46. /*
  47. * controller driver data structures
  48. */
  49. /* 16 endpoints (not to be confused with 32 hardware endpoints) */
  50. #define NUM_ENDPOINTS 16
  51. /*
  52. * IRQ indices make reading the code a little easier
  53. */
  54. #define IRQ_USB_LP 0
  55. #define IRQ_USB_HP 1
  56. #define IRQ_USB_DEVDMA 2
  57. #define IRQ_USB_ATX 3
  58. #define EP_OUT 0 /* RX (from host) */
  59. #define EP_IN 1 /* TX (to host) */
  60. /* Returns the interrupt mask for the selected hardware endpoint */
  61. #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
  62. #define EP_INT_TYPE 0
  63. #define EP_ISO_TYPE 1
  64. #define EP_BLK_TYPE 2
  65. #define EP_CTL_TYPE 3
  66. /* EP0 states */
  67. #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
  68. #define DATA_IN 1 /* Expect dev->host transfer */
  69. #define DATA_OUT 2 /* Expect host->dev transfer */
  70. /* DD (DMA Descriptor) structure, requires word alignment, this is already
  71. * defined in the LPC32XX USB device header file, but this version is slightly
  72. * modified to tag some work data with each DMA descriptor. */
  73. struct lpc32xx_usbd_dd_gad {
  74. u32 dd_next_phy;
  75. u32 dd_setup;
  76. u32 dd_buffer_addr;
  77. u32 dd_status;
  78. u32 dd_iso_ps_mem_addr;
  79. u32 this_dma;
  80. u32 iso_status[6]; /* 5 spare */
  81. u32 dd_next_v;
  82. };
  83. /*
  84. * Logical endpoint structure
  85. */
  86. struct lpc32xx_ep {
  87. struct usb_ep ep;
  88. struct list_head queue;
  89. struct lpc32xx_udc *udc;
  90. u32 hwep_num_base; /* Physical hardware EP */
  91. u32 hwep_num; /* Maps to hardware endpoint */
  92. u32 maxpacket;
  93. u32 lep;
  94. bool is_in;
  95. bool req_pending;
  96. u32 eptype;
  97. u32 totalints;
  98. bool wedge;
  99. };
  100. /*
  101. * Common UDC structure
  102. */
  103. struct lpc32xx_udc {
  104. struct usb_gadget gadget;
  105. struct usb_gadget_driver *driver;
  106. struct platform_device *pdev;
  107. struct device *dev;
  108. struct dentry *pde;
  109. spinlock_t lock;
  110. struct i2c_client *isp1301_i2c_client;
  111. /* Board and device specific */
  112. struct lpc32xx_usbd_cfg *board;
  113. u32 io_p_start;
  114. u32 io_p_size;
  115. void __iomem *udp_baseaddr;
  116. int udp_irq[4];
  117. struct clk *usb_slv_clk;
  118. /* DMA support */
  119. u32 *udca_v_base;
  120. u32 udca_p_base;
  121. struct dma_pool *dd_cache;
  122. /* Common EP and control data */
  123. u32 enabled_devints;
  124. u32 enabled_hwepints;
  125. u32 dev_status;
  126. u32 realized_eps;
  127. /* VBUS detection, pullup, and power flags */
  128. u8 vbus;
  129. u8 last_vbus;
  130. int pullup;
  131. int poweron;
  132. /* Work queues related to I2C support */
  133. struct work_struct pullup_job;
  134. struct work_struct vbus_job;
  135. struct work_struct power_job;
  136. /* USB device peripheral - various */
  137. struct lpc32xx_ep ep[NUM_ENDPOINTS];
  138. bool enabled;
  139. bool clocked;
  140. bool suspended;
  141. int ep0state;
  142. atomic_t enabled_ep_cnt;
  143. wait_queue_head_t ep_disable_wait_queue;
  144. };
  145. /*
  146. * Endpoint request
  147. */
  148. struct lpc32xx_request {
  149. struct usb_request req;
  150. struct list_head queue;
  151. struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
  152. bool mapped;
  153. bool send_zlp;
  154. };
  155. static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
  156. {
  157. return container_of(g, struct lpc32xx_udc, gadget);
  158. }
  159. #define ep_dbg(epp, fmt, arg...) \
  160. dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
  161. #define ep_err(epp, fmt, arg...) \
  162. dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
  163. #define ep_info(epp, fmt, arg...) \
  164. dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
  165. #define ep_warn(epp, fmt, arg...) \
  166. dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
  167. #define UDCA_BUFF_SIZE (128)
  168. /**********************************************************************
  169. * USB device controller register offsets
  170. **********************************************************************/
  171. #define USBD_DEVINTST(x) ((x) + 0x200)
  172. #define USBD_DEVINTEN(x) ((x) + 0x204)
  173. #define USBD_DEVINTCLR(x) ((x) + 0x208)
  174. #define USBD_DEVINTSET(x) ((x) + 0x20C)
  175. #define USBD_CMDCODE(x) ((x) + 0x210)
  176. #define USBD_CMDDATA(x) ((x) + 0x214)
  177. #define USBD_RXDATA(x) ((x) + 0x218)
  178. #define USBD_TXDATA(x) ((x) + 0x21C)
  179. #define USBD_RXPLEN(x) ((x) + 0x220)
  180. #define USBD_TXPLEN(x) ((x) + 0x224)
  181. #define USBD_CTRL(x) ((x) + 0x228)
  182. #define USBD_DEVINTPRI(x) ((x) + 0x22C)
  183. #define USBD_EPINTST(x) ((x) + 0x230)
  184. #define USBD_EPINTEN(x) ((x) + 0x234)
  185. #define USBD_EPINTCLR(x) ((x) + 0x238)
  186. #define USBD_EPINTSET(x) ((x) + 0x23C)
  187. #define USBD_EPINTPRI(x) ((x) + 0x240)
  188. #define USBD_REEP(x) ((x) + 0x244)
  189. #define USBD_EPIND(x) ((x) + 0x248)
  190. #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
  191. /* DMA support registers only below */
  192. /* Set, clear, or get enabled state of the DMA request status. If
  193. * enabled, an IN or OUT token will start a DMA transfer for the EP */
  194. #define USBD_DMARST(x) ((x) + 0x250)
  195. #define USBD_DMARCLR(x) ((x) + 0x254)
  196. #define USBD_DMARSET(x) ((x) + 0x258)
  197. /* DMA UDCA head pointer */
  198. #define USBD_UDCAH(x) ((x) + 0x280)
  199. /* EP DMA status, enable, and disable. This is used to specifically
  200. * enabled or disable DMA for a specific EP */
  201. #define USBD_EPDMAST(x) ((x) + 0x284)
  202. #define USBD_EPDMAEN(x) ((x) + 0x288)
  203. #define USBD_EPDMADIS(x) ((x) + 0x28C)
  204. /* DMA master interrupts enable and pending interrupts */
  205. #define USBD_DMAINTST(x) ((x) + 0x290)
  206. #define USBD_DMAINTEN(x) ((x) + 0x294)
  207. /* DMA end of transfer interrupt enable, disable, status */
  208. #define USBD_EOTINTST(x) ((x) + 0x2A0)
  209. #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
  210. #define USBD_EOTINTSET(x) ((x) + 0x2A8)
  211. /* New DD request interrupt enable, disable, status */
  212. #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
  213. #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
  214. #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
  215. /* DMA error interrupt enable, disable, status */
  216. #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
  217. #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
  218. #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
  219. /**********************************************************************
  220. * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
  221. * USBD_DEVINTPRI register definitions
  222. **********************************************************************/
  223. #define USBD_ERR_INT (1 << 9)
  224. #define USBD_EP_RLZED (1 << 8)
  225. #define USBD_TXENDPKT (1 << 7)
  226. #define USBD_RXENDPKT (1 << 6)
  227. #define USBD_CDFULL (1 << 5)
  228. #define USBD_CCEMPTY (1 << 4)
  229. #define USBD_DEV_STAT (1 << 3)
  230. #define USBD_EP_SLOW (1 << 2)
  231. #define USBD_EP_FAST (1 << 1)
  232. #define USBD_FRAME (1 << 0)
  233. /**********************************************************************
  234. * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
  235. * USBD_EPINTPRI register definitions
  236. **********************************************************************/
  237. /* End point selection macro (RX) */
  238. #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
  239. /* End point selection macro (TX) */
  240. #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
  241. /**********************************************************************
  242. * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
  243. * USBD_EPDMAEN/USBD_EPDMADIS/
  244. * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
  245. * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
  246. * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
  247. * register definitions
  248. **********************************************************************/
  249. /* Endpoint selection macro */
  250. #define USBD_EP_SEL(e) (1 << (e))
  251. /**********************************************************************
  252. * SBD_DMAINTST/USBD_DMAINTEN
  253. **********************************************************************/
  254. #define USBD_SYS_ERR_INT (1 << 2)
  255. #define USBD_NEW_DD_INT (1 << 1)
  256. #define USBD_EOT_INT (1 << 0)
  257. /**********************************************************************
  258. * USBD_RXPLEN register definitions
  259. **********************************************************************/
  260. #define USBD_PKT_RDY (1 << 11)
  261. #define USBD_DV (1 << 10)
  262. #define USBD_PK_LEN_MASK 0x3FF
  263. /**********************************************************************
  264. * USBD_CTRL register definitions
  265. **********************************************************************/
  266. #define USBD_LOG_ENDPOINT(e) ((e) << 2)
  267. #define USBD_WR_EN (1 << 1)
  268. #define USBD_RD_EN (1 << 0)
  269. /**********************************************************************
  270. * USBD_CMDCODE register definitions
  271. **********************************************************************/
  272. #define USBD_CMD_CODE(c) ((c) << 16)
  273. #define USBD_CMD_PHASE(p) ((p) << 8)
  274. /**********************************************************************
  275. * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
  276. **********************************************************************/
  277. #define USBD_DMAEP(e) (1 << (e))
  278. /* DD (DMA Descriptor) structure, requires word alignment */
  279. struct lpc32xx_usbd_dd {
  280. u32 *dd_next;
  281. u32 dd_setup;
  282. u32 dd_buffer_addr;
  283. u32 dd_status;
  284. u32 dd_iso_ps_mem_addr;
  285. };
  286. /* dd_setup bit defines */
  287. #define DD_SETUP_ATLE_DMA_MODE 0x01
  288. #define DD_SETUP_NEXT_DD_VALID 0x04
  289. #define DD_SETUP_ISO_EP 0x10
  290. #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
  291. #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
  292. /* dd_status bit defines */
  293. #define DD_STATUS_DD_RETIRED 0x01
  294. #define DD_STATUS_STS_MASK 0x1E
  295. #define DD_STATUS_STS_NS 0x00 /* Not serviced */
  296. #define DD_STATUS_STS_BS 0x02 /* Being serviced */
  297. #define DD_STATUS_STS_NC 0x04 /* Normal completion */
  298. #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
  299. #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
  300. #define DD_STATUS_STS_SE 0x12 /* System error */
  301. #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
  302. #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
  303. #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
  304. #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
  305. #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
  306. /*
  307. *
  308. * Protocol engine bits below
  309. *
  310. */
  311. /* Device Interrupt Bit Definitions */
  312. #define FRAME_INT 0x00000001
  313. #define EP_FAST_INT 0x00000002
  314. #define EP_SLOW_INT 0x00000004
  315. #define DEV_STAT_INT 0x00000008
  316. #define CCEMTY_INT 0x00000010
  317. #define CDFULL_INT 0x00000020
  318. #define RxENDPKT_INT 0x00000040
  319. #define TxENDPKT_INT 0x00000080
  320. #define EP_RLZED_INT 0x00000100
  321. #define ERR_INT 0x00000200
  322. /* Rx & Tx Packet Length Definitions */
  323. #define PKT_LNGTH_MASK 0x000003FF
  324. #define PKT_DV 0x00000400
  325. #define PKT_RDY 0x00000800
  326. /* USB Control Definitions */
  327. #define CTRL_RD_EN 0x00000001
  328. #define CTRL_WR_EN 0x00000002
  329. /* Command Codes */
  330. #define CMD_SET_ADDR 0x00D00500
  331. #define CMD_CFG_DEV 0x00D80500
  332. #define CMD_SET_MODE 0x00F30500
  333. #define CMD_RD_FRAME 0x00F50500
  334. #define DAT_RD_FRAME 0x00F50200
  335. #define CMD_RD_TEST 0x00FD0500
  336. #define DAT_RD_TEST 0x00FD0200
  337. #define CMD_SET_DEV_STAT 0x00FE0500
  338. #define CMD_GET_DEV_STAT 0x00FE0500
  339. #define DAT_GET_DEV_STAT 0x00FE0200
  340. #define CMD_GET_ERR_CODE 0x00FF0500
  341. #define DAT_GET_ERR_CODE 0x00FF0200
  342. #define CMD_RD_ERR_STAT 0x00FB0500
  343. #define DAT_RD_ERR_STAT 0x00FB0200
  344. #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
  345. #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
  346. #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
  347. #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
  348. #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
  349. #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
  350. #define CMD_CLR_BUF 0x00F20500
  351. #define DAT_CLR_BUF 0x00F20200
  352. #define CMD_VALID_BUF 0x00FA0500
  353. /* Device Address Register Definitions */
  354. #define DEV_ADDR_MASK 0x7F
  355. #define DEV_EN 0x80
  356. /* Device Configure Register Definitions */
  357. #define CONF_DVICE 0x01
  358. /* Device Mode Register Definitions */
  359. #define AP_CLK 0x01
  360. #define INAK_CI 0x02
  361. #define INAK_CO 0x04
  362. #define INAK_II 0x08
  363. #define INAK_IO 0x10
  364. #define INAK_BI 0x20
  365. #define INAK_BO 0x40
  366. /* Device Status Register Definitions */
  367. #define DEV_CON 0x01
  368. #define DEV_CON_CH 0x02
  369. #define DEV_SUS 0x04
  370. #define DEV_SUS_CH 0x08
  371. #define DEV_RST 0x10
  372. /* Error Code Register Definitions */
  373. #define ERR_EC_MASK 0x0F
  374. #define ERR_EA 0x10
  375. /* Error Status Register Definitions */
  376. #define ERR_PID 0x01
  377. #define ERR_UEPKT 0x02
  378. #define ERR_DCRC 0x04
  379. #define ERR_TIMOUT 0x08
  380. #define ERR_EOP 0x10
  381. #define ERR_B_OVRN 0x20
  382. #define ERR_BTSTF 0x40
  383. #define ERR_TGL 0x80
  384. /* Endpoint Select Register Definitions */
  385. #define EP_SEL_F 0x01
  386. #define EP_SEL_ST 0x02
  387. #define EP_SEL_STP 0x04
  388. #define EP_SEL_PO 0x08
  389. #define EP_SEL_EPN 0x10
  390. #define EP_SEL_B_1_FULL 0x20
  391. #define EP_SEL_B_2_FULL 0x40
  392. /* Endpoint Status Register Definitions */
  393. #define EP_STAT_ST 0x01
  394. #define EP_STAT_DA 0x20
  395. #define EP_STAT_RF_MO 0x40
  396. #define EP_STAT_CND_ST 0x80
  397. /* Clear Buffer Register Definitions */
  398. #define CLR_BUF_PO 0x01
  399. /* DMA Interrupt Bit Definitions */
  400. #define EOT_INT 0x01
  401. #define NDD_REQ_INT 0x02
  402. #define SYS_ERR_INT 0x04
  403. #define DRIVER_VERSION "1.03"
  404. static const char driver_name[] = "lpc32xx_udc";
  405. /*
  406. *
  407. * proc interface support
  408. *
  409. */
  410. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  411. static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
  412. static const char debug_filename[] = "driver/udc";
  413. static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
  414. {
  415. struct lpc32xx_request *req;
  416. seq_printf(s, "\n");
  417. seq_printf(s, "%12s, maxpacket %4d %3s",
  418. ep->ep.name, ep->ep.maxpacket,
  419. ep->is_in ? "in" : "out");
  420. seq_printf(s, " type %4s", epnames[ep->eptype]);
  421. seq_printf(s, " ints: %12d", ep->totalints);
  422. if (list_empty(&ep->queue))
  423. seq_printf(s, "\t(queue empty)\n");
  424. else {
  425. list_for_each_entry(req, &ep->queue, queue) {
  426. u32 length = req->req.actual;
  427. seq_printf(s, "\treq %p len %d/%d buf %p\n",
  428. &req->req, length,
  429. req->req.length, req->req.buf);
  430. }
  431. }
  432. }
  433. static int proc_udc_show(struct seq_file *s, void *unused)
  434. {
  435. struct lpc32xx_udc *udc = s->private;
  436. struct lpc32xx_ep *ep;
  437. unsigned long flags;
  438. seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
  439. spin_lock_irqsave(&udc->lock, flags);
  440. seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
  441. udc->vbus ? "present" : "off",
  442. udc->enabled ? (udc->vbus ? "active" : "enabled") :
  443. "disabled",
  444. udc->gadget.is_selfpowered ? "self" : "VBUS",
  445. udc->suspended ? ", suspended" : "",
  446. udc->driver ? udc->driver->driver.name : "(none)");
  447. if (udc->enabled && udc->vbus) {
  448. proc_ep_show(s, &udc->ep[0]);
  449. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
  450. proc_ep_show(s, ep);
  451. }
  452. spin_unlock_irqrestore(&udc->lock, flags);
  453. return 0;
  454. }
  455. static int proc_udc_open(struct inode *inode, struct file *file)
  456. {
  457. return single_open(file, proc_udc_show, PDE_DATA(inode));
  458. }
  459. static const struct file_operations proc_ops = {
  460. .owner = THIS_MODULE,
  461. .open = proc_udc_open,
  462. .read = seq_read,
  463. .llseek = seq_lseek,
  464. .release = single_release,
  465. };
  466. static void create_debug_file(struct lpc32xx_udc *udc)
  467. {
  468. udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
  469. }
  470. static void remove_debug_file(struct lpc32xx_udc *udc)
  471. {
  472. debugfs_remove(udc->pde);
  473. }
  474. #else
  475. static inline void create_debug_file(struct lpc32xx_udc *udc) {}
  476. static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
  477. #endif
  478. /* Primary initialization sequence for the ISP1301 transceiver */
  479. static void isp1301_udc_configure(struct lpc32xx_udc *udc)
  480. {
  481. /* LPC32XX only supports DAT_SE0 USB mode */
  482. /* This sequence is important */
  483. /* Disable transparent UART mode first */
  484. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  485. (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  486. MC1_UART_EN);
  487. /* Set full speed and SE0 mode */
  488. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  489. (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  490. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  491. ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
  492. /*
  493. * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
  494. */
  495. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  496. (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  497. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  498. ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
  499. /* Driver VBUS_DRV high or low depending on board setup */
  500. if (udc->board->vbus_drv_pol != 0)
  501. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  502. ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
  503. else
  504. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  505. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  506. OTG1_VBUS_DRV);
  507. /* Bi-directional mode with suspend control
  508. * Enable both pulldowns for now - the pullup will be enable when VBUS
  509. * is detected */
  510. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  511. (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  512. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  513. ISP1301_I2C_OTG_CONTROL_1,
  514. (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
  515. /* Discharge VBUS (just in case) */
  516. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  517. ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
  518. msleep(1);
  519. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  520. (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  521. OTG1_VBUS_DISCHRG);
  522. /* Clear and enable VBUS high edge interrupt */
  523. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  524. ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  525. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  526. ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  527. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  528. ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
  529. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  530. ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  531. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  532. ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
  533. dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
  534. i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
  535. dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
  536. i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
  537. dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
  538. i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
  539. }
  540. /* Enables or disables the USB device pullup via the ISP1301 transceiver */
  541. static void isp1301_pullup_set(struct lpc32xx_udc *udc)
  542. {
  543. if (udc->pullup)
  544. /* Enable pullup for bus signalling */
  545. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  546. ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
  547. else
  548. /* Enable pullup for bus signalling */
  549. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  550. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  551. OTG1_DP_PULLUP);
  552. }
  553. static void pullup_work(struct work_struct *work)
  554. {
  555. struct lpc32xx_udc *udc =
  556. container_of(work, struct lpc32xx_udc, pullup_job);
  557. isp1301_pullup_set(udc);
  558. }
  559. static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
  560. int block)
  561. {
  562. if (en_pullup == udc->pullup)
  563. return;
  564. udc->pullup = en_pullup;
  565. if (block)
  566. isp1301_pullup_set(udc);
  567. else
  568. /* defer slow i2c pull up setting */
  569. schedule_work(&udc->pullup_job);
  570. }
  571. #ifdef CONFIG_PM
  572. /* Powers up or down the ISP1301 transceiver */
  573. static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
  574. {
  575. if (enable != 0)
  576. /* Power up ISP1301 - this ISP1301 will automatically wakeup
  577. when VBUS is detected */
  578. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  579. ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
  580. MC2_GLOBAL_PWR_DN);
  581. else
  582. /* Power down ISP1301 */
  583. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  584. ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
  585. }
  586. static void power_work(struct work_struct *work)
  587. {
  588. struct lpc32xx_udc *udc =
  589. container_of(work, struct lpc32xx_udc, power_job);
  590. isp1301_set_powerstate(udc, udc->poweron);
  591. }
  592. #endif
  593. /*
  594. *
  595. * USB protocol engine command/data read/write helper functions
  596. *
  597. */
  598. /* Issues a single command to the USB device state machine */
  599. static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
  600. {
  601. u32 pass = 0;
  602. int to;
  603. /* EP may lock on CLRI if this read isn't done */
  604. u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
  605. (void) tmp;
  606. while (pass == 0) {
  607. writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
  608. /* Write command code */
  609. writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
  610. to = 10000;
  611. while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
  612. USBD_CCEMPTY) == 0) && (to > 0)) {
  613. to--;
  614. }
  615. if (to > 0)
  616. pass = 1;
  617. cpu_relax();
  618. }
  619. }
  620. /* Issues 2 commands (or command and data) to the USB device state machine */
  621. static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
  622. u32 data)
  623. {
  624. udc_protocol_cmd_w(udc, cmd);
  625. udc_protocol_cmd_w(udc, data);
  626. }
  627. /* Issues a single command to the USB device state machine and reads
  628. * response data */
  629. static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
  630. {
  631. u32 tmp;
  632. int to = 1000;
  633. /* Write a command and read data from the protocol engine */
  634. writel((USBD_CDFULL | USBD_CCEMPTY),
  635. USBD_DEVINTCLR(udc->udp_baseaddr));
  636. /* Write command code */
  637. udc_protocol_cmd_w(udc, cmd);
  638. tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
  639. while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
  640. && (to > 0))
  641. to--;
  642. if (!to)
  643. dev_dbg(udc->dev,
  644. "Protocol engine didn't receive response (CDFULL)\n");
  645. return readl(USBD_CMDDATA(udc->udp_baseaddr));
  646. }
  647. /*
  648. *
  649. * USB device interrupt mask support functions
  650. *
  651. */
  652. /* Enable one or more USB device interrupts */
  653. static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
  654. {
  655. udc->enabled_devints |= devmask;
  656. writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
  657. }
  658. /* Disable one or more USB device interrupts */
  659. static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
  660. {
  661. udc->enabled_devints &= ~mask;
  662. writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
  663. }
  664. /* Clear one or more USB device interrupts */
  665. static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
  666. {
  667. writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
  668. }
  669. /*
  670. *
  671. * Endpoint interrupt disable/enable functions
  672. *
  673. */
  674. /* Enable one or more USB endpoint interrupts */
  675. static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
  676. {
  677. udc->enabled_hwepints |= (1 << hwep);
  678. writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
  679. }
  680. /* Disable one or more USB endpoint interrupts */
  681. static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
  682. {
  683. udc->enabled_hwepints &= ~(1 << hwep);
  684. writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
  685. }
  686. /* Clear one or more USB endpoint interrupts */
  687. static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
  688. {
  689. writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
  690. }
  691. /* Enable DMA for the HW channel */
  692. static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
  693. {
  694. writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
  695. }
  696. /* Disable DMA for the HW channel */
  697. static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
  698. {
  699. writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
  700. }
  701. /*
  702. *
  703. * Endpoint realize/unrealize functions
  704. *
  705. */
  706. /* Before an endpoint can be used, it needs to be realized
  707. * in the USB protocol engine - this realizes the endpoint.
  708. * The interrupt (FIFO or DMA) is not enabled with this function */
  709. static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
  710. u32 maxpacket)
  711. {
  712. int to = 1000;
  713. writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
  714. writel(hwep, USBD_EPIND(udc->udp_baseaddr));
  715. udc->realized_eps |= (1 << hwep);
  716. writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
  717. writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
  718. /* Wait until endpoint is realized in hardware */
  719. while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
  720. USBD_EP_RLZED)) && (to > 0))
  721. to--;
  722. if (!to)
  723. dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
  724. writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
  725. }
  726. /* Unrealize an EP */
  727. static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
  728. {
  729. udc->realized_eps &= ~(1 << hwep);
  730. writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
  731. }
  732. /*
  733. *
  734. * Endpoint support functions
  735. *
  736. */
  737. /* Select and clear endpoint interrupt */
  738. static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
  739. {
  740. udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
  741. return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
  742. }
  743. /* Disables the endpoint in the USB protocol engine */
  744. static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
  745. {
  746. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
  747. DAT_WR_BYTE(EP_STAT_DA));
  748. }
  749. /* Stalls the endpoint - endpoint will return STALL */
  750. static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
  751. {
  752. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
  753. DAT_WR_BYTE(EP_STAT_ST));
  754. }
  755. /* Clear stall or reset endpoint */
  756. static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
  757. {
  758. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
  759. DAT_WR_BYTE(0));
  760. }
  761. /* Select an endpoint for endpoint status, clear, validate */
  762. static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
  763. {
  764. udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
  765. }
  766. /*
  767. *
  768. * Endpoint buffer management functions
  769. *
  770. */
  771. /* Clear the current endpoint's buffer */
  772. static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
  773. {
  774. udc_select_hwep(udc, hwep);
  775. udc_protocol_cmd_w(udc, CMD_CLR_BUF);
  776. }
  777. /* Validate the current endpoint's buffer */
  778. static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
  779. {
  780. udc_select_hwep(udc, hwep);
  781. udc_protocol_cmd_w(udc, CMD_VALID_BUF);
  782. }
  783. static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
  784. {
  785. /* Clear EP interrupt */
  786. uda_clear_hwepint(udc, hwep);
  787. return udc_selep_clrint(udc, hwep);
  788. }
  789. /*
  790. *
  791. * USB EP DMA support
  792. *
  793. */
  794. /* Allocate a DMA Descriptor */
  795. static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
  796. {
  797. dma_addr_t dma;
  798. struct lpc32xx_usbd_dd_gad *dd;
  799. dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
  800. if (dd)
  801. dd->this_dma = dma;
  802. return dd;
  803. }
  804. /* Free a DMA Descriptor */
  805. static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
  806. {
  807. dma_pool_free(udc->dd_cache, dd, dd->this_dma);
  808. }
  809. /*
  810. *
  811. * USB setup and shutdown functions
  812. *
  813. */
  814. /* Enables or disables most of the USB system clocks when low power mode is
  815. * needed. Clocks are typically started on a connection event, and disabled
  816. * when a cable is disconnected */
  817. static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
  818. {
  819. if (enable != 0) {
  820. if (udc->clocked)
  821. return;
  822. udc->clocked = 1;
  823. clk_prepare_enable(udc->usb_slv_clk);
  824. } else {
  825. if (!udc->clocked)
  826. return;
  827. udc->clocked = 0;
  828. clk_disable_unprepare(udc->usb_slv_clk);
  829. }
  830. }
  831. /* Set/reset USB device address */
  832. static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
  833. {
  834. /* Address will be latched at the end of the status phase, or
  835. latched immediately if function is called twice */
  836. udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
  837. DAT_WR_BYTE(DEV_EN | addr));
  838. }
  839. /* Setup up a IN request for DMA transfer - this consists of determining the
  840. * list of DMA addresses for the transfer, allocating DMA Descriptors,
  841. * installing the DD into the UDCA, and then enabling the DMA for that EP */
  842. static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  843. {
  844. struct lpc32xx_request *req;
  845. u32 hwep = ep->hwep_num;
  846. ep->req_pending = 1;
  847. /* There will always be a request waiting here */
  848. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  849. /* Place the DD Descriptor into the UDCA */
  850. udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
  851. /* Enable DMA and interrupt for the HW EP */
  852. udc_ep_dma_enable(udc, hwep);
  853. /* Clear ZLP if last packet is not of MAXP size */
  854. if (req->req.length % ep->ep.maxpacket)
  855. req->send_zlp = 0;
  856. return 0;
  857. }
  858. /* Setup up a OUT request for DMA transfer - this consists of determining the
  859. * list of DMA addresses for the transfer, allocating DMA Descriptors,
  860. * installing the DD into the UDCA, and then enabling the DMA for that EP */
  861. static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  862. {
  863. struct lpc32xx_request *req;
  864. u32 hwep = ep->hwep_num;
  865. ep->req_pending = 1;
  866. /* There will always be a request waiting here */
  867. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  868. /* Place the DD Descriptor into the UDCA */
  869. udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
  870. /* Enable DMA and interrupt for the HW EP */
  871. udc_ep_dma_enable(udc, hwep);
  872. return 0;
  873. }
  874. static void udc_disable(struct lpc32xx_udc *udc)
  875. {
  876. u32 i;
  877. /* Disable device */
  878. udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
  879. udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
  880. /* Disable all device interrupts (including EP0) */
  881. uda_disable_devint(udc, 0x3FF);
  882. /* Disable and reset all endpoint interrupts */
  883. for (i = 0; i < 32; i++) {
  884. uda_disable_hwepint(udc, i);
  885. uda_clear_hwepint(udc, i);
  886. udc_disable_hwep(udc, i);
  887. udc_unrealize_hwep(udc, i);
  888. udc->udca_v_base[i] = 0;
  889. /* Disable and clear all interrupts and DMA */
  890. udc_ep_dma_disable(udc, i);
  891. writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
  892. writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
  893. writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  894. writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
  895. }
  896. /* Disable DMA interrupts */
  897. writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
  898. writel(0, USBD_UDCAH(udc->udp_baseaddr));
  899. }
  900. static void udc_enable(struct lpc32xx_udc *udc)
  901. {
  902. u32 i;
  903. struct lpc32xx_ep *ep = &udc->ep[0];
  904. /* Start with known state */
  905. udc_disable(udc);
  906. /* Enable device */
  907. udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
  908. /* EP interrupts on high priority, FRAME interrupt on low priority */
  909. writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
  910. writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
  911. /* Clear any pending device interrupts */
  912. writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
  913. /* Setup UDCA - not yet used (DMA) */
  914. writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
  915. /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
  916. for (i = 0; i <= 1; i++) {
  917. udc_realize_hwep(udc, i, ep->ep.maxpacket);
  918. uda_enable_hwepint(udc, i);
  919. udc_select_hwep(udc, i);
  920. udc_clrstall_hwep(udc, i);
  921. udc_clr_buffer_hwep(udc, i);
  922. }
  923. /* Device interrupt setup */
  924. uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
  925. USBD_EP_FAST));
  926. uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
  927. USBD_EP_FAST));
  928. /* Set device address to 0 - called twice to force a latch in the USB
  929. engine without the need of a setup packet status closure */
  930. udc_set_address(udc, 0);
  931. udc_set_address(udc, 0);
  932. /* Enable master DMA interrupts */
  933. writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
  934. USBD_DMAINTEN(udc->udp_baseaddr));
  935. udc->dev_status = 0;
  936. }
  937. /*
  938. *
  939. * USB device board specific events handled via callbacks
  940. *
  941. */
  942. /* Connection change event - notify board function of change */
  943. static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
  944. {
  945. /* Just notify of a connection change event (optional) */
  946. if (udc->board->conn_chgb != NULL)
  947. udc->board->conn_chgb(conn);
  948. }
  949. /* Suspend/resume event - notify board function of change */
  950. static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
  951. {
  952. /* Just notify of a Suspend/resume change event (optional) */
  953. if (udc->board->susp_chgb != NULL)
  954. udc->board->susp_chgb(conn);
  955. if (conn)
  956. udc->suspended = 0;
  957. else
  958. udc->suspended = 1;
  959. }
  960. /* Remote wakeup enable/disable - notify board function of change */
  961. static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
  962. {
  963. if (udc->board->rmwk_chgb != NULL)
  964. udc->board->rmwk_chgb(udc->dev_status &
  965. (1 << USB_DEVICE_REMOTE_WAKEUP));
  966. }
  967. /* Reads data from FIFO, adjusts for alignment and data size */
  968. static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
  969. {
  970. int n, i, bl;
  971. u16 *p16;
  972. u32 *p32, tmp, cbytes;
  973. /* Use optimal data transfer method based on source address and size */
  974. switch (((u32) data) & 0x3) {
  975. case 0: /* 32-bit aligned */
  976. p32 = (u32 *) data;
  977. cbytes = (bytes & ~0x3);
  978. /* Copy 32-bit aligned data first */
  979. for (n = 0; n < cbytes; n += 4)
  980. *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
  981. /* Handle any remaining bytes */
  982. bl = bytes - cbytes;
  983. if (bl) {
  984. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  985. for (n = 0; n < bl; n++)
  986. data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
  987. }
  988. break;
  989. case 1: /* 8-bit aligned */
  990. case 3:
  991. /* Each byte has to be handled independently */
  992. for (n = 0; n < bytes; n += 4) {
  993. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  994. bl = bytes - n;
  995. if (bl > 4)
  996. bl = 4;
  997. for (i = 0; i < bl; i++)
  998. data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
  999. }
  1000. break;
  1001. case 2: /* 16-bit aligned */
  1002. p16 = (u16 *) data;
  1003. cbytes = (bytes & ~0x3);
  1004. /* Copy 32-bit sized objects first with 16-bit alignment */
  1005. for (n = 0; n < cbytes; n += 4) {
  1006. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  1007. *p16++ = (u16)(tmp & 0xFFFF);
  1008. *p16++ = (u16)((tmp >> 16) & 0xFFFF);
  1009. }
  1010. /* Handle any remaining bytes */
  1011. bl = bytes - cbytes;
  1012. if (bl) {
  1013. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  1014. for (n = 0; n < bl; n++)
  1015. data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
  1016. }
  1017. break;
  1018. }
  1019. }
  1020. /* Read data from the FIFO for an endpoint. This function is for endpoints (such
  1021. * as EP0) that don't use DMA. This function should only be called if a packet
  1022. * is known to be ready to read for the endpoint. Note that the endpoint must
  1023. * be selected in the protocol engine prior to this call. */
  1024. static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
  1025. u32 bytes)
  1026. {
  1027. u32 tmpv;
  1028. int to = 1000;
  1029. u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
  1030. /* Setup read of endpoint */
  1031. writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
  1032. /* Wait until packet is ready */
  1033. while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
  1034. PKT_RDY) == 0) && (to > 0))
  1035. to--;
  1036. if (!to)
  1037. dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
  1038. /* Mask out count */
  1039. tmp = tmpv & PKT_LNGTH_MASK;
  1040. if (bytes < tmp)
  1041. tmp = bytes;
  1042. if ((tmp > 0) && (data != NULL))
  1043. udc_pop_fifo(udc, (u8 *) data, tmp);
  1044. writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
  1045. /* Clear the buffer */
  1046. udc_clr_buffer_hwep(udc, hwep);
  1047. return tmp;
  1048. }
  1049. /* Stuffs data into the FIFO, adjusts for alignment and data size */
  1050. static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
  1051. {
  1052. int n, i, bl;
  1053. u16 *p16;
  1054. u32 *p32, tmp, cbytes;
  1055. /* Use optimal data transfer method based on source address and size */
  1056. switch (((u32) data) & 0x3) {
  1057. case 0: /* 32-bit aligned */
  1058. p32 = (u32 *) data;
  1059. cbytes = (bytes & ~0x3);
  1060. /* Copy 32-bit aligned data first */
  1061. for (n = 0; n < cbytes; n += 4)
  1062. writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
  1063. /* Handle any remaining bytes */
  1064. bl = bytes - cbytes;
  1065. if (bl) {
  1066. tmp = 0;
  1067. for (n = 0; n < bl; n++)
  1068. tmp |= data[cbytes + n] << (n * 8);
  1069. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1070. }
  1071. break;
  1072. case 1: /* 8-bit aligned */
  1073. case 3:
  1074. /* Each byte has to be handled independently */
  1075. for (n = 0; n < bytes; n += 4) {
  1076. bl = bytes - n;
  1077. if (bl > 4)
  1078. bl = 4;
  1079. tmp = 0;
  1080. for (i = 0; i < bl; i++)
  1081. tmp |= data[n + i] << (i * 8);
  1082. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1083. }
  1084. break;
  1085. case 2: /* 16-bit aligned */
  1086. p16 = (u16 *) data;
  1087. cbytes = (bytes & ~0x3);
  1088. /* Copy 32-bit aligned data first */
  1089. for (n = 0; n < cbytes; n += 4) {
  1090. tmp = *p16++ & 0xFFFF;
  1091. tmp |= (*p16++ & 0xFFFF) << 16;
  1092. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1093. }
  1094. /* Handle any remaining bytes */
  1095. bl = bytes - cbytes;
  1096. if (bl) {
  1097. tmp = 0;
  1098. for (n = 0; n < bl; n++)
  1099. tmp |= data[cbytes + n] << (n * 8);
  1100. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1101. }
  1102. break;
  1103. }
  1104. }
  1105. /* Write data to the FIFO for an endpoint. This function is for endpoints (such
  1106. * as EP0) that don't use DMA. Note that the endpoint must be selected in the
  1107. * protocol engine prior to this call. */
  1108. static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
  1109. u32 bytes)
  1110. {
  1111. u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
  1112. if ((bytes > 0) && (data == NULL))
  1113. return;
  1114. /* Setup write of endpoint */
  1115. writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
  1116. writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
  1117. /* Need at least 1 byte to trigger TX */
  1118. if (bytes == 0)
  1119. writel(0, USBD_TXDATA(udc->udp_baseaddr));
  1120. else
  1121. udc_stuff_fifo(udc, (u8 *) data, bytes);
  1122. writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
  1123. udc_val_buffer_hwep(udc, hwep);
  1124. }
  1125. /* USB device reset - resets USB to a default state with just EP0
  1126. enabled */
  1127. static void uda_usb_reset(struct lpc32xx_udc *udc)
  1128. {
  1129. u32 i = 0;
  1130. /* Re-init device controller and EP0 */
  1131. udc_enable(udc);
  1132. udc->gadget.speed = USB_SPEED_FULL;
  1133. for (i = 1; i < NUM_ENDPOINTS; i++) {
  1134. struct lpc32xx_ep *ep = &udc->ep[i];
  1135. ep->req_pending = 0;
  1136. }
  1137. }
  1138. /* Send a ZLP on EP0 */
  1139. static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
  1140. {
  1141. udc_write_hwep(udc, EP_IN, NULL, 0);
  1142. }
  1143. /* Get current frame number */
  1144. static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
  1145. {
  1146. u16 flo, fhi;
  1147. udc_protocol_cmd_w(udc, CMD_RD_FRAME);
  1148. flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
  1149. fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
  1150. return (fhi << 8) | flo;
  1151. }
  1152. /* Set the device as configured - enables all endpoints */
  1153. static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
  1154. {
  1155. udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
  1156. }
  1157. /* Set the device as unconfigured - disables all endpoints */
  1158. static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
  1159. {
  1160. udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
  1161. }
  1162. /* reinit == restore initial software state */
  1163. static void udc_reinit(struct lpc32xx_udc *udc)
  1164. {
  1165. u32 i;
  1166. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1167. INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
  1168. for (i = 0; i < NUM_ENDPOINTS; i++) {
  1169. struct lpc32xx_ep *ep = &udc->ep[i];
  1170. if (i != 0)
  1171. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1172. usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
  1173. INIT_LIST_HEAD(&ep->queue);
  1174. ep->req_pending = 0;
  1175. }
  1176. udc->ep0state = WAIT_FOR_SETUP;
  1177. }
  1178. /* Must be called with lock */
  1179. static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
  1180. {
  1181. struct lpc32xx_udc *udc = ep->udc;
  1182. list_del_init(&req->queue);
  1183. if (req->req.status == -EINPROGRESS)
  1184. req->req.status = status;
  1185. else
  1186. status = req->req.status;
  1187. if (ep->lep) {
  1188. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  1189. /* Free DDs */
  1190. udc_dd_free(udc, req->dd_desc_ptr);
  1191. }
  1192. if (status && status != -ESHUTDOWN)
  1193. ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
  1194. ep->req_pending = 0;
  1195. spin_unlock(&udc->lock);
  1196. usb_gadget_giveback_request(&ep->ep, &req->req);
  1197. spin_lock(&udc->lock);
  1198. }
  1199. /* Must be called with lock */
  1200. static void nuke(struct lpc32xx_ep *ep, int status)
  1201. {
  1202. struct lpc32xx_request *req;
  1203. while (!list_empty(&ep->queue)) {
  1204. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  1205. done(ep, req, status);
  1206. }
  1207. if (status == -ESHUTDOWN) {
  1208. uda_disable_hwepint(ep->udc, ep->hwep_num);
  1209. udc_disable_hwep(ep->udc, ep->hwep_num);
  1210. }
  1211. }
  1212. /* IN endpoint 0 transfer */
  1213. static int udc_ep0_in_req(struct lpc32xx_udc *udc)
  1214. {
  1215. struct lpc32xx_request *req;
  1216. struct lpc32xx_ep *ep0 = &udc->ep[0];
  1217. u32 tsend, ts = 0;
  1218. if (list_empty(&ep0->queue))
  1219. /* Nothing to send */
  1220. return 0;
  1221. else
  1222. req = list_entry(ep0->queue.next, struct lpc32xx_request,
  1223. queue);
  1224. tsend = ts = req->req.length - req->req.actual;
  1225. if (ts == 0) {
  1226. /* Send a ZLP */
  1227. udc_ep0_send_zlp(udc);
  1228. done(ep0, req, 0);
  1229. return 1;
  1230. } else if (ts > ep0->ep.maxpacket)
  1231. ts = ep0->ep.maxpacket; /* Just send what we can */
  1232. /* Write data to the EP0 FIFO and start transfer */
  1233. udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
  1234. /* Increment data pointer */
  1235. req->req.actual += ts;
  1236. if (tsend >= ep0->ep.maxpacket)
  1237. return 0; /* Stay in data transfer state */
  1238. /* Transfer request is complete */
  1239. udc->ep0state = WAIT_FOR_SETUP;
  1240. done(ep0, req, 0);
  1241. return 1;
  1242. }
  1243. /* OUT endpoint 0 transfer */
  1244. static int udc_ep0_out_req(struct lpc32xx_udc *udc)
  1245. {
  1246. struct lpc32xx_request *req;
  1247. struct lpc32xx_ep *ep0 = &udc->ep[0];
  1248. u32 tr, bufferspace;
  1249. if (list_empty(&ep0->queue))
  1250. return 0;
  1251. else
  1252. req = list_entry(ep0->queue.next, struct lpc32xx_request,
  1253. queue);
  1254. if (req) {
  1255. if (req->req.length == 0) {
  1256. /* Just dequeue request */
  1257. done(ep0, req, 0);
  1258. udc->ep0state = WAIT_FOR_SETUP;
  1259. return 1;
  1260. }
  1261. /* Get data from FIFO */
  1262. bufferspace = req->req.length - req->req.actual;
  1263. if (bufferspace > ep0->ep.maxpacket)
  1264. bufferspace = ep0->ep.maxpacket;
  1265. /* Copy data to buffer */
  1266. prefetchw(req->req.buf + req->req.actual);
  1267. tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
  1268. bufferspace);
  1269. req->req.actual += bufferspace;
  1270. if (tr < ep0->ep.maxpacket) {
  1271. /* This is the last packet */
  1272. done(ep0, req, 0);
  1273. udc->ep0state = WAIT_FOR_SETUP;
  1274. return 1;
  1275. }
  1276. }
  1277. return 0;
  1278. }
  1279. /* Must be called with lock */
  1280. static void stop_activity(struct lpc32xx_udc *udc)
  1281. {
  1282. struct usb_gadget_driver *driver = udc->driver;
  1283. int i;
  1284. if (udc->gadget.speed == USB_SPEED_UNKNOWN)
  1285. driver = NULL;
  1286. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1287. udc->suspended = 0;
  1288. for (i = 0; i < NUM_ENDPOINTS; i++) {
  1289. struct lpc32xx_ep *ep = &udc->ep[i];
  1290. nuke(ep, -ESHUTDOWN);
  1291. }
  1292. if (driver) {
  1293. spin_unlock(&udc->lock);
  1294. driver->disconnect(&udc->gadget);
  1295. spin_lock(&udc->lock);
  1296. }
  1297. isp1301_pullup_enable(udc, 0, 0);
  1298. udc_disable(udc);
  1299. udc_reinit(udc);
  1300. }
  1301. /*
  1302. * Activate or kill host pullup
  1303. * Can be called with or without lock
  1304. */
  1305. static void pullup(struct lpc32xx_udc *udc, int is_on)
  1306. {
  1307. if (!udc->clocked)
  1308. return;
  1309. if (!udc->enabled || !udc->vbus)
  1310. is_on = 0;
  1311. if (is_on != udc->pullup)
  1312. isp1301_pullup_enable(udc, is_on, 0);
  1313. }
  1314. /* Must be called without lock */
  1315. static int lpc32xx_ep_disable(struct usb_ep *_ep)
  1316. {
  1317. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1318. struct lpc32xx_udc *udc = ep->udc;
  1319. unsigned long flags;
  1320. if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
  1321. return -EINVAL;
  1322. spin_lock_irqsave(&udc->lock, flags);
  1323. nuke(ep, -ESHUTDOWN);
  1324. /* Clear all DMA statuses for this EP */
  1325. udc_ep_dma_disable(udc, ep->hwep_num);
  1326. writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
  1327. writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
  1328. writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  1329. writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
  1330. /* Remove the DD pointer in the UDCA */
  1331. udc->udca_v_base[ep->hwep_num] = 0;
  1332. /* Disable and reset endpoint and interrupt */
  1333. uda_clear_hwepint(udc, ep->hwep_num);
  1334. udc_unrealize_hwep(udc, ep->hwep_num);
  1335. ep->hwep_num = 0;
  1336. spin_unlock_irqrestore(&udc->lock, flags);
  1337. atomic_dec(&udc->enabled_ep_cnt);
  1338. wake_up(&udc->ep_disable_wait_queue);
  1339. return 0;
  1340. }
  1341. /* Must be called without lock */
  1342. static int lpc32xx_ep_enable(struct usb_ep *_ep,
  1343. const struct usb_endpoint_descriptor *desc)
  1344. {
  1345. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1346. struct lpc32xx_udc *udc;
  1347. u16 maxpacket;
  1348. u32 tmp;
  1349. unsigned long flags;
  1350. /* Verify EP data */
  1351. if ((!_ep) || (!ep) || (!desc) ||
  1352. (desc->bDescriptorType != USB_DT_ENDPOINT))
  1353. return -EINVAL;
  1354. udc = ep->udc;
  1355. maxpacket = usb_endpoint_maxp(desc);
  1356. if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
  1357. dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
  1358. return -EINVAL;
  1359. }
  1360. /* Don't touch EP0 */
  1361. if (ep->hwep_num_base == 0) {
  1362. dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
  1363. return -EINVAL;
  1364. }
  1365. /* Is driver ready? */
  1366. if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
  1367. dev_dbg(udc->dev, "bogus device state\n");
  1368. return -ESHUTDOWN;
  1369. }
  1370. tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  1371. switch (tmp) {
  1372. case USB_ENDPOINT_XFER_CONTROL:
  1373. return -EINVAL;
  1374. case USB_ENDPOINT_XFER_INT:
  1375. if (maxpacket > ep->maxpacket) {
  1376. dev_dbg(udc->dev,
  1377. "Bad INT endpoint maxpacket %d\n", maxpacket);
  1378. return -EINVAL;
  1379. }
  1380. break;
  1381. case USB_ENDPOINT_XFER_BULK:
  1382. switch (maxpacket) {
  1383. case 8:
  1384. case 16:
  1385. case 32:
  1386. case 64:
  1387. break;
  1388. default:
  1389. dev_dbg(udc->dev,
  1390. "Bad BULK endpoint maxpacket %d\n", maxpacket);
  1391. return -EINVAL;
  1392. }
  1393. break;
  1394. case USB_ENDPOINT_XFER_ISOC:
  1395. break;
  1396. }
  1397. spin_lock_irqsave(&udc->lock, flags);
  1398. /* Initialize endpoint to match the selected descriptor */
  1399. ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
  1400. ep->ep.maxpacket = maxpacket;
  1401. /* Map hardware endpoint from base and direction */
  1402. if (ep->is_in)
  1403. /* IN endpoints are offset 1 from the OUT endpoint */
  1404. ep->hwep_num = ep->hwep_num_base + EP_IN;
  1405. else
  1406. ep->hwep_num = ep->hwep_num_base;
  1407. ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
  1408. ep->hwep_num, maxpacket, (ep->is_in == 1));
  1409. /* Realize the endpoint, interrupt is enabled later when
  1410. * buffers are queued, IN EPs will NAK until buffers are ready */
  1411. udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
  1412. udc_clr_buffer_hwep(udc, ep->hwep_num);
  1413. uda_disable_hwepint(udc, ep->hwep_num);
  1414. udc_clrstall_hwep(udc, ep->hwep_num);
  1415. /* Clear all DMA statuses for this EP */
  1416. udc_ep_dma_disable(udc, ep->hwep_num);
  1417. writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
  1418. writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
  1419. writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  1420. writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
  1421. spin_unlock_irqrestore(&udc->lock, flags);
  1422. atomic_inc(&udc->enabled_ep_cnt);
  1423. return 0;
  1424. }
  1425. /*
  1426. * Allocate a USB request list
  1427. * Can be called with or without lock
  1428. */
  1429. static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
  1430. gfp_t gfp_flags)
  1431. {
  1432. struct lpc32xx_request *req;
  1433. req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
  1434. if (!req)
  1435. return NULL;
  1436. INIT_LIST_HEAD(&req->queue);
  1437. return &req->req;
  1438. }
  1439. /*
  1440. * De-allocate a USB request list
  1441. * Can be called with or without lock
  1442. */
  1443. static void lpc32xx_ep_free_request(struct usb_ep *_ep,
  1444. struct usb_request *_req)
  1445. {
  1446. struct lpc32xx_request *req;
  1447. req = container_of(_req, struct lpc32xx_request, req);
  1448. BUG_ON(!list_empty(&req->queue));
  1449. kfree(req);
  1450. }
  1451. /* Must be called without lock */
  1452. static int lpc32xx_ep_queue(struct usb_ep *_ep,
  1453. struct usb_request *_req, gfp_t gfp_flags)
  1454. {
  1455. struct lpc32xx_request *req;
  1456. struct lpc32xx_ep *ep;
  1457. struct lpc32xx_udc *udc;
  1458. unsigned long flags;
  1459. int status = 0;
  1460. req = container_of(_req, struct lpc32xx_request, req);
  1461. ep = container_of(_ep, struct lpc32xx_ep, ep);
  1462. if (!_ep || !_req || !_req->complete || !_req->buf ||
  1463. !list_empty(&req->queue))
  1464. return -EINVAL;
  1465. udc = ep->udc;
  1466. if (udc->gadget.speed == USB_SPEED_UNKNOWN)
  1467. return -EPIPE;
  1468. if (ep->lep) {
  1469. struct lpc32xx_usbd_dd_gad *dd;
  1470. status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
  1471. if (status)
  1472. return status;
  1473. /* For the request, build a list of DDs */
  1474. dd = udc_dd_alloc(udc);
  1475. if (!dd) {
  1476. /* Error allocating DD */
  1477. return -ENOMEM;
  1478. }
  1479. req->dd_desc_ptr = dd;
  1480. /* Setup the DMA descriptor */
  1481. dd->dd_next_phy = dd->dd_next_v = 0;
  1482. dd->dd_buffer_addr = req->req.dma;
  1483. dd->dd_status = 0;
  1484. /* Special handling for ISO EPs */
  1485. if (ep->eptype == EP_ISO_TYPE) {
  1486. dd->dd_setup = DD_SETUP_ISO_EP |
  1487. DD_SETUP_PACKETLEN(0) |
  1488. DD_SETUP_DMALENBYTES(1);
  1489. dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
  1490. if (ep->is_in)
  1491. dd->iso_status[0] = req->req.length;
  1492. else
  1493. dd->iso_status[0] = 0;
  1494. } else
  1495. dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
  1496. DD_SETUP_DMALENBYTES(req->req.length);
  1497. }
  1498. ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
  1499. _req, _req->length, _req->buf, ep->is_in, _req->zero);
  1500. spin_lock_irqsave(&udc->lock, flags);
  1501. _req->status = -EINPROGRESS;
  1502. _req->actual = 0;
  1503. req->send_zlp = _req->zero;
  1504. /* Kickstart empty queues */
  1505. if (list_empty(&ep->queue)) {
  1506. list_add_tail(&req->queue, &ep->queue);
  1507. if (ep->hwep_num_base == 0) {
  1508. /* Handle expected data direction */
  1509. if (ep->is_in) {
  1510. /* IN packet to host */
  1511. udc->ep0state = DATA_IN;
  1512. status = udc_ep0_in_req(udc);
  1513. } else {
  1514. /* OUT packet from host */
  1515. udc->ep0state = DATA_OUT;
  1516. status = udc_ep0_out_req(udc);
  1517. }
  1518. } else if (ep->is_in) {
  1519. /* IN packet to host and kick off transfer */
  1520. if (!ep->req_pending)
  1521. udc_ep_in_req_dma(udc, ep);
  1522. } else
  1523. /* OUT packet from host and kick off list */
  1524. if (!ep->req_pending)
  1525. udc_ep_out_req_dma(udc, ep);
  1526. } else
  1527. list_add_tail(&req->queue, &ep->queue);
  1528. spin_unlock_irqrestore(&udc->lock, flags);
  1529. return (status < 0) ? status : 0;
  1530. }
  1531. /* Must be called without lock */
  1532. static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1533. {
  1534. struct lpc32xx_ep *ep;
  1535. struct lpc32xx_request *req;
  1536. unsigned long flags;
  1537. ep = container_of(_ep, struct lpc32xx_ep, ep);
  1538. if (!_ep || ep->hwep_num_base == 0)
  1539. return -EINVAL;
  1540. spin_lock_irqsave(&ep->udc->lock, flags);
  1541. /* make sure it's actually queued on this endpoint */
  1542. list_for_each_entry(req, &ep->queue, queue) {
  1543. if (&req->req == _req)
  1544. break;
  1545. }
  1546. if (&req->req != _req) {
  1547. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1548. return -EINVAL;
  1549. }
  1550. done(ep, req, -ECONNRESET);
  1551. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1552. return 0;
  1553. }
  1554. /* Must be called without lock */
  1555. static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
  1556. {
  1557. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1558. struct lpc32xx_udc *udc;
  1559. unsigned long flags;
  1560. if ((!ep) || (ep->hwep_num <= 1))
  1561. return -EINVAL;
  1562. /* Don't halt an IN EP */
  1563. if (ep->is_in)
  1564. return -EAGAIN;
  1565. udc = ep->udc;
  1566. spin_lock_irqsave(&udc->lock, flags);
  1567. if (value == 1) {
  1568. /* stall */
  1569. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
  1570. DAT_WR_BYTE(EP_STAT_ST));
  1571. } else {
  1572. /* End stall */
  1573. ep->wedge = 0;
  1574. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
  1575. DAT_WR_BYTE(0));
  1576. }
  1577. spin_unlock_irqrestore(&udc->lock, flags);
  1578. return 0;
  1579. }
  1580. /* set the halt feature and ignores clear requests */
  1581. static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
  1582. {
  1583. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1584. if (!_ep || !ep->udc)
  1585. return -EINVAL;
  1586. ep->wedge = 1;
  1587. return usb_ep_set_halt(_ep);
  1588. }
  1589. static const struct usb_ep_ops lpc32xx_ep_ops = {
  1590. .enable = lpc32xx_ep_enable,
  1591. .disable = lpc32xx_ep_disable,
  1592. .alloc_request = lpc32xx_ep_alloc_request,
  1593. .free_request = lpc32xx_ep_free_request,
  1594. .queue = lpc32xx_ep_queue,
  1595. .dequeue = lpc32xx_ep_dequeue,
  1596. .set_halt = lpc32xx_ep_set_halt,
  1597. .set_wedge = lpc32xx_ep_set_wedge,
  1598. };
  1599. /* Send a ZLP on a non-0 IN EP */
  1600. void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  1601. {
  1602. /* Clear EP status */
  1603. udc_clearep_getsts(udc, ep->hwep_num);
  1604. /* Send ZLP via FIFO mechanism */
  1605. udc_write_hwep(udc, ep->hwep_num, NULL, 0);
  1606. }
  1607. /*
  1608. * Handle EP completion for ZLP
  1609. * This function will only be called when a delayed ZLP needs to be sent out
  1610. * after a DMA transfer has filled both buffers.
  1611. */
  1612. void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  1613. {
  1614. u32 epstatus;
  1615. struct lpc32xx_request *req;
  1616. if (ep->hwep_num <= 0)
  1617. return;
  1618. uda_clear_hwepint(udc, ep->hwep_num);
  1619. /* If this interrupt isn't enabled, return now */
  1620. if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
  1621. return;
  1622. /* Get endpoint status */
  1623. epstatus = udc_clearep_getsts(udc, ep->hwep_num);
  1624. /*
  1625. * This should never happen, but protect against writing to the
  1626. * buffer when full.
  1627. */
  1628. if (epstatus & EP_SEL_F)
  1629. return;
  1630. if (ep->is_in) {
  1631. udc_send_in_zlp(udc, ep);
  1632. uda_disable_hwepint(udc, ep->hwep_num);
  1633. } else
  1634. return;
  1635. /* If there isn't a request waiting, something went wrong */
  1636. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  1637. if (req) {
  1638. done(ep, req, 0);
  1639. /* Start another request if ready */
  1640. if (!list_empty(&ep->queue)) {
  1641. if (ep->is_in)
  1642. udc_ep_in_req_dma(udc, ep);
  1643. else
  1644. udc_ep_out_req_dma(udc, ep);
  1645. } else
  1646. ep->req_pending = 0;
  1647. }
  1648. }
  1649. /* DMA end of transfer completion */
  1650. static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  1651. {
  1652. u32 status, epstatus;
  1653. struct lpc32xx_request *req;
  1654. struct lpc32xx_usbd_dd_gad *dd;
  1655. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1656. ep->totalints++;
  1657. #endif
  1658. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  1659. if (!req) {
  1660. ep_err(ep, "DMA interrupt on no req!\n");
  1661. return;
  1662. }
  1663. dd = req->dd_desc_ptr;
  1664. /* DMA descriptor should always be retired for this call */
  1665. if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
  1666. ep_warn(ep, "DMA descriptor did not retire\n");
  1667. /* Disable DMA */
  1668. udc_ep_dma_disable(udc, ep->hwep_num);
  1669. writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
  1670. writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
  1671. /* System error? */
  1672. if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
  1673. (1 << ep->hwep_num)) {
  1674. writel((1 << ep->hwep_num),
  1675. USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  1676. ep_err(ep, "AHB critical error!\n");
  1677. ep->req_pending = 0;
  1678. /* The error could have occurred on a packet of a multipacket
  1679. * transfer, so recovering the transfer is not possible. Close
  1680. * the request with an error */
  1681. done(ep, req, -ECONNABORTED);
  1682. return;
  1683. }
  1684. /* Handle the current DD's status */
  1685. status = dd->dd_status;
  1686. switch (status & DD_STATUS_STS_MASK) {
  1687. case DD_STATUS_STS_NS:
  1688. /* DD not serviced? This shouldn't happen! */
  1689. ep->req_pending = 0;
  1690. ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
  1691. status);
  1692. done(ep, req, -ECONNABORTED);
  1693. return;
  1694. case DD_STATUS_STS_BS:
  1695. /* Interrupt only fires on EOT - This shouldn't happen! */
  1696. ep->req_pending = 0;
  1697. ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
  1698. status);
  1699. done(ep, req, -ECONNABORTED);
  1700. return;
  1701. case DD_STATUS_STS_NC:
  1702. case DD_STATUS_STS_DUR:
  1703. /* Really just a short packet, not an underrun */
  1704. /* This is a good status and what we expect */
  1705. break;
  1706. default:
  1707. /* Data overrun, system error, or unknown */
  1708. ep->req_pending = 0;
  1709. ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
  1710. status);
  1711. done(ep, req, -ECONNABORTED);
  1712. return;
  1713. }
  1714. /* ISO endpoints are handled differently */
  1715. if (ep->eptype == EP_ISO_TYPE) {
  1716. if (ep->is_in)
  1717. req->req.actual = req->req.length;
  1718. else
  1719. req->req.actual = dd->iso_status[0] & 0xFFFF;
  1720. } else
  1721. req->req.actual += DD_STATUS_CURDMACNT(status);
  1722. /* Send a ZLP if necessary. This will be done for non-int
  1723. * packets which have a size that is a divisor of MAXP */
  1724. if (req->send_zlp) {
  1725. /*
  1726. * If at least 1 buffer is available, send the ZLP now.
  1727. * Otherwise, the ZLP send needs to be deferred until a
  1728. * buffer is available.
  1729. */
  1730. if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
  1731. udc_clearep_getsts(udc, ep->hwep_num);
  1732. uda_enable_hwepint(udc, ep->hwep_num);
  1733. epstatus = udc_clearep_getsts(udc, ep->hwep_num);
  1734. /* Let the EP interrupt handle the ZLP */
  1735. return;
  1736. } else
  1737. udc_send_in_zlp(udc, ep);
  1738. }
  1739. /* Transfer request is complete */
  1740. done(ep, req, 0);
  1741. /* Start another request if ready */
  1742. udc_clearep_getsts(udc, ep->hwep_num);
  1743. if (!list_empty((&ep->queue))) {
  1744. if (ep->is_in)
  1745. udc_ep_in_req_dma(udc, ep);
  1746. else
  1747. udc_ep_out_req_dma(udc, ep);
  1748. } else
  1749. ep->req_pending = 0;
  1750. }
  1751. /*
  1752. *
  1753. * Endpoint 0 functions
  1754. *
  1755. */
  1756. static void udc_handle_dev(struct lpc32xx_udc *udc)
  1757. {
  1758. u32 tmp;
  1759. udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
  1760. tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
  1761. if (tmp & DEV_RST)
  1762. uda_usb_reset(udc);
  1763. else if (tmp & DEV_CON_CH)
  1764. uda_power_event(udc, (tmp & DEV_CON));
  1765. else if (tmp & DEV_SUS_CH) {
  1766. if (tmp & DEV_SUS) {
  1767. if (udc->vbus == 0)
  1768. stop_activity(udc);
  1769. else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
  1770. udc->driver) {
  1771. /* Power down transceiver */
  1772. udc->poweron = 0;
  1773. schedule_work(&udc->pullup_job);
  1774. uda_resm_susp_event(udc, 1);
  1775. }
  1776. } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
  1777. udc->driver && udc->vbus) {
  1778. uda_resm_susp_event(udc, 0);
  1779. /* Power up transceiver */
  1780. udc->poweron = 1;
  1781. schedule_work(&udc->pullup_job);
  1782. }
  1783. }
  1784. }
  1785. static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
  1786. {
  1787. struct lpc32xx_ep *ep;
  1788. u32 ep0buff = 0, tmp;
  1789. switch (reqtype & USB_RECIP_MASK) {
  1790. case USB_RECIP_INTERFACE:
  1791. break; /* Not supported */
  1792. case USB_RECIP_DEVICE:
  1793. ep0buff = udc->gadget.is_selfpowered;
  1794. if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
  1795. ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
  1796. break;
  1797. case USB_RECIP_ENDPOINT:
  1798. tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
  1799. ep = &udc->ep[tmp];
  1800. if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
  1801. return -EOPNOTSUPP;
  1802. if (wIndex & USB_DIR_IN) {
  1803. if (!ep->is_in)
  1804. return -EOPNOTSUPP; /* Something's wrong */
  1805. } else if (ep->is_in)
  1806. return -EOPNOTSUPP; /* Not an IN endpoint */
  1807. /* Get status of the endpoint */
  1808. udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
  1809. tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
  1810. if (tmp & EP_SEL_ST)
  1811. ep0buff = (1 << USB_ENDPOINT_HALT);
  1812. else
  1813. ep0buff = 0;
  1814. break;
  1815. default:
  1816. break;
  1817. }
  1818. /* Return data */
  1819. udc_write_hwep(udc, EP_IN, &ep0buff, 2);
  1820. return 0;
  1821. }
  1822. static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
  1823. {
  1824. struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
  1825. struct usb_ctrlrequest ctrlpkt;
  1826. int i, bytes;
  1827. u16 wIndex, wValue, wLength, reqtype, req, tmp;
  1828. /* Nuke previous transfers */
  1829. nuke(ep0, -EPROTO);
  1830. /* Get setup packet */
  1831. bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
  1832. if (bytes != 8) {
  1833. ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
  1834. bytes);
  1835. return;
  1836. }
  1837. /* Native endianness */
  1838. wIndex = le16_to_cpu(ctrlpkt.wIndex);
  1839. wValue = le16_to_cpu(ctrlpkt.wValue);
  1840. wLength = le16_to_cpu(ctrlpkt.wLength);
  1841. reqtype = le16_to_cpu(ctrlpkt.bRequestType);
  1842. /* Set direction of EP0 */
  1843. if (likely(reqtype & USB_DIR_IN))
  1844. ep0->is_in = 1;
  1845. else
  1846. ep0->is_in = 0;
  1847. /* Handle SETUP packet */
  1848. req = le16_to_cpu(ctrlpkt.bRequest);
  1849. switch (req) {
  1850. case USB_REQ_CLEAR_FEATURE:
  1851. case USB_REQ_SET_FEATURE:
  1852. switch (reqtype) {
  1853. case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
  1854. if (wValue != USB_DEVICE_REMOTE_WAKEUP)
  1855. goto stall; /* Nothing else handled */
  1856. /* Tell board about event */
  1857. if (req == USB_REQ_CLEAR_FEATURE)
  1858. udc->dev_status &=
  1859. ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1860. else
  1861. udc->dev_status |=
  1862. (1 << USB_DEVICE_REMOTE_WAKEUP);
  1863. uda_remwkp_cgh(udc);
  1864. goto zlp_send;
  1865. case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
  1866. tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
  1867. if ((wValue != USB_ENDPOINT_HALT) ||
  1868. (tmp >= NUM_ENDPOINTS))
  1869. break;
  1870. /* Find hardware endpoint from logical endpoint */
  1871. ep = &udc->ep[tmp];
  1872. tmp = ep->hwep_num;
  1873. if (tmp == 0)
  1874. break;
  1875. if (req == USB_REQ_SET_FEATURE)
  1876. udc_stall_hwep(udc, tmp);
  1877. else if (!ep->wedge)
  1878. udc_clrstall_hwep(udc, tmp);
  1879. goto zlp_send;
  1880. default:
  1881. break;
  1882. }
  1883. case USB_REQ_SET_ADDRESS:
  1884. if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
  1885. udc_set_address(udc, wValue);
  1886. goto zlp_send;
  1887. }
  1888. break;
  1889. case USB_REQ_GET_STATUS:
  1890. udc_get_status(udc, reqtype, wIndex);
  1891. return;
  1892. default:
  1893. break; /* Let GadgetFS handle the descriptor instead */
  1894. }
  1895. if (likely(udc->driver)) {
  1896. /* device-2-host (IN) or no data setup command, process
  1897. * immediately */
  1898. spin_unlock(&udc->lock);
  1899. i = udc->driver->setup(&udc->gadget, &ctrlpkt);
  1900. spin_lock(&udc->lock);
  1901. if (req == USB_REQ_SET_CONFIGURATION) {
  1902. /* Configuration is set after endpoints are realized */
  1903. if (wValue) {
  1904. /* Set configuration */
  1905. udc_set_device_configured(udc);
  1906. udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
  1907. DAT_WR_BYTE(AP_CLK |
  1908. INAK_BI | INAK_II));
  1909. } else {
  1910. /* Clear configuration */
  1911. udc_set_device_unconfigured(udc);
  1912. /* Disable NAK interrupts */
  1913. udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
  1914. DAT_WR_BYTE(AP_CLK));
  1915. }
  1916. }
  1917. if (i < 0) {
  1918. /* setup processing failed, force stall */
  1919. dev_dbg(udc->dev,
  1920. "req %02x.%02x protocol STALL; stat %d\n",
  1921. reqtype, req, i);
  1922. udc->ep0state = WAIT_FOR_SETUP;
  1923. goto stall;
  1924. }
  1925. }
  1926. if (!ep0->is_in)
  1927. udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
  1928. return;
  1929. stall:
  1930. udc_stall_hwep(udc, EP_IN);
  1931. return;
  1932. zlp_send:
  1933. udc_ep0_send_zlp(udc);
  1934. return;
  1935. }
  1936. /* IN endpoint 0 transfer */
  1937. static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
  1938. {
  1939. struct lpc32xx_ep *ep0 = &udc->ep[0];
  1940. u32 epstatus;
  1941. /* Clear EP interrupt */
  1942. epstatus = udc_clearep_getsts(udc, EP_IN);
  1943. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1944. ep0->totalints++;
  1945. #endif
  1946. /* Stalled? Clear stall and reset buffers */
  1947. if (epstatus & EP_SEL_ST) {
  1948. udc_clrstall_hwep(udc, EP_IN);
  1949. nuke(ep0, -ECONNABORTED);
  1950. udc->ep0state = WAIT_FOR_SETUP;
  1951. return;
  1952. }
  1953. /* Is a buffer available? */
  1954. if (!(epstatus & EP_SEL_F)) {
  1955. /* Handle based on current state */
  1956. if (udc->ep0state == DATA_IN)
  1957. udc_ep0_in_req(udc);
  1958. else {
  1959. /* Unknown state for EP0 oe end of DATA IN phase */
  1960. nuke(ep0, -ECONNABORTED);
  1961. udc->ep0state = WAIT_FOR_SETUP;
  1962. }
  1963. }
  1964. }
  1965. /* OUT endpoint 0 transfer */
  1966. static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
  1967. {
  1968. struct lpc32xx_ep *ep0 = &udc->ep[0];
  1969. u32 epstatus;
  1970. /* Clear EP interrupt */
  1971. epstatus = udc_clearep_getsts(udc, EP_OUT);
  1972. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1973. ep0->totalints++;
  1974. #endif
  1975. /* Stalled? */
  1976. if (epstatus & EP_SEL_ST) {
  1977. udc_clrstall_hwep(udc, EP_OUT);
  1978. nuke(ep0, -ECONNABORTED);
  1979. udc->ep0state = WAIT_FOR_SETUP;
  1980. return;
  1981. }
  1982. /* A NAK may occur if a packet couldn't be received yet */
  1983. if (epstatus & EP_SEL_EPN)
  1984. return;
  1985. /* Setup packet incoming? */
  1986. if (epstatus & EP_SEL_STP) {
  1987. nuke(ep0, 0);
  1988. udc->ep0state = WAIT_FOR_SETUP;
  1989. }
  1990. /* Data available? */
  1991. if (epstatus & EP_SEL_F)
  1992. /* Handle based on current state */
  1993. switch (udc->ep0state) {
  1994. case WAIT_FOR_SETUP:
  1995. udc_handle_ep0_setup(udc);
  1996. break;
  1997. case DATA_OUT:
  1998. udc_ep0_out_req(udc);
  1999. break;
  2000. default:
  2001. /* Unknown state for EP0 */
  2002. nuke(ep0, -ECONNABORTED);
  2003. udc->ep0state = WAIT_FOR_SETUP;
  2004. }
  2005. }
  2006. /* Must be called without lock */
  2007. static int lpc32xx_get_frame(struct usb_gadget *gadget)
  2008. {
  2009. int frame;
  2010. unsigned long flags;
  2011. struct lpc32xx_udc *udc = to_udc(gadget);
  2012. if (!udc->clocked)
  2013. return -EINVAL;
  2014. spin_lock_irqsave(&udc->lock, flags);
  2015. frame = (int) udc_get_current_frame(udc);
  2016. spin_unlock_irqrestore(&udc->lock, flags);
  2017. return frame;
  2018. }
  2019. static int lpc32xx_wakeup(struct usb_gadget *gadget)
  2020. {
  2021. return -ENOTSUPP;
  2022. }
  2023. static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
  2024. {
  2025. gadget->is_selfpowered = (is_on != 0);
  2026. return 0;
  2027. }
  2028. /*
  2029. * vbus is here! turn everything on that's ready
  2030. * Must be called without lock
  2031. */
  2032. static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
  2033. {
  2034. unsigned long flags;
  2035. struct lpc32xx_udc *udc = to_udc(gadget);
  2036. spin_lock_irqsave(&udc->lock, flags);
  2037. /* Doesn't need lock */
  2038. if (udc->driver) {
  2039. udc_clk_set(udc, 1);
  2040. udc_enable(udc);
  2041. pullup(udc, is_active);
  2042. } else {
  2043. stop_activity(udc);
  2044. pullup(udc, 0);
  2045. spin_unlock_irqrestore(&udc->lock, flags);
  2046. /*
  2047. * Wait for all the endpoints to disable,
  2048. * before disabling clocks. Don't wait if
  2049. * endpoints are not enabled.
  2050. */
  2051. if (atomic_read(&udc->enabled_ep_cnt))
  2052. wait_event_interruptible(udc->ep_disable_wait_queue,
  2053. (atomic_read(&udc->enabled_ep_cnt) == 0));
  2054. spin_lock_irqsave(&udc->lock, flags);
  2055. udc_clk_set(udc, 0);
  2056. }
  2057. spin_unlock_irqrestore(&udc->lock, flags);
  2058. return 0;
  2059. }
  2060. /* Can be called with or without lock */
  2061. static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
  2062. {
  2063. struct lpc32xx_udc *udc = to_udc(gadget);
  2064. /* Doesn't need lock */
  2065. pullup(udc, is_on);
  2066. return 0;
  2067. }
  2068. static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
  2069. static int lpc32xx_stop(struct usb_gadget *);
  2070. static const struct usb_gadget_ops lpc32xx_udc_ops = {
  2071. .get_frame = lpc32xx_get_frame,
  2072. .wakeup = lpc32xx_wakeup,
  2073. .set_selfpowered = lpc32xx_set_selfpowered,
  2074. .vbus_session = lpc32xx_vbus_session,
  2075. .pullup = lpc32xx_pullup,
  2076. .udc_start = lpc32xx_start,
  2077. .udc_stop = lpc32xx_stop,
  2078. };
  2079. static void nop_release(struct device *dev)
  2080. {
  2081. /* nothing to free */
  2082. }
  2083. static const struct lpc32xx_udc controller_template = {
  2084. .gadget = {
  2085. .ops = &lpc32xx_udc_ops,
  2086. .name = driver_name,
  2087. .dev = {
  2088. .init_name = "gadget",
  2089. .release = nop_release,
  2090. }
  2091. },
  2092. .ep[0] = {
  2093. .ep = {
  2094. .name = "ep0",
  2095. .ops = &lpc32xx_ep_ops,
  2096. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
  2097. USB_EP_CAPS_DIR_ALL),
  2098. },
  2099. .maxpacket = 64,
  2100. .hwep_num_base = 0,
  2101. .hwep_num = 0, /* Can be 0 or 1, has special handling */
  2102. .lep = 0,
  2103. .eptype = EP_CTL_TYPE,
  2104. },
  2105. .ep[1] = {
  2106. .ep = {
  2107. .name = "ep1-int",
  2108. .ops = &lpc32xx_ep_ops,
  2109. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
  2110. USB_EP_CAPS_DIR_ALL),
  2111. },
  2112. .maxpacket = 64,
  2113. .hwep_num_base = 2,
  2114. .hwep_num = 0, /* 2 or 3, will be set later */
  2115. .lep = 1,
  2116. .eptype = EP_INT_TYPE,
  2117. },
  2118. .ep[2] = {
  2119. .ep = {
  2120. .name = "ep2-bulk",
  2121. .ops = &lpc32xx_ep_ops,
  2122. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  2123. USB_EP_CAPS_DIR_ALL),
  2124. },
  2125. .maxpacket = 64,
  2126. .hwep_num_base = 4,
  2127. .hwep_num = 0, /* 4 or 5, will be set later */
  2128. .lep = 2,
  2129. .eptype = EP_BLK_TYPE,
  2130. },
  2131. .ep[3] = {
  2132. .ep = {
  2133. .name = "ep3-iso",
  2134. .ops = &lpc32xx_ep_ops,
  2135. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
  2136. USB_EP_CAPS_DIR_ALL),
  2137. },
  2138. .maxpacket = 1023,
  2139. .hwep_num_base = 6,
  2140. .hwep_num = 0, /* 6 or 7, will be set later */
  2141. .lep = 3,
  2142. .eptype = EP_ISO_TYPE,
  2143. },
  2144. .ep[4] = {
  2145. .ep = {
  2146. .name = "ep4-int",
  2147. .ops = &lpc32xx_ep_ops,
  2148. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
  2149. USB_EP_CAPS_DIR_ALL),
  2150. },
  2151. .maxpacket = 64,
  2152. .hwep_num_base = 8,
  2153. .hwep_num = 0, /* 8 or 9, will be set later */
  2154. .lep = 4,
  2155. .eptype = EP_INT_TYPE,
  2156. },
  2157. .ep[5] = {
  2158. .ep = {
  2159. .name = "ep5-bulk",
  2160. .ops = &lpc32xx_ep_ops,
  2161. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  2162. USB_EP_CAPS_DIR_ALL),
  2163. },
  2164. .maxpacket = 64,
  2165. .hwep_num_base = 10,
  2166. .hwep_num = 0, /* 10 or 11, will be set later */
  2167. .lep = 5,
  2168. .eptype = EP_BLK_TYPE,
  2169. },
  2170. .ep[6] = {
  2171. .ep = {
  2172. .name = "ep6-iso",
  2173. .ops = &lpc32xx_ep_ops,
  2174. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
  2175. USB_EP_CAPS_DIR_ALL),
  2176. },
  2177. .maxpacket = 1023,
  2178. .hwep_num_base = 12,
  2179. .hwep_num = 0, /* 12 or 13, will be set later */
  2180. .lep = 6,
  2181. .eptype = EP_ISO_TYPE,
  2182. },
  2183. .ep[7] = {
  2184. .ep = {
  2185. .name = "ep7-int",
  2186. .ops = &lpc32xx_ep_ops,
  2187. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
  2188. USB_EP_CAPS_DIR_ALL),
  2189. },
  2190. .maxpacket = 64,
  2191. .hwep_num_base = 14,
  2192. .hwep_num = 0,
  2193. .lep = 7,
  2194. .eptype = EP_INT_TYPE,
  2195. },
  2196. .ep[8] = {
  2197. .ep = {
  2198. .name = "ep8-bulk",
  2199. .ops = &lpc32xx_ep_ops,
  2200. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  2201. USB_EP_CAPS_DIR_ALL),
  2202. },
  2203. .maxpacket = 64,
  2204. .hwep_num_base = 16,
  2205. .hwep_num = 0,
  2206. .lep = 8,
  2207. .eptype = EP_BLK_TYPE,
  2208. },
  2209. .ep[9] = {
  2210. .ep = {
  2211. .name = "ep9-iso",
  2212. .ops = &lpc32xx_ep_ops,
  2213. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
  2214. USB_EP_CAPS_DIR_ALL),
  2215. },
  2216. .maxpacket = 1023,
  2217. .hwep_num_base = 18,
  2218. .hwep_num = 0,
  2219. .lep = 9,
  2220. .eptype = EP_ISO_TYPE,
  2221. },
  2222. .ep[10] = {
  2223. .ep = {
  2224. .name = "ep10-int",
  2225. .ops = &lpc32xx_ep_ops,
  2226. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
  2227. USB_EP_CAPS_DIR_ALL),
  2228. },
  2229. .maxpacket = 64,
  2230. .hwep_num_base = 20,
  2231. .hwep_num = 0,
  2232. .lep = 10,
  2233. .eptype = EP_INT_TYPE,
  2234. },
  2235. .ep[11] = {
  2236. .ep = {
  2237. .name = "ep11-bulk",
  2238. .ops = &lpc32xx_ep_ops,
  2239. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  2240. USB_EP_CAPS_DIR_ALL),
  2241. },
  2242. .maxpacket = 64,
  2243. .hwep_num_base = 22,
  2244. .hwep_num = 0,
  2245. .lep = 11,
  2246. .eptype = EP_BLK_TYPE,
  2247. },
  2248. .ep[12] = {
  2249. .ep = {
  2250. .name = "ep12-iso",
  2251. .ops = &lpc32xx_ep_ops,
  2252. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
  2253. USB_EP_CAPS_DIR_ALL),
  2254. },
  2255. .maxpacket = 1023,
  2256. .hwep_num_base = 24,
  2257. .hwep_num = 0,
  2258. .lep = 12,
  2259. .eptype = EP_ISO_TYPE,
  2260. },
  2261. .ep[13] = {
  2262. .ep = {
  2263. .name = "ep13-int",
  2264. .ops = &lpc32xx_ep_ops,
  2265. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
  2266. USB_EP_CAPS_DIR_ALL),
  2267. },
  2268. .maxpacket = 64,
  2269. .hwep_num_base = 26,
  2270. .hwep_num = 0,
  2271. .lep = 13,
  2272. .eptype = EP_INT_TYPE,
  2273. },
  2274. .ep[14] = {
  2275. .ep = {
  2276. .name = "ep14-bulk",
  2277. .ops = &lpc32xx_ep_ops,
  2278. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  2279. USB_EP_CAPS_DIR_ALL),
  2280. },
  2281. .maxpacket = 64,
  2282. .hwep_num_base = 28,
  2283. .hwep_num = 0,
  2284. .lep = 14,
  2285. .eptype = EP_BLK_TYPE,
  2286. },
  2287. .ep[15] = {
  2288. .ep = {
  2289. .name = "ep15-bulk",
  2290. .ops = &lpc32xx_ep_ops,
  2291. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  2292. USB_EP_CAPS_DIR_ALL),
  2293. },
  2294. .maxpacket = 1023,
  2295. .hwep_num_base = 30,
  2296. .hwep_num = 0,
  2297. .lep = 15,
  2298. .eptype = EP_BLK_TYPE,
  2299. },
  2300. };
  2301. /* ISO and status interrupts */
  2302. static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
  2303. {
  2304. u32 tmp, devstat;
  2305. struct lpc32xx_udc *udc = _udc;
  2306. spin_lock(&udc->lock);
  2307. /* Read the device status register */
  2308. devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
  2309. devstat &= ~USBD_EP_FAST;
  2310. writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
  2311. devstat = devstat & udc->enabled_devints;
  2312. /* Device specific handling needed? */
  2313. if (devstat & USBD_DEV_STAT)
  2314. udc_handle_dev(udc);
  2315. /* Start of frame? (devstat & FRAME_INT):
  2316. * The frame interrupt isn't really needed for ISO support,
  2317. * as the driver will queue the necessary packets */
  2318. /* Error? */
  2319. if (devstat & ERR_INT) {
  2320. /* All types of errors, from cable removal during transfer to
  2321. * misc protocol and bit errors. These are mostly for just info,
  2322. * as the USB hardware will work around these. If these errors
  2323. * happen alot, something is wrong. */
  2324. udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
  2325. tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
  2326. dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
  2327. }
  2328. spin_unlock(&udc->lock);
  2329. return IRQ_HANDLED;
  2330. }
  2331. /* EP interrupts */
  2332. static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
  2333. {
  2334. u32 tmp;
  2335. struct lpc32xx_udc *udc = _udc;
  2336. spin_lock(&udc->lock);
  2337. /* Read the device status register */
  2338. writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
  2339. /* Endpoints */
  2340. tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
  2341. /* Special handling for EP0 */
  2342. if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
  2343. /* Handle EP0 IN */
  2344. if (tmp & (EP_MASK_SEL(0, EP_IN)))
  2345. udc_handle_ep0_in(udc);
  2346. /* Handle EP0 OUT */
  2347. if (tmp & (EP_MASK_SEL(0, EP_OUT)))
  2348. udc_handle_ep0_out(udc);
  2349. }
  2350. /* All other EPs */
  2351. if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
  2352. int i;
  2353. /* Handle other EP interrupts */
  2354. for (i = 1; i < NUM_ENDPOINTS; i++) {
  2355. if (tmp & (1 << udc->ep[i].hwep_num))
  2356. udc_handle_eps(udc, &udc->ep[i]);
  2357. }
  2358. }
  2359. spin_unlock(&udc->lock);
  2360. return IRQ_HANDLED;
  2361. }
  2362. static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
  2363. {
  2364. struct lpc32xx_udc *udc = _udc;
  2365. int i;
  2366. u32 tmp;
  2367. spin_lock(&udc->lock);
  2368. /* Handle EP DMA EOT interrupts */
  2369. tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
  2370. (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
  2371. readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
  2372. readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
  2373. for (i = 1; i < NUM_ENDPOINTS; i++) {
  2374. if (tmp & (1 << udc->ep[i].hwep_num))
  2375. udc_handle_dma_ep(udc, &udc->ep[i]);
  2376. }
  2377. spin_unlock(&udc->lock);
  2378. return IRQ_HANDLED;
  2379. }
  2380. /*
  2381. *
  2382. * VBUS detection, pullup handler, and Gadget cable state notification
  2383. *
  2384. */
  2385. static void vbus_work(struct work_struct *work)
  2386. {
  2387. u8 value;
  2388. struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
  2389. vbus_job);
  2390. if (udc->enabled != 0) {
  2391. /* Discharge VBUS real quick */
  2392. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  2393. ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
  2394. /* Give VBUS some time (100mS) to discharge */
  2395. msleep(100);
  2396. /* Disable VBUS discharge resistor */
  2397. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  2398. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  2399. OTG1_VBUS_DISCHRG);
  2400. /* Clear interrupt */
  2401. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  2402. ISP1301_I2C_INTERRUPT_LATCH |
  2403. ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  2404. /* Get the VBUS status from the transceiver */
  2405. value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
  2406. ISP1301_I2C_INTERRUPT_SOURCE);
  2407. /* VBUS on or off? */
  2408. if (value & INT_SESS_VLD)
  2409. udc->vbus = 1;
  2410. else
  2411. udc->vbus = 0;
  2412. /* VBUS changed? */
  2413. if (udc->last_vbus != udc->vbus) {
  2414. udc->last_vbus = udc->vbus;
  2415. lpc32xx_vbus_session(&udc->gadget, udc->vbus);
  2416. }
  2417. }
  2418. /* Re-enable after completion */
  2419. enable_irq(udc->udp_irq[IRQ_USB_ATX]);
  2420. }
  2421. static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
  2422. {
  2423. struct lpc32xx_udc *udc = _udc;
  2424. /* Defer handling of VBUS IRQ to work queue */
  2425. disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
  2426. schedule_work(&udc->vbus_job);
  2427. return IRQ_HANDLED;
  2428. }
  2429. static int lpc32xx_start(struct usb_gadget *gadget,
  2430. struct usb_gadget_driver *driver)
  2431. {
  2432. struct lpc32xx_udc *udc = to_udc(gadget);
  2433. int i;
  2434. if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
  2435. dev_err(udc->dev, "bad parameter.\n");
  2436. return -EINVAL;
  2437. }
  2438. if (udc->driver) {
  2439. dev_err(udc->dev, "UDC already has a gadget driver\n");
  2440. return -EBUSY;
  2441. }
  2442. udc->driver = driver;
  2443. udc->gadget.dev.of_node = udc->dev->of_node;
  2444. udc->enabled = 1;
  2445. udc->gadget.is_selfpowered = 1;
  2446. udc->vbus = 0;
  2447. /* Force VBUS process once to check for cable insertion */
  2448. udc->last_vbus = udc->vbus = 0;
  2449. schedule_work(&udc->vbus_job);
  2450. /* Do not re-enable ATX IRQ (3) */
  2451. for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
  2452. enable_irq(udc->udp_irq[i]);
  2453. return 0;
  2454. }
  2455. static int lpc32xx_stop(struct usb_gadget *gadget)
  2456. {
  2457. int i;
  2458. struct lpc32xx_udc *udc = to_udc(gadget);
  2459. for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
  2460. disable_irq(udc->udp_irq[i]);
  2461. if (udc->clocked) {
  2462. spin_lock(&udc->lock);
  2463. stop_activity(udc);
  2464. spin_unlock(&udc->lock);
  2465. /*
  2466. * Wait for all the endpoints to disable,
  2467. * before disabling clocks. Don't wait if
  2468. * endpoints are not enabled.
  2469. */
  2470. if (atomic_read(&udc->enabled_ep_cnt))
  2471. wait_event_interruptible(udc->ep_disable_wait_queue,
  2472. (atomic_read(&udc->enabled_ep_cnt) == 0));
  2473. spin_lock(&udc->lock);
  2474. udc_clk_set(udc, 0);
  2475. spin_unlock(&udc->lock);
  2476. }
  2477. udc->enabled = 0;
  2478. udc->driver = NULL;
  2479. return 0;
  2480. }
  2481. static void lpc32xx_udc_shutdown(struct platform_device *dev)
  2482. {
  2483. /* Force disconnect on reboot */
  2484. struct lpc32xx_udc *udc = platform_get_drvdata(dev);
  2485. pullup(udc, 0);
  2486. }
  2487. /*
  2488. * Callbacks to be overridden by options passed via OF (TODO)
  2489. */
  2490. static void lpc32xx_usbd_conn_chg(int conn)
  2491. {
  2492. /* Do nothing, it might be nice to enable an LED
  2493. * based on conn state being !0 */
  2494. }
  2495. static void lpc32xx_usbd_susp_chg(int susp)
  2496. {
  2497. /* Device suspend if susp != 0 */
  2498. }
  2499. static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
  2500. {
  2501. /* Enable or disable USB remote wakeup */
  2502. }
  2503. struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
  2504. .vbus_drv_pol = 0,
  2505. .conn_chgb = &lpc32xx_usbd_conn_chg,
  2506. .susp_chgb = &lpc32xx_usbd_susp_chg,
  2507. .rmwk_chgb = &lpc32xx_rmwkup_chg,
  2508. };
  2509. static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
  2510. static int lpc32xx_udc_probe(struct platform_device *pdev)
  2511. {
  2512. struct device *dev = &pdev->dev;
  2513. struct lpc32xx_udc *udc;
  2514. int retval, i;
  2515. struct resource *res;
  2516. dma_addr_t dma_handle;
  2517. struct device_node *isp1301_node;
  2518. udc = kmemdup(&controller_template, sizeof(*udc), GFP_KERNEL);
  2519. if (!udc)
  2520. return -ENOMEM;
  2521. for (i = 0; i <= 15; i++)
  2522. udc->ep[i].udc = udc;
  2523. udc->gadget.ep0 = &udc->ep[0].ep;
  2524. /* init software state */
  2525. udc->gadget.dev.parent = dev;
  2526. udc->pdev = pdev;
  2527. udc->dev = &pdev->dev;
  2528. udc->enabled = 0;
  2529. if (pdev->dev.of_node) {
  2530. isp1301_node = of_parse_phandle(pdev->dev.of_node,
  2531. "transceiver", 0);
  2532. } else {
  2533. isp1301_node = NULL;
  2534. }
  2535. udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
  2536. if (!udc->isp1301_i2c_client) {
  2537. retval = -EPROBE_DEFER;
  2538. goto phy_fail;
  2539. }
  2540. dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
  2541. udc->isp1301_i2c_client->addr);
  2542. pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
  2543. retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  2544. if (retval)
  2545. goto resource_fail;
  2546. udc->board = &lpc32xx_usbddata;
  2547. /*
  2548. * Resources are mapped as follows:
  2549. * IORESOURCE_MEM, base address and size of USB space
  2550. * IORESOURCE_IRQ, USB device low priority interrupt number
  2551. * IORESOURCE_IRQ, USB device high priority interrupt number
  2552. * IORESOURCE_IRQ, USB device interrupt number
  2553. * IORESOURCE_IRQ, USB transceiver interrupt number
  2554. */
  2555. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2556. if (!res) {
  2557. retval = -ENXIO;
  2558. goto resource_fail;
  2559. }
  2560. spin_lock_init(&udc->lock);
  2561. /* Get IRQs */
  2562. for (i = 0; i < 4; i++) {
  2563. udc->udp_irq[i] = platform_get_irq(pdev, i);
  2564. if (udc->udp_irq[i] < 0) {
  2565. dev_err(udc->dev,
  2566. "irq resource %d not available!\n", i);
  2567. retval = udc->udp_irq[i];
  2568. goto irq_fail;
  2569. }
  2570. }
  2571. udc->io_p_start = res->start;
  2572. udc->io_p_size = resource_size(res);
  2573. if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
  2574. dev_err(udc->dev, "someone's using UDC memory\n");
  2575. retval = -EBUSY;
  2576. goto request_mem_region_fail;
  2577. }
  2578. udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
  2579. if (!udc->udp_baseaddr) {
  2580. retval = -ENOMEM;
  2581. dev_err(udc->dev, "IO map failure\n");
  2582. goto io_map_fail;
  2583. }
  2584. /* Get USB device clock */
  2585. udc->usb_slv_clk = clk_get(&pdev->dev, NULL);
  2586. if (IS_ERR(udc->usb_slv_clk)) {
  2587. dev_err(udc->dev, "failed to acquire USB device clock\n");
  2588. retval = PTR_ERR(udc->usb_slv_clk);
  2589. goto usb_clk_get_fail;
  2590. }
  2591. /* Enable USB device clock */
  2592. retval = clk_prepare_enable(udc->usb_slv_clk);
  2593. if (retval < 0) {
  2594. dev_err(udc->dev, "failed to start USB device clock\n");
  2595. goto usb_clk_enable_fail;
  2596. }
  2597. /* Setup deferred workqueue data */
  2598. udc->poweron = udc->pullup = 0;
  2599. INIT_WORK(&udc->pullup_job, pullup_work);
  2600. INIT_WORK(&udc->vbus_job, vbus_work);
  2601. #ifdef CONFIG_PM
  2602. INIT_WORK(&udc->power_job, power_work);
  2603. #endif
  2604. /* All clocks are now on */
  2605. udc->clocked = 1;
  2606. isp1301_udc_configure(udc);
  2607. /* Allocate memory for the UDCA */
  2608. udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
  2609. &dma_handle,
  2610. (GFP_KERNEL | GFP_DMA));
  2611. if (!udc->udca_v_base) {
  2612. dev_err(udc->dev, "error getting UDCA region\n");
  2613. retval = -ENOMEM;
  2614. goto i2c_fail;
  2615. }
  2616. udc->udca_p_base = dma_handle;
  2617. dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
  2618. UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
  2619. /* Setup the DD DMA memory pool */
  2620. udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
  2621. sizeof(struct lpc32xx_usbd_dd_gad),
  2622. sizeof(u32), 0);
  2623. if (!udc->dd_cache) {
  2624. dev_err(udc->dev, "error getting DD DMA region\n");
  2625. retval = -ENOMEM;
  2626. goto dma_alloc_fail;
  2627. }
  2628. /* Clear USB peripheral and initialize gadget endpoints */
  2629. udc_disable(udc);
  2630. udc_reinit(udc);
  2631. /* Request IRQs - low and high priority USB device IRQs are routed to
  2632. * the same handler, while the DMA interrupt is routed elsewhere */
  2633. retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
  2634. 0, "udc_lp", udc);
  2635. if (retval < 0) {
  2636. dev_err(udc->dev, "LP request irq %d failed\n",
  2637. udc->udp_irq[IRQ_USB_LP]);
  2638. goto irq_lp_fail;
  2639. }
  2640. retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
  2641. 0, "udc_hp", udc);
  2642. if (retval < 0) {
  2643. dev_err(udc->dev, "HP request irq %d failed\n",
  2644. udc->udp_irq[IRQ_USB_HP]);
  2645. goto irq_hp_fail;
  2646. }
  2647. retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
  2648. lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
  2649. if (retval < 0) {
  2650. dev_err(udc->dev, "DEV request irq %d failed\n",
  2651. udc->udp_irq[IRQ_USB_DEVDMA]);
  2652. goto irq_dev_fail;
  2653. }
  2654. /* The transceiver interrupt is used for VBUS detection and will
  2655. kick off the VBUS handler function */
  2656. retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
  2657. 0, "udc_otg", udc);
  2658. if (retval < 0) {
  2659. dev_err(udc->dev, "VBUS request irq %d failed\n",
  2660. udc->udp_irq[IRQ_USB_ATX]);
  2661. goto irq_xcvr_fail;
  2662. }
  2663. /* Initialize wait queue */
  2664. init_waitqueue_head(&udc->ep_disable_wait_queue);
  2665. atomic_set(&udc->enabled_ep_cnt, 0);
  2666. /* Keep all IRQs disabled until GadgetFS starts up */
  2667. for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
  2668. disable_irq(udc->udp_irq[i]);
  2669. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2670. if (retval < 0)
  2671. goto add_gadget_fail;
  2672. dev_set_drvdata(dev, udc);
  2673. device_init_wakeup(dev, 1);
  2674. create_debug_file(udc);
  2675. /* Disable clocks for now */
  2676. udc_clk_set(udc, 0);
  2677. dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
  2678. return 0;
  2679. add_gadget_fail:
  2680. free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
  2681. irq_xcvr_fail:
  2682. free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
  2683. irq_dev_fail:
  2684. free_irq(udc->udp_irq[IRQ_USB_HP], udc);
  2685. irq_hp_fail:
  2686. free_irq(udc->udp_irq[IRQ_USB_LP], udc);
  2687. irq_lp_fail:
  2688. dma_pool_destroy(udc->dd_cache);
  2689. dma_alloc_fail:
  2690. dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
  2691. udc->udca_v_base, udc->udca_p_base);
  2692. i2c_fail:
  2693. clk_disable_unprepare(udc->usb_slv_clk);
  2694. usb_clk_enable_fail:
  2695. clk_put(udc->usb_slv_clk);
  2696. usb_clk_get_fail:
  2697. iounmap(udc->udp_baseaddr);
  2698. io_map_fail:
  2699. release_mem_region(udc->io_p_start, udc->io_p_size);
  2700. dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
  2701. request_mem_region_fail:
  2702. irq_fail:
  2703. resource_fail:
  2704. phy_fail:
  2705. kfree(udc);
  2706. return retval;
  2707. }
  2708. static int lpc32xx_udc_remove(struct platform_device *pdev)
  2709. {
  2710. struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
  2711. usb_del_gadget_udc(&udc->gadget);
  2712. if (udc->driver)
  2713. return -EBUSY;
  2714. udc_clk_set(udc, 1);
  2715. udc_disable(udc);
  2716. pullup(udc, 0);
  2717. free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
  2718. device_init_wakeup(&pdev->dev, 0);
  2719. remove_debug_file(udc);
  2720. dma_pool_destroy(udc->dd_cache);
  2721. dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
  2722. udc->udca_v_base, udc->udca_p_base);
  2723. free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
  2724. free_irq(udc->udp_irq[IRQ_USB_HP], udc);
  2725. free_irq(udc->udp_irq[IRQ_USB_LP], udc);
  2726. clk_disable_unprepare(udc->usb_slv_clk);
  2727. clk_put(udc->usb_slv_clk);
  2728. iounmap(udc->udp_baseaddr);
  2729. release_mem_region(udc->io_p_start, udc->io_p_size);
  2730. kfree(udc);
  2731. return 0;
  2732. }
  2733. #ifdef CONFIG_PM
  2734. static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
  2735. {
  2736. struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
  2737. if (udc->clocked) {
  2738. /* Power down ISP */
  2739. udc->poweron = 0;
  2740. isp1301_set_powerstate(udc, 0);
  2741. /* Disable clocking */
  2742. udc_clk_set(udc, 0);
  2743. /* Keep clock flag on, so we know to re-enable clocks
  2744. on resume */
  2745. udc->clocked = 1;
  2746. /* Kill global USB clock */
  2747. clk_disable_unprepare(udc->usb_slv_clk);
  2748. }
  2749. return 0;
  2750. }
  2751. static int lpc32xx_udc_resume(struct platform_device *pdev)
  2752. {
  2753. struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
  2754. if (udc->clocked) {
  2755. /* Enable global USB clock */
  2756. clk_prepare_enable(udc->usb_slv_clk);
  2757. /* Enable clocking */
  2758. udc_clk_set(udc, 1);
  2759. /* ISP back to normal power mode */
  2760. udc->poweron = 1;
  2761. isp1301_set_powerstate(udc, 1);
  2762. }
  2763. return 0;
  2764. }
  2765. #else
  2766. #define lpc32xx_udc_suspend NULL
  2767. #define lpc32xx_udc_resume NULL
  2768. #endif
  2769. #ifdef CONFIG_OF
  2770. static const struct of_device_id lpc32xx_udc_of_match[] = {
  2771. { .compatible = "nxp,lpc3220-udc", },
  2772. { },
  2773. };
  2774. MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
  2775. #endif
  2776. static struct platform_driver lpc32xx_udc_driver = {
  2777. .remove = lpc32xx_udc_remove,
  2778. .shutdown = lpc32xx_udc_shutdown,
  2779. .suspend = lpc32xx_udc_suspend,
  2780. .resume = lpc32xx_udc_resume,
  2781. .driver = {
  2782. .name = (char *) driver_name,
  2783. .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
  2784. },
  2785. };
  2786. module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
  2787. MODULE_DESCRIPTION("LPC32XX udc driver");
  2788. MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
  2789. MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
  2790. MODULE_LICENSE("GPL");
  2791. MODULE_ALIAS("platform:lpc32xx_udc");