omap_udc.c 76 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
  4. *
  5. * Copyright (C) 2004 Texas Instruments, Inc.
  6. * Copyright (C) 2004-2005 David Brownell
  7. *
  8. * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
  9. */
  10. #undef DEBUG
  11. #undef VERBOSE
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/ioport.h>
  15. #include <linux/types.h>
  16. #include <linux/errno.h>
  17. #include <linux/delay.h>
  18. #include <linux/slab.h>
  19. #include <linux/timer.h>
  20. #include <linux/list.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/proc_fs.h>
  23. #include <linux/mm.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include <linux/usb/otg.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/clk.h>
  31. #include <linux/err.h>
  32. #include <linux/prefetch.h>
  33. #include <linux/io.h>
  34. #include <asm/byteorder.h>
  35. #include <asm/irq.h>
  36. #include <asm/unaligned.h>
  37. #include <asm/mach-types.h>
  38. #include <linux/omap-dma.h>
  39. #include <mach/usb.h>
  40. #include "omap_udc.h"
  41. #undef USB_TRACE
  42. /* bulk DMA seems to be behaving for both IN and OUT */
  43. #define USE_DMA
  44. /* ISO too */
  45. #define USE_ISO
  46. #define DRIVER_DESC "OMAP UDC driver"
  47. #define DRIVER_VERSION "4 October 2004"
  48. #define OMAP_DMA_USB_W2FC_TX0 29
  49. #define OMAP_DMA_USB_W2FC_RX0 26
  50. /*
  51. * The OMAP UDC needs _very_ early endpoint setup: before enabling the
  52. * D+ pullup to allow enumeration. That's too early for the gadget
  53. * framework to use from usb_endpoint_enable(), which happens after
  54. * enumeration as part of activating an interface. (But if we add an
  55. * optional new "UDC not yet running" state to the gadget driver model,
  56. * even just during driver binding, the endpoint autoconfig logic is the
  57. * natural spot to manufacture new endpoints.)
  58. *
  59. * So instead of using endpoint enable calls to control the hardware setup,
  60. * this driver defines a "fifo mode" parameter. It's used during driver
  61. * initialization to choose among a set of pre-defined endpoint configs.
  62. * See omap_udc_setup() for available modes, or to add others. That code
  63. * lives in an init section, so use this driver as a module if you need
  64. * to change the fifo mode after the kernel boots.
  65. *
  66. * Gadget drivers normally ignore endpoints they don't care about, and
  67. * won't include them in configuration descriptors. That means only
  68. * misbehaving hosts would even notice they exist.
  69. */
  70. #ifdef USE_ISO
  71. static unsigned fifo_mode = 3;
  72. #else
  73. static unsigned fifo_mode;
  74. #endif
  75. /* "modprobe omap_udc fifo_mode=42", or else as a kernel
  76. * boot parameter "omap_udc:fifo_mode=42"
  77. */
  78. module_param(fifo_mode, uint, 0);
  79. MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
  80. #ifdef USE_DMA
  81. static bool use_dma = 1;
  82. /* "modprobe omap_udc use_dma=y", or else as a kernel
  83. * boot parameter "omap_udc:use_dma=y"
  84. */
  85. module_param(use_dma, bool, 0);
  86. MODULE_PARM_DESC(use_dma, "enable/disable DMA");
  87. #else /* !USE_DMA */
  88. /* save a bit of code */
  89. #define use_dma 0
  90. #endif /* !USE_DMA */
  91. static const char driver_name[] = "omap_udc";
  92. static const char driver_desc[] = DRIVER_DESC;
  93. /*-------------------------------------------------------------------------*/
  94. /* there's a notion of "current endpoint" for modifying endpoint
  95. * state, and PIO access to its FIFO.
  96. */
  97. static void use_ep(struct omap_ep *ep, u16 select)
  98. {
  99. u16 num = ep->bEndpointAddress & 0x0f;
  100. if (ep->bEndpointAddress & USB_DIR_IN)
  101. num |= UDC_EP_DIR;
  102. omap_writew(num | select, UDC_EP_NUM);
  103. /* when select, MUST deselect later !! */
  104. }
  105. static inline void deselect_ep(void)
  106. {
  107. u16 w;
  108. w = omap_readw(UDC_EP_NUM);
  109. w &= ~UDC_EP_SEL;
  110. omap_writew(w, UDC_EP_NUM);
  111. /* 6 wait states before TX will happen */
  112. }
  113. static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
  114. /*-------------------------------------------------------------------------*/
  115. static int omap_ep_enable(struct usb_ep *_ep,
  116. const struct usb_endpoint_descriptor *desc)
  117. {
  118. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  119. struct omap_udc *udc;
  120. unsigned long flags;
  121. u16 maxp;
  122. /* catch various bogus parameters */
  123. if (!_ep || !desc
  124. || desc->bDescriptorType != USB_DT_ENDPOINT
  125. || ep->bEndpointAddress != desc->bEndpointAddress
  126. || ep->maxpacket < usb_endpoint_maxp(desc)) {
  127. DBG("%s, bad ep or descriptor\n", __func__);
  128. return -EINVAL;
  129. }
  130. maxp = usb_endpoint_maxp(desc);
  131. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  132. && maxp != ep->maxpacket)
  133. || usb_endpoint_maxp(desc) > ep->maxpacket
  134. || !desc->wMaxPacketSize) {
  135. DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
  136. return -ERANGE;
  137. }
  138. #ifdef USE_ISO
  139. if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
  140. && desc->bInterval != 1)) {
  141. /* hardware wants period = 1; USB allows 2^(Interval-1) */
  142. DBG("%s, unsupported ISO period %dms\n", _ep->name,
  143. 1 << (desc->bInterval - 1));
  144. return -EDOM;
  145. }
  146. #else
  147. if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  148. DBG("%s, ISO nyet\n", _ep->name);
  149. return -EDOM;
  150. }
  151. #endif
  152. /* xfer types must match, except that interrupt ~= bulk */
  153. if (ep->bmAttributes != desc->bmAttributes
  154. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  155. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  156. DBG("%s, %s type mismatch\n", __func__, _ep->name);
  157. return -EINVAL;
  158. }
  159. udc = ep->udc;
  160. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
  161. DBG("%s, bogus device state\n", __func__);
  162. return -ESHUTDOWN;
  163. }
  164. spin_lock_irqsave(&udc->lock, flags);
  165. ep->ep.desc = desc;
  166. ep->irqs = 0;
  167. ep->stopped = 0;
  168. ep->ep.maxpacket = maxp;
  169. /* set endpoint to initial state */
  170. ep->dma_channel = 0;
  171. ep->has_dma = 0;
  172. ep->lch = -1;
  173. use_ep(ep, UDC_EP_SEL);
  174. omap_writew(udc->clr_halt, UDC_CTRL);
  175. ep->ackwait = 0;
  176. deselect_ep();
  177. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
  178. list_add(&ep->iso, &udc->iso);
  179. /* maybe assign a DMA channel to this endpoint */
  180. if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
  181. /* FIXME ISO can dma, but prefers first channel */
  182. dma_channel_claim(ep, 0);
  183. /* PIO OUT may RX packets */
  184. if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
  185. && !ep->has_dma
  186. && !(ep->bEndpointAddress & USB_DIR_IN)) {
  187. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  188. ep->ackwait = 1 + ep->double_buf;
  189. }
  190. spin_unlock_irqrestore(&udc->lock, flags);
  191. VDBG("%s enabled\n", _ep->name);
  192. return 0;
  193. }
  194. static void nuke(struct omap_ep *, int status);
  195. static int omap_ep_disable(struct usb_ep *_ep)
  196. {
  197. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  198. unsigned long flags;
  199. if (!_ep || !ep->ep.desc) {
  200. DBG("%s, %s not enabled\n", __func__,
  201. _ep ? ep->ep.name : NULL);
  202. return -EINVAL;
  203. }
  204. spin_lock_irqsave(&ep->udc->lock, flags);
  205. ep->ep.desc = NULL;
  206. nuke(ep, -ESHUTDOWN);
  207. ep->ep.maxpacket = ep->maxpacket;
  208. ep->has_dma = 0;
  209. omap_writew(UDC_SET_HALT, UDC_CTRL);
  210. list_del_init(&ep->iso);
  211. del_timer(&ep->timer);
  212. spin_unlock_irqrestore(&ep->udc->lock, flags);
  213. VDBG("%s disabled\n", _ep->name);
  214. return 0;
  215. }
  216. /*-------------------------------------------------------------------------*/
  217. static struct usb_request *
  218. omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  219. {
  220. struct omap_req *req;
  221. req = kzalloc(sizeof(*req), gfp_flags);
  222. if (!req)
  223. return NULL;
  224. INIT_LIST_HEAD(&req->queue);
  225. return &req->req;
  226. }
  227. static void
  228. omap_free_request(struct usb_ep *ep, struct usb_request *_req)
  229. {
  230. struct omap_req *req = container_of(_req, struct omap_req, req);
  231. kfree(req);
  232. }
  233. /*-------------------------------------------------------------------------*/
  234. static void
  235. done(struct omap_ep *ep, struct omap_req *req, int status)
  236. {
  237. struct omap_udc *udc = ep->udc;
  238. unsigned stopped = ep->stopped;
  239. list_del_init(&req->queue);
  240. if (req->req.status == -EINPROGRESS)
  241. req->req.status = status;
  242. else
  243. status = req->req.status;
  244. if (use_dma && ep->has_dma)
  245. usb_gadget_unmap_request(&udc->gadget, &req->req,
  246. (ep->bEndpointAddress & USB_DIR_IN));
  247. #ifndef USB_TRACE
  248. if (status && status != -ESHUTDOWN)
  249. #endif
  250. VDBG("complete %s req %p stat %d len %u/%u\n",
  251. ep->ep.name, &req->req, status,
  252. req->req.actual, req->req.length);
  253. /* don't modify queue heads during completion callback */
  254. ep->stopped = 1;
  255. spin_unlock(&ep->udc->lock);
  256. usb_gadget_giveback_request(&ep->ep, &req->req);
  257. spin_lock(&ep->udc->lock);
  258. ep->stopped = stopped;
  259. }
  260. /*-------------------------------------------------------------------------*/
  261. #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
  262. #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
  263. #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
  264. #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
  265. static inline int
  266. write_packet(u8 *buf, struct omap_req *req, unsigned max)
  267. {
  268. unsigned len;
  269. u16 *wp;
  270. len = min(req->req.length - req->req.actual, max);
  271. req->req.actual += len;
  272. max = len;
  273. if (likely((((int)buf) & 1) == 0)) {
  274. wp = (u16 *)buf;
  275. while (max >= 2) {
  276. omap_writew(*wp++, UDC_DATA);
  277. max -= 2;
  278. }
  279. buf = (u8 *)wp;
  280. }
  281. while (max--)
  282. omap_writeb(*buf++, UDC_DATA);
  283. return len;
  284. }
  285. /* FIXME change r/w fifo calling convention */
  286. /* return: 0 = still running, 1 = completed, negative = errno */
  287. static int write_fifo(struct omap_ep *ep, struct omap_req *req)
  288. {
  289. u8 *buf;
  290. unsigned count;
  291. int is_last;
  292. u16 ep_stat;
  293. buf = req->req.buf + req->req.actual;
  294. prefetch(buf);
  295. /* PIO-IN isn't double buffered except for iso */
  296. ep_stat = omap_readw(UDC_STAT_FLG);
  297. if (ep_stat & UDC_FIFO_UNWRITABLE)
  298. return 0;
  299. count = ep->ep.maxpacket;
  300. count = write_packet(buf, req, count);
  301. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  302. ep->ackwait = 1;
  303. /* last packet is often short (sometimes a zlp) */
  304. if (count != ep->ep.maxpacket)
  305. is_last = 1;
  306. else if (req->req.length == req->req.actual
  307. && !req->req.zero)
  308. is_last = 1;
  309. else
  310. is_last = 0;
  311. /* NOTE: requests complete when all IN data is in a
  312. * FIFO (or sometimes later, if a zlp was needed).
  313. * Use usb_ep_fifo_status() where needed.
  314. */
  315. if (is_last)
  316. done(ep, req, 0);
  317. return is_last;
  318. }
  319. static inline int
  320. read_packet(u8 *buf, struct omap_req *req, unsigned avail)
  321. {
  322. unsigned len;
  323. u16 *wp;
  324. len = min(req->req.length - req->req.actual, avail);
  325. req->req.actual += len;
  326. avail = len;
  327. if (likely((((int)buf) & 1) == 0)) {
  328. wp = (u16 *)buf;
  329. while (avail >= 2) {
  330. *wp++ = omap_readw(UDC_DATA);
  331. avail -= 2;
  332. }
  333. buf = (u8 *)wp;
  334. }
  335. while (avail--)
  336. *buf++ = omap_readb(UDC_DATA);
  337. return len;
  338. }
  339. /* return: 0 = still running, 1 = queue empty, negative = errno */
  340. static int read_fifo(struct omap_ep *ep, struct omap_req *req)
  341. {
  342. u8 *buf;
  343. unsigned count, avail;
  344. int is_last;
  345. buf = req->req.buf + req->req.actual;
  346. prefetchw(buf);
  347. for (;;) {
  348. u16 ep_stat = omap_readw(UDC_STAT_FLG);
  349. is_last = 0;
  350. if (ep_stat & FIFO_EMPTY) {
  351. if (!ep->double_buf)
  352. break;
  353. ep->fnf = 1;
  354. }
  355. if (ep_stat & UDC_EP_HALTED)
  356. break;
  357. if (ep_stat & UDC_FIFO_FULL)
  358. avail = ep->ep.maxpacket;
  359. else {
  360. avail = omap_readw(UDC_RXFSTAT);
  361. ep->fnf = ep->double_buf;
  362. }
  363. count = read_packet(buf, req, avail);
  364. /* partial packet reads may not be errors */
  365. if (count < ep->ep.maxpacket) {
  366. is_last = 1;
  367. /* overflowed this request? flush extra data */
  368. if (count != avail) {
  369. req->req.status = -EOVERFLOW;
  370. avail -= count;
  371. while (avail--)
  372. omap_readw(UDC_DATA);
  373. }
  374. } else if (req->req.length == req->req.actual)
  375. is_last = 1;
  376. else
  377. is_last = 0;
  378. if (!ep->bEndpointAddress)
  379. break;
  380. if (is_last)
  381. done(ep, req, 0);
  382. break;
  383. }
  384. return is_last;
  385. }
  386. /*-------------------------------------------------------------------------*/
  387. static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
  388. {
  389. dma_addr_t end;
  390. /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
  391. * the last transfer's bytecount by more than a FIFO's worth.
  392. */
  393. if (cpu_is_omap15xx())
  394. return 0;
  395. end = omap_get_dma_src_pos(ep->lch);
  396. if (end == ep->dma_counter)
  397. return 0;
  398. end |= start & (0xffff << 16);
  399. if (end < start)
  400. end += 0x10000;
  401. return end - start;
  402. }
  403. static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
  404. {
  405. dma_addr_t end;
  406. end = omap_get_dma_dst_pos(ep->lch);
  407. if (end == ep->dma_counter)
  408. return 0;
  409. end |= start & (0xffff << 16);
  410. if (cpu_is_omap15xx())
  411. end++;
  412. if (end < start)
  413. end += 0x10000;
  414. return end - start;
  415. }
  416. /* Each USB transfer request using DMA maps to one or more DMA transfers.
  417. * When DMA completion isn't request completion, the UDC continues with
  418. * the next DMA transfer for that USB transfer.
  419. */
  420. static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
  421. {
  422. u16 txdma_ctrl, w;
  423. unsigned length = req->req.length - req->req.actual;
  424. const int sync_mode = cpu_is_omap15xx()
  425. ? OMAP_DMA_SYNC_FRAME
  426. : OMAP_DMA_SYNC_ELEMENT;
  427. int dma_trigger = 0;
  428. /* measure length in either bytes or packets */
  429. if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
  430. || (cpu_is_omap15xx() && length < ep->maxpacket)) {
  431. txdma_ctrl = UDC_TXN_EOT | length;
  432. omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
  433. length, 1, sync_mode, dma_trigger, 0);
  434. } else {
  435. length = min(length / ep->maxpacket,
  436. (unsigned) UDC_TXN_TSC + 1);
  437. txdma_ctrl = length;
  438. omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
  439. ep->ep.maxpacket >> 1, length, sync_mode,
  440. dma_trigger, 0);
  441. length *= ep->maxpacket;
  442. }
  443. omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
  444. OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
  445. 0, 0);
  446. omap_start_dma(ep->lch);
  447. ep->dma_counter = omap_get_dma_src_pos(ep->lch);
  448. w = omap_readw(UDC_DMA_IRQ_EN);
  449. w |= UDC_TX_DONE_IE(ep->dma_channel);
  450. omap_writew(w, UDC_DMA_IRQ_EN);
  451. omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
  452. req->dma_bytes = length;
  453. }
  454. static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
  455. {
  456. u16 w;
  457. if (status == 0) {
  458. req->req.actual += req->dma_bytes;
  459. /* return if this request needs to send data or zlp */
  460. if (req->req.actual < req->req.length)
  461. return;
  462. if (req->req.zero
  463. && req->dma_bytes != 0
  464. && (req->req.actual % ep->maxpacket) == 0)
  465. return;
  466. } else
  467. req->req.actual += dma_src_len(ep, req->req.dma
  468. + req->req.actual);
  469. /* tx completion */
  470. omap_stop_dma(ep->lch);
  471. w = omap_readw(UDC_DMA_IRQ_EN);
  472. w &= ~UDC_TX_DONE_IE(ep->dma_channel);
  473. omap_writew(w, UDC_DMA_IRQ_EN);
  474. done(ep, req, status);
  475. }
  476. static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
  477. {
  478. unsigned packets = req->req.length - req->req.actual;
  479. int dma_trigger = 0;
  480. u16 w;
  481. /* set up this DMA transfer, enable the fifo, start */
  482. packets /= ep->ep.maxpacket;
  483. packets = min(packets, (unsigned)UDC_RXN_TC + 1);
  484. req->dma_bytes = packets * ep->ep.maxpacket;
  485. omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
  486. ep->ep.maxpacket >> 1, packets,
  487. OMAP_DMA_SYNC_ELEMENT,
  488. dma_trigger, 0);
  489. omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
  490. OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
  491. 0, 0);
  492. ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
  493. omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
  494. w = omap_readw(UDC_DMA_IRQ_EN);
  495. w |= UDC_RX_EOT_IE(ep->dma_channel);
  496. omap_writew(w, UDC_DMA_IRQ_EN);
  497. omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
  498. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  499. omap_start_dma(ep->lch);
  500. }
  501. static void
  502. finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
  503. {
  504. u16 count, w;
  505. if (status == 0)
  506. ep->dma_counter = (u16) (req->req.dma + req->req.actual);
  507. count = dma_dest_len(ep, req->req.dma + req->req.actual);
  508. count += req->req.actual;
  509. if (one)
  510. count--;
  511. if (count <= req->req.length)
  512. req->req.actual = count;
  513. if (count != req->dma_bytes || status)
  514. omap_stop_dma(ep->lch);
  515. /* if this wasn't short, request may need another transfer */
  516. else if (req->req.actual < req->req.length)
  517. return;
  518. /* rx completion */
  519. w = omap_readw(UDC_DMA_IRQ_EN);
  520. w &= ~UDC_RX_EOT_IE(ep->dma_channel);
  521. omap_writew(w, UDC_DMA_IRQ_EN);
  522. done(ep, req, status);
  523. }
  524. static void dma_irq(struct omap_udc *udc, u16 irq_src)
  525. {
  526. u16 dman_stat = omap_readw(UDC_DMAN_STAT);
  527. struct omap_ep *ep;
  528. struct omap_req *req;
  529. /* IN dma: tx to host */
  530. if (irq_src & UDC_TXN_DONE) {
  531. ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
  532. ep->irqs++;
  533. /* can see TXN_DONE after dma abort */
  534. if (!list_empty(&ep->queue)) {
  535. req = container_of(ep->queue.next,
  536. struct omap_req, queue);
  537. finish_in_dma(ep, req, 0);
  538. }
  539. omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
  540. if (!list_empty(&ep->queue)) {
  541. req = container_of(ep->queue.next,
  542. struct omap_req, queue);
  543. next_in_dma(ep, req);
  544. }
  545. }
  546. /* OUT dma: rx from host */
  547. if (irq_src & UDC_RXN_EOT) {
  548. ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
  549. ep->irqs++;
  550. /* can see RXN_EOT after dma abort */
  551. if (!list_empty(&ep->queue)) {
  552. req = container_of(ep->queue.next,
  553. struct omap_req, queue);
  554. finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
  555. }
  556. omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
  557. if (!list_empty(&ep->queue)) {
  558. req = container_of(ep->queue.next,
  559. struct omap_req, queue);
  560. next_out_dma(ep, req);
  561. }
  562. }
  563. if (irq_src & UDC_RXN_CNT) {
  564. ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
  565. ep->irqs++;
  566. /* omap15xx does this unasked... */
  567. VDBG("%s, RX_CNT irq?\n", ep->ep.name);
  568. omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
  569. }
  570. }
  571. static void dma_error(int lch, u16 ch_status, void *data)
  572. {
  573. struct omap_ep *ep = data;
  574. /* if ch_status & OMAP_DMA_DROP_IRQ ... */
  575. /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
  576. ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
  577. /* complete current transfer ... */
  578. }
  579. static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
  580. {
  581. u16 reg;
  582. int status, restart, is_in;
  583. int dma_channel;
  584. is_in = ep->bEndpointAddress & USB_DIR_IN;
  585. if (is_in)
  586. reg = omap_readw(UDC_TXDMA_CFG);
  587. else
  588. reg = omap_readw(UDC_RXDMA_CFG);
  589. reg |= UDC_DMA_REQ; /* "pulse" activated */
  590. ep->dma_channel = 0;
  591. ep->lch = -1;
  592. if (channel == 0 || channel > 3) {
  593. if ((reg & 0x0f00) == 0)
  594. channel = 3;
  595. else if ((reg & 0x00f0) == 0)
  596. channel = 2;
  597. else if ((reg & 0x000f) == 0) /* preferred for ISO */
  598. channel = 1;
  599. else {
  600. status = -EMLINK;
  601. goto just_restart;
  602. }
  603. }
  604. reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
  605. ep->dma_channel = channel;
  606. if (is_in) {
  607. dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
  608. status = omap_request_dma(dma_channel,
  609. ep->ep.name, dma_error, ep, &ep->lch);
  610. if (status == 0) {
  611. omap_writew(reg, UDC_TXDMA_CFG);
  612. /* EMIFF or SDRC */
  613. omap_set_dma_src_burst_mode(ep->lch,
  614. OMAP_DMA_DATA_BURST_4);
  615. omap_set_dma_src_data_pack(ep->lch, 1);
  616. /* TIPB */
  617. omap_set_dma_dest_params(ep->lch,
  618. OMAP_DMA_PORT_TIPB,
  619. OMAP_DMA_AMODE_CONSTANT,
  620. UDC_DATA_DMA,
  621. 0, 0);
  622. }
  623. } else {
  624. dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
  625. status = omap_request_dma(dma_channel,
  626. ep->ep.name, dma_error, ep, &ep->lch);
  627. if (status == 0) {
  628. omap_writew(reg, UDC_RXDMA_CFG);
  629. /* TIPB */
  630. omap_set_dma_src_params(ep->lch,
  631. OMAP_DMA_PORT_TIPB,
  632. OMAP_DMA_AMODE_CONSTANT,
  633. UDC_DATA_DMA,
  634. 0, 0);
  635. /* EMIFF or SDRC */
  636. omap_set_dma_dest_burst_mode(ep->lch,
  637. OMAP_DMA_DATA_BURST_4);
  638. omap_set_dma_dest_data_pack(ep->lch, 1);
  639. }
  640. }
  641. if (status)
  642. ep->dma_channel = 0;
  643. else {
  644. ep->has_dma = 1;
  645. omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
  646. /* channel type P: hw synch (fifo) */
  647. if (!cpu_is_omap15xx())
  648. omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
  649. }
  650. just_restart:
  651. /* restart any queue, even if the claim failed */
  652. restart = !ep->stopped && !list_empty(&ep->queue);
  653. if (status)
  654. DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
  655. restart ? " (restart)" : "");
  656. else
  657. DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
  658. is_in ? 't' : 'r',
  659. ep->dma_channel - 1, ep->lch,
  660. restart ? " (restart)" : "");
  661. if (restart) {
  662. struct omap_req *req;
  663. req = container_of(ep->queue.next, struct omap_req, queue);
  664. if (ep->has_dma)
  665. (is_in ? next_in_dma : next_out_dma)(ep, req);
  666. else {
  667. use_ep(ep, UDC_EP_SEL);
  668. (is_in ? write_fifo : read_fifo)(ep, req);
  669. deselect_ep();
  670. if (!is_in) {
  671. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  672. ep->ackwait = 1 + ep->double_buf;
  673. }
  674. /* IN: 6 wait states before it'll tx */
  675. }
  676. }
  677. }
  678. static void dma_channel_release(struct omap_ep *ep)
  679. {
  680. int shift = 4 * (ep->dma_channel - 1);
  681. u16 mask = 0x0f << shift;
  682. struct omap_req *req;
  683. int active;
  684. /* abort any active usb transfer request */
  685. if (!list_empty(&ep->queue))
  686. req = container_of(ep->queue.next, struct omap_req, queue);
  687. else
  688. req = NULL;
  689. active = omap_get_dma_active_status(ep->lch);
  690. DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
  691. active ? "active" : "idle",
  692. (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
  693. ep->dma_channel - 1, req);
  694. /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
  695. * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
  696. */
  697. /* wait till current packet DMA finishes, and fifo empties */
  698. if (ep->bEndpointAddress & USB_DIR_IN) {
  699. omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
  700. UDC_TXDMA_CFG);
  701. if (req) {
  702. finish_in_dma(ep, req, -ECONNRESET);
  703. /* clear FIFO; hosts probably won't empty it */
  704. use_ep(ep, UDC_EP_SEL);
  705. omap_writew(UDC_CLR_EP, UDC_CTRL);
  706. deselect_ep();
  707. }
  708. while (omap_readw(UDC_TXDMA_CFG) & mask)
  709. udelay(10);
  710. } else {
  711. omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
  712. UDC_RXDMA_CFG);
  713. /* dma empties the fifo */
  714. while (omap_readw(UDC_RXDMA_CFG) & mask)
  715. udelay(10);
  716. if (req)
  717. finish_out_dma(ep, req, -ECONNRESET, 0);
  718. }
  719. omap_free_dma(ep->lch);
  720. ep->dma_channel = 0;
  721. ep->lch = -1;
  722. /* has_dma still set, till endpoint is fully quiesced */
  723. }
  724. /*-------------------------------------------------------------------------*/
  725. static int
  726. omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  727. {
  728. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  729. struct omap_req *req = container_of(_req, struct omap_req, req);
  730. struct omap_udc *udc;
  731. unsigned long flags;
  732. int is_iso = 0;
  733. /* catch various bogus parameters */
  734. if (!_req || !req->req.complete || !req->req.buf
  735. || !list_empty(&req->queue)) {
  736. DBG("%s, bad params\n", __func__);
  737. return -EINVAL;
  738. }
  739. if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
  740. DBG("%s, bad ep\n", __func__);
  741. return -EINVAL;
  742. }
  743. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  744. if (req->req.length > ep->ep.maxpacket)
  745. return -EMSGSIZE;
  746. is_iso = 1;
  747. }
  748. /* this isn't bogus, but OMAP DMA isn't the only hardware to
  749. * have a hard time with partial packet reads... reject it.
  750. */
  751. if (use_dma
  752. && ep->has_dma
  753. && ep->bEndpointAddress != 0
  754. && (ep->bEndpointAddress & USB_DIR_IN) == 0
  755. && (req->req.length % ep->ep.maxpacket) != 0) {
  756. DBG("%s, no partial packet OUT reads\n", __func__);
  757. return -EMSGSIZE;
  758. }
  759. udc = ep->udc;
  760. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  761. return -ESHUTDOWN;
  762. if (use_dma && ep->has_dma)
  763. usb_gadget_map_request(&udc->gadget, &req->req,
  764. (ep->bEndpointAddress & USB_DIR_IN));
  765. VDBG("%s queue req %p, len %d buf %p\n",
  766. ep->ep.name, _req, _req->length, _req->buf);
  767. spin_lock_irqsave(&udc->lock, flags);
  768. req->req.status = -EINPROGRESS;
  769. req->req.actual = 0;
  770. /* maybe kickstart non-iso i/o queues */
  771. if (is_iso) {
  772. u16 w;
  773. w = omap_readw(UDC_IRQ_EN);
  774. w |= UDC_SOF_IE;
  775. omap_writew(w, UDC_IRQ_EN);
  776. } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
  777. int is_in;
  778. if (ep->bEndpointAddress == 0) {
  779. if (!udc->ep0_pending || !list_empty(&ep->queue)) {
  780. spin_unlock_irqrestore(&udc->lock, flags);
  781. return -EL2HLT;
  782. }
  783. /* empty DATA stage? */
  784. is_in = udc->ep0_in;
  785. if (!req->req.length) {
  786. /* chip became CONFIGURED or ADDRESSED
  787. * earlier; drivers may already have queued
  788. * requests to non-control endpoints
  789. */
  790. if (udc->ep0_set_config) {
  791. u16 irq_en = omap_readw(UDC_IRQ_EN);
  792. irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
  793. if (!udc->ep0_reset_config)
  794. irq_en |= UDC_EPN_RX_IE
  795. | UDC_EPN_TX_IE;
  796. omap_writew(irq_en, UDC_IRQ_EN);
  797. }
  798. /* STATUS for zero length DATA stages is
  799. * always an IN ... even for IN transfers,
  800. * a weird case which seem to stall OMAP.
  801. */
  802. omap_writew(UDC_EP_SEL | UDC_EP_DIR,
  803. UDC_EP_NUM);
  804. omap_writew(UDC_CLR_EP, UDC_CTRL);
  805. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  806. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  807. /* cleanup */
  808. udc->ep0_pending = 0;
  809. done(ep, req, 0);
  810. req = NULL;
  811. /* non-empty DATA stage */
  812. } else if (is_in) {
  813. omap_writew(UDC_EP_SEL | UDC_EP_DIR,
  814. UDC_EP_NUM);
  815. } else {
  816. if (udc->ep0_setup)
  817. goto irq_wait;
  818. omap_writew(UDC_EP_SEL, UDC_EP_NUM);
  819. }
  820. } else {
  821. is_in = ep->bEndpointAddress & USB_DIR_IN;
  822. if (!ep->has_dma)
  823. use_ep(ep, UDC_EP_SEL);
  824. /* if ISO: SOF IRQs must be enabled/disabled! */
  825. }
  826. if (ep->has_dma)
  827. (is_in ? next_in_dma : next_out_dma)(ep, req);
  828. else if (req) {
  829. if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
  830. req = NULL;
  831. deselect_ep();
  832. if (!is_in) {
  833. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  834. ep->ackwait = 1 + ep->double_buf;
  835. }
  836. /* IN: 6 wait states before it'll tx */
  837. }
  838. }
  839. irq_wait:
  840. /* irq handler advances the queue */
  841. if (req != NULL)
  842. list_add_tail(&req->queue, &ep->queue);
  843. spin_unlock_irqrestore(&udc->lock, flags);
  844. return 0;
  845. }
  846. static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  847. {
  848. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  849. struct omap_req *req;
  850. unsigned long flags;
  851. if (!_ep || !_req)
  852. return -EINVAL;
  853. spin_lock_irqsave(&ep->udc->lock, flags);
  854. /* make sure it's actually queued on this endpoint */
  855. list_for_each_entry(req, &ep->queue, queue) {
  856. if (&req->req == _req)
  857. break;
  858. }
  859. if (&req->req != _req) {
  860. spin_unlock_irqrestore(&ep->udc->lock, flags);
  861. return -EINVAL;
  862. }
  863. if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
  864. int channel = ep->dma_channel;
  865. /* releasing the channel cancels the request,
  866. * reclaiming the channel restarts the queue
  867. */
  868. dma_channel_release(ep);
  869. dma_channel_claim(ep, channel);
  870. } else
  871. done(ep, req, -ECONNRESET);
  872. spin_unlock_irqrestore(&ep->udc->lock, flags);
  873. return 0;
  874. }
  875. /*-------------------------------------------------------------------------*/
  876. static int omap_ep_set_halt(struct usb_ep *_ep, int value)
  877. {
  878. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  879. unsigned long flags;
  880. int status = -EOPNOTSUPP;
  881. spin_lock_irqsave(&ep->udc->lock, flags);
  882. /* just use protocol stalls for ep0; real halts are annoying */
  883. if (ep->bEndpointAddress == 0) {
  884. if (!ep->udc->ep0_pending)
  885. status = -EINVAL;
  886. else if (value) {
  887. if (ep->udc->ep0_set_config) {
  888. WARNING("error changing config?\n");
  889. omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
  890. }
  891. omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
  892. ep->udc->ep0_pending = 0;
  893. status = 0;
  894. } else /* NOP */
  895. status = 0;
  896. /* otherwise, all active non-ISO endpoints can halt */
  897. } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
  898. /* IN endpoints must already be idle */
  899. if ((ep->bEndpointAddress & USB_DIR_IN)
  900. && !list_empty(&ep->queue)) {
  901. status = -EAGAIN;
  902. goto done;
  903. }
  904. if (value) {
  905. int channel;
  906. if (use_dma && ep->dma_channel
  907. && !list_empty(&ep->queue)) {
  908. channel = ep->dma_channel;
  909. dma_channel_release(ep);
  910. } else
  911. channel = 0;
  912. use_ep(ep, UDC_EP_SEL);
  913. if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
  914. omap_writew(UDC_SET_HALT, UDC_CTRL);
  915. status = 0;
  916. } else
  917. status = -EAGAIN;
  918. deselect_ep();
  919. if (channel)
  920. dma_channel_claim(ep, channel);
  921. } else {
  922. use_ep(ep, 0);
  923. omap_writew(ep->udc->clr_halt, UDC_CTRL);
  924. ep->ackwait = 0;
  925. if (!(ep->bEndpointAddress & USB_DIR_IN)) {
  926. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  927. ep->ackwait = 1 + ep->double_buf;
  928. }
  929. }
  930. }
  931. done:
  932. VDBG("%s %s halt stat %d\n", ep->ep.name,
  933. value ? "set" : "clear", status);
  934. spin_unlock_irqrestore(&ep->udc->lock, flags);
  935. return status;
  936. }
  937. static const struct usb_ep_ops omap_ep_ops = {
  938. .enable = omap_ep_enable,
  939. .disable = omap_ep_disable,
  940. .alloc_request = omap_alloc_request,
  941. .free_request = omap_free_request,
  942. .queue = omap_ep_queue,
  943. .dequeue = omap_ep_dequeue,
  944. .set_halt = omap_ep_set_halt,
  945. /* fifo_status ... report bytes in fifo */
  946. /* fifo_flush ... flush fifo */
  947. };
  948. /*-------------------------------------------------------------------------*/
  949. static int omap_get_frame(struct usb_gadget *gadget)
  950. {
  951. u16 sof = omap_readw(UDC_SOF);
  952. return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
  953. }
  954. static int omap_wakeup(struct usb_gadget *gadget)
  955. {
  956. struct omap_udc *udc;
  957. unsigned long flags;
  958. int retval = -EHOSTUNREACH;
  959. udc = container_of(gadget, struct omap_udc, gadget);
  960. spin_lock_irqsave(&udc->lock, flags);
  961. if (udc->devstat & UDC_SUS) {
  962. /* NOTE: OTG spec erratum says that OTG devices may
  963. * issue wakeups without host enable.
  964. */
  965. if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
  966. DBG("remote wakeup...\n");
  967. omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
  968. retval = 0;
  969. }
  970. /* NOTE: non-OTG systems may use SRP TOO... */
  971. } else if (!(udc->devstat & UDC_ATT)) {
  972. if (!IS_ERR_OR_NULL(udc->transceiver))
  973. retval = otg_start_srp(udc->transceiver->otg);
  974. }
  975. spin_unlock_irqrestore(&udc->lock, flags);
  976. return retval;
  977. }
  978. static int
  979. omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  980. {
  981. struct omap_udc *udc;
  982. unsigned long flags;
  983. u16 syscon1;
  984. gadget->is_selfpowered = (is_selfpowered != 0);
  985. udc = container_of(gadget, struct omap_udc, gadget);
  986. spin_lock_irqsave(&udc->lock, flags);
  987. syscon1 = omap_readw(UDC_SYSCON1);
  988. if (is_selfpowered)
  989. syscon1 |= UDC_SELF_PWR;
  990. else
  991. syscon1 &= ~UDC_SELF_PWR;
  992. omap_writew(syscon1, UDC_SYSCON1);
  993. spin_unlock_irqrestore(&udc->lock, flags);
  994. return 0;
  995. }
  996. static int can_pullup(struct omap_udc *udc)
  997. {
  998. return udc->driver && udc->softconnect && udc->vbus_active;
  999. }
  1000. static void pullup_enable(struct omap_udc *udc)
  1001. {
  1002. u16 w;
  1003. w = omap_readw(UDC_SYSCON1);
  1004. w |= UDC_PULLUP_EN;
  1005. omap_writew(w, UDC_SYSCON1);
  1006. if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
  1007. u32 l;
  1008. l = omap_readl(OTG_CTRL);
  1009. l |= OTG_BSESSVLD;
  1010. omap_writel(l, OTG_CTRL);
  1011. }
  1012. omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
  1013. }
  1014. static void pullup_disable(struct omap_udc *udc)
  1015. {
  1016. u16 w;
  1017. if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
  1018. u32 l;
  1019. l = omap_readl(OTG_CTRL);
  1020. l &= ~OTG_BSESSVLD;
  1021. omap_writel(l, OTG_CTRL);
  1022. }
  1023. omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
  1024. w = omap_readw(UDC_SYSCON1);
  1025. w &= ~UDC_PULLUP_EN;
  1026. omap_writew(w, UDC_SYSCON1);
  1027. }
  1028. static struct omap_udc *udc;
  1029. static void omap_udc_enable_clock(int enable)
  1030. {
  1031. if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
  1032. return;
  1033. if (enable) {
  1034. clk_enable(udc->dc_clk);
  1035. clk_enable(udc->hhc_clk);
  1036. udelay(100);
  1037. } else {
  1038. clk_disable(udc->hhc_clk);
  1039. clk_disable(udc->dc_clk);
  1040. }
  1041. }
  1042. /*
  1043. * Called by whatever detects VBUS sessions: external transceiver
  1044. * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
  1045. */
  1046. static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
  1047. {
  1048. struct omap_udc *udc;
  1049. unsigned long flags;
  1050. u32 l;
  1051. udc = container_of(gadget, struct omap_udc, gadget);
  1052. spin_lock_irqsave(&udc->lock, flags);
  1053. VDBG("VBUS %s\n", is_active ? "on" : "off");
  1054. udc->vbus_active = (is_active != 0);
  1055. if (cpu_is_omap15xx()) {
  1056. /* "software" detect, ignored if !VBUS_MODE_1510 */
  1057. l = omap_readl(FUNC_MUX_CTRL_0);
  1058. if (is_active)
  1059. l |= VBUS_CTRL_1510;
  1060. else
  1061. l &= ~VBUS_CTRL_1510;
  1062. omap_writel(l, FUNC_MUX_CTRL_0);
  1063. }
  1064. if (udc->dc_clk != NULL && is_active) {
  1065. if (!udc->clk_requested) {
  1066. omap_udc_enable_clock(1);
  1067. udc->clk_requested = 1;
  1068. }
  1069. }
  1070. if (can_pullup(udc))
  1071. pullup_enable(udc);
  1072. else
  1073. pullup_disable(udc);
  1074. if (udc->dc_clk != NULL && !is_active) {
  1075. if (udc->clk_requested) {
  1076. omap_udc_enable_clock(0);
  1077. udc->clk_requested = 0;
  1078. }
  1079. }
  1080. spin_unlock_irqrestore(&udc->lock, flags);
  1081. return 0;
  1082. }
  1083. static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1084. {
  1085. struct omap_udc *udc;
  1086. udc = container_of(gadget, struct omap_udc, gadget);
  1087. if (!IS_ERR_OR_NULL(udc->transceiver))
  1088. return usb_phy_set_power(udc->transceiver, mA);
  1089. return -EOPNOTSUPP;
  1090. }
  1091. static int omap_pullup(struct usb_gadget *gadget, int is_on)
  1092. {
  1093. struct omap_udc *udc;
  1094. unsigned long flags;
  1095. udc = container_of(gadget, struct omap_udc, gadget);
  1096. spin_lock_irqsave(&udc->lock, flags);
  1097. udc->softconnect = (is_on != 0);
  1098. if (can_pullup(udc))
  1099. pullup_enable(udc);
  1100. else
  1101. pullup_disable(udc);
  1102. spin_unlock_irqrestore(&udc->lock, flags);
  1103. return 0;
  1104. }
  1105. static int omap_udc_start(struct usb_gadget *g,
  1106. struct usb_gadget_driver *driver);
  1107. static int omap_udc_stop(struct usb_gadget *g);
  1108. static const struct usb_gadget_ops omap_gadget_ops = {
  1109. .get_frame = omap_get_frame,
  1110. .wakeup = omap_wakeup,
  1111. .set_selfpowered = omap_set_selfpowered,
  1112. .vbus_session = omap_vbus_session,
  1113. .vbus_draw = omap_vbus_draw,
  1114. .pullup = omap_pullup,
  1115. .udc_start = omap_udc_start,
  1116. .udc_stop = omap_udc_stop,
  1117. };
  1118. /*-------------------------------------------------------------------------*/
  1119. /* dequeue ALL requests; caller holds udc->lock */
  1120. static void nuke(struct omap_ep *ep, int status)
  1121. {
  1122. struct omap_req *req;
  1123. ep->stopped = 1;
  1124. if (use_dma && ep->dma_channel)
  1125. dma_channel_release(ep);
  1126. use_ep(ep, 0);
  1127. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1128. if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
  1129. omap_writew(UDC_SET_HALT, UDC_CTRL);
  1130. while (!list_empty(&ep->queue)) {
  1131. req = list_entry(ep->queue.next, struct omap_req, queue);
  1132. done(ep, req, status);
  1133. }
  1134. }
  1135. /* caller holds udc->lock */
  1136. static void udc_quiesce(struct omap_udc *udc)
  1137. {
  1138. struct omap_ep *ep;
  1139. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1140. nuke(&udc->ep[0], -ESHUTDOWN);
  1141. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
  1142. nuke(ep, -ESHUTDOWN);
  1143. }
  1144. /*-------------------------------------------------------------------------*/
  1145. static void update_otg(struct omap_udc *udc)
  1146. {
  1147. u16 devstat;
  1148. if (!gadget_is_otg(&udc->gadget))
  1149. return;
  1150. if (omap_readl(OTG_CTRL) & OTG_ID)
  1151. devstat = omap_readw(UDC_DEVSTAT);
  1152. else
  1153. devstat = 0;
  1154. udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
  1155. udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
  1156. udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
  1157. /* Enable HNP early, avoiding races on suspend irq path.
  1158. * ASSUMES OTG state machine B_BUS_REQ input is true.
  1159. */
  1160. if (udc->gadget.b_hnp_enable) {
  1161. u32 l;
  1162. l = omap_readl(OTG_CTRL);
  1163. l |= OTG_B_HNPEN | OTG_B_BUSREQ;
  1164. l &= ~OTG_PULLUP;
  1165. omap_writel(l, OTG_CTRL);
  1166. }
  1167. }
  1168. static void ep0_irq(struct omap_udc *udc, u16 irq_src)
  1169. {
  1170. struct omap_ep *ep0 = &udc->ep[0];
  1171. struct omap_req *req = NULL;
  1172. ep0->irqs++;
  1173. /* Clear any pending requests and then scrub any rx/tx state
  1174. * before starting to handle the SETUP request.
  1175. */
  1176. if (irq_src & UDC_SETUP) {
  1177. u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
  1178. nuke(ep0, 0);
  1179. if (ack) {
  1180. omap_writew(ack, UDC_IRQ_SRC);
  1181. irq_src = UDC_SETUP;
  1182. }
  1183. }
  1184. /* IN/OUT packets mean we're in the DATA or STATUS stage.
  1185. * This driver uses only uses protocol stalls (ep0 never halts),
  1186. * and if we got this far the gadget driver already had a
  1187. * chance to stall. Tries to be forgiving of host oddities.
  1188. *
  1189. * NOTE: the last chance gadget drivers have to stall control
  1190. * requests is during their request completion callback.
  1191. */
  1192. if (!list_empty(&ep0->queue))
  1193. req = container_of(ep0->queue.next, struct omap_req, queue);
  1194. /* IN == TX to host */
  1195. if (irq_src & UDC_EP0_TX) {
  1196. int stat;
  1197. omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
  1198. omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
  1199. stat = omap_readw(UDC_STAT_FLG);
  1200. if (stat & UDC_ACK) {
  1201. if (udc->ep0_in) {
  1202. /* write next IN packet from response,
  1203. * or set up the status stage.
  1204. */
  1205. if (req)
  1206. stat = write_fifo(ep0, req);
  1207. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1208. if (!req && udc->ep0_pending) {
  1209. omap_writew(UDC_EP_SEL, UDC_EP_NUM);
  1210. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1211. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1212. omap_writew(0, UDC_EP_NUM);
  1213. udc->ep0_pending = 0;
  1214. } /* else: 6 wait states before it'll tx */
  1215. } else {
  1216. /* ack status stage of OUT transfer */
  1217. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1218. if (req)
  1219. done(ep0, req, 0);
  1220. }
  1221. req = NULL;
  1222. } else if (stat & UDC_STALL) {
  1223. omap_writew(UDC_CLR_HALT, UDC_CTRL);
  1224. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1225. } else {
  1226. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1227. }
  1228. }
  1229. /* OUT == RX from host */
  1230. if (irq_src & UDC_EP0_RX) {
  1231. int stat;
  1232. omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
  1233. omap_writew(UDC_EP_SEL, UDC_EP_NUM);
  1234. stat = omap_readw(UDC_STAT_FLG);
  1235. if (stat & UDC_ACK) {
  1236. if (!udc->ep0_in) {
  1237. stat = 0;
  1238. /* read next OUT packet of request, maybe
  1239. * reactiviting the fifo; stall on errors.
  1240. */
  1241. stat = read_fifo(ep0, req);
  1242. if (!req || stat < 0) {
  1243. omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
  1244. udc->ep0_pending = 0;
  1245. stat = 0;
  1246. } else if (stat == 0)
  1247. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1248. omap_writew(0, UDC_EP_NUM);
  1249. /* activate status stage */
  1250. if (stat == 1) {
  1251. done(ep0, req, 0);
  1252. /* that may have STALLed ep0... */
  1253. omap_writew(UDC_EP_SEL | UDC_EP_DIR,
  1254. UDC_EP_NUM);
  1255. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1256. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1257. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1258. udc->ep0_pending = 0;
  1259. }
  1260. } else {
  1261. /* ack status stage of IN transfer */
  1262. omap_writew(0, UDC_EP_NUM);
  1263. if (req)
  1264. done(ep0, req, 0);
  1265. }
  1266. } else if (stat & UDC_STALL) {
  1267. omap_writew(UDC_CLR_HALT, UDC_CTRL);
  1268. omap_writew(0, UDC_EP_NUM);
  1269. } else {
  1270. omap_writew(0, UDC_EP_NUM);
  1271. }
  1272. }
  1273. /* SETUP starts all control transfers */
  1274. if (irq_src & UDC_SETUP) {
  1275. union u {
  1276. u16 word[4];
  1277. struct usb_ctrlrequest r;
  1278. } u;
  1279. int status = -EINVAL;
  1280. struct omap_ep *ep;
  1281. /* read the (latest) SETUP message */
  1282. do {
  1283. omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
  1284. /* two bytes at a time */
  1285. u.word[0] = omap_readw(UDC_DATA);
  1286. u.word[1] = omap_readw(UDC_DATA);
  1287. u.word[2] = omap_readw(UDC_DATA);
  1288. u.word[3] = omap_readw(UDC_DATA);
  1289. omap_writew(0, UDC_EP_NUM);
  1290. } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
  1291. #define w_value le16_to_cpu(u.r.wValue)
  1292. #define w_index le16_to_cpu(u.r.wIndex)
  1293. #define w_length le16_to_cpu(u.r.wLength)
  1294. /* Delegate almost all control requests to the gadget driver,
  1295. * except for a handful of ch9 status/feature requests that
  1296. * hardware doesn't autodecode _and_ the gadget API hides.
  1297. */
  1298. udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
  1299. udc->ep0_set_config = 0;
  1300. udc->ep0_pending = 1;
  1301. ep0->stopped = 0;
  1302. ep0->ackwait = 0;
  1303. switch (u.r.bRequest) {
  1304. case USB_REQ_SET_CONFIGURATION:
  1305. /* udc needs to know when ep != 0 is valid */
  1306. if (u.r.bRequestType != USB_RECIP_DEVICE)
  1307. goto delegate;
  1308. if (w_length != 0)
  1309. goto do_stall;
  1310. udc->ep0_set_config = 1;
  1311. udc->ep0_reset_config = (w_value == 0);
  1312. VDBG("set config %d\n", w_value);
  1313. /* update udc NOW since gadget driver may start
  1314. * queueing requests immediately; clear config
  1315. * later if it fails the request.
  1316. */
  1317. if (udc->ep0_reset_config)
  1318. omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
  1319. else
  1320. omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
  1321. update_otg(udc);
  1322. goto delegate;
  1323. case USB_REQ_CLEAR_FEATURE:
  1324. /* clear endpoint halt */
  1325. if (u.r.bRequestType != USB_RECIP_ENDPOINT)
  1326. goto delegate;
  1327. if (w_value != USB_ENDPOINT_HALT
  1328. || w_length != 0)
  1329. goto do_stall;
  1330. ep = &udc->ep[w_index & 0xf];
  1331. if (ep != ep0) {
  1332. if (w_index & USB_DIR_IN)
  1333. ep += 16;
  1334. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
  1335. || !ep->ep.desc)
  1336. goto do_stall;
  1337. use_ep(ep, 0);
  1338. omap_writew(udc->clr_halt, UDC_CTRL);
  1339. ep->ackwait = 0;
  1340. if (!(ep->bEndpointAddress & USB_DIR_IN)) {
  1341. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1342. ep->ackwait = 1 + ep->double_buf;
  1343. }
  1344. /* NOTE: assumes the host behaves sanely,
  1345. * only clearing real halts. Else we may
  1346. * need to kill pending transfers and then
  1347. * restart the queue... very messy for DMA!
  1348. */
  1349. }
  1350. VDBG("%s halt cleared by host\n", ep->name);
  1351. goto ep0out_status_stage;
  1352. case USB_REQ_SET_FEATURE:
  1353. /* set endpoint halt */
  1354. if (u.r.bRequestType != USB_RECIP_ENDPOINT)
  1355. goto delegate;
  1356. if (w_value != USB_ENDPOINT_HALT
  1357. || w_length != 0)
  1358. goto do_stall;
  1359. ep = &udc->ep[w_index & 0xf];
  1360. if (w_index & USB_DIR_IN)
  1361. ep += 16;
  1362. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
  1363. || ep == ep0 || !ep->ep.desc)
  1364. goto do_stall;
  1365. if (use_dma && ep->has_dma) {
  1366. /* this has rude side-effects (aborts) and
  1367. * can't really work if DMA-IN is active
  1368. */
  1369. DBG("%s host set_halt, NYET\n", ep->name);
  1370. goto do_stall;
  1371. }
  1372. use_ep(ep, 0);
  1373. /* can't halt if fifo isn't empty... */
  1374. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1375. omap_writew(UDC_SET_HALT, UDC_CTRL);
  1376. VDBG("%s halted by host\n", ep->name);
  1377. ep0out_status_stage:
  1378. status = 0;
  1379. omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
  1380. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1381. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1382. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1383. udc->ep0_pending = 0;
  1384. break;
  1385. case USB_REQ_GET_STATUS:
  1386. /* USB_ENDPOINT_HALT status? */
  1387. if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
  1388. goto intf_status;
  1389. /* ep0 never stalls */
  1390. if (!(w_index & 0xf))
  1391. goto zero_status;
  1392. /* only active endpoints count */
  1393. ep = &udc->ep[w_index & 0xf];
  1394. if (w_index & USB_DIR_IN)
  1395. ep += 16;
  1396. if (!ep->ep.desc)
  1397. goto do_stall;
  1398. /* iso never stalls */
  1399. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
  1400. goto zero_status;
  1401. /* FIXME don't assume non-halted endpoints!! */
  1402. ERR("%s status, can't report\n", ep->ep.name);
  1403. goto do_stall;
  1404. intf_status:
  1405. /* return interface status. if we were pedantic,
  1406. * we'd detect non-existent interfaces, and stall.
  1407. */
  1408. if (u.r.bRequestType
  1409. != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1410. goto delegate;
  1411. zero_status:
  1412. /* return two zero bytes */
  1413. omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
  1414. omap_writew(0, UDC_DATA);
  1415. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1416. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1417. status = 0;
  1418. VDBG("GET_STATUS, interface %d\n", w_index);
  1419. /* next, status stage */
  1420. break;
  1421. default:
  1422. delegate:
  1423. /* activate the ep0out fifo right away */
  1424. if (!udc->ep0_in && w_length) {
  1425. omap_writew(0, UDC_EP_NUM);
  1426. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1427. }
  1428. /* gadget drivers see class/vendor specific requests,
  1429. * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
  1430. * and more
  1431. */
  1432. VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
  1433. u.r.bRequestType, u.r.bRequest,
  1434. w_value, w_index, w_length);
  1435. #undef w_value
  1436. #undef w_index
  1437. #undef w_length
  1438. /* The gadget driver may return an error here,
  1439. * causing an immediate protocol stall.
  1440. *
  1441. * Else it must issue a response, either queueing a
  1442. * response buffer for the DATA stage, or halting ep0
  1443. * (causing a protocol stall, not a real halt). A
  1444. * zero length buffer means no DATA stage.
  1445. *
  1446. * It's fine to issue that response after the setup()
  1447. * call returns, and this IRQ was handled.
  1448. */
  1449. udc->ep0_setup = 1;
  1450. spin_unlock(&udc->lock);
  1451. status = udc->driver->setup(&udc->gadget, &u.r);
  1452. spin_lock(&udc->lock);
  1453. udc->ep0_setup = 0;
  1454. }
  1455. if (status < 0) {
  1456. do_stall:
  1457. VDBG("req %02x.%02x protocol STALL; stat %d\n",
  1458. u.r.bRequestType, u.r.bRequest, status);
  1459. if (udc->ep0_set_config) {
  1460. if (udc->ep0_reset_config)
  1461. WARNING("error resetting config?\n");
  1462. else
  1463. omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
  1464. }
  1465. omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
  1466. udc->ep0_pending = 0;
  1467. }
  1468. }
  1469. }
  1470. /*-------------------------------------------------------------------------*/
  1471. #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
  1472. static void devstate_irq(struct omap_udc *udc, u16 irq_src)
  1473. {
  1474. u16 devstat, change;
  1475. devstat = omap_readw(UDC_DEVSTAT);
  1476. change = devstat ^ udc->devstat;
  1477. udc->devstat = devstat;
  1478. if (change & (UDC_USB_RESET|UDC_ATT)) {
  1479. udc_quiesce(udc);
  1480. if (change & UDC_ATT) {
  1481. /* driver for any external transceiver will
  1482. * have called omap_vbus_session() already
  1483. */
  1484. if (devstat & UDC_ATT) {
  1485. udc->gadget.speed = USB_SPEED_FULL;
  1486. VDBG("connect\n");
  1487. if (IS_ERR_OR_NULL(udc->transceiver))
  1488. pullup_enable(udc);
  1489. /* if (driver->connect) call it */
  1490. } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1491. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1492. if (IS_ERR_OR_NULL(udc->transceiver))
  1493. pullup_disable(udc);
  1494. DBG("disconnect, gadget %s\n",
  1495. udc->driver->driver.name);
  1496. if (udc->driver->disconnect) {
  1497. spin_unlock(&udc->lock);
  1498. udc->driver->disconnect(&udc->gadget);
  1499. spin_lock(&udc->lock);
  1500. }
  1501. }
  1502. change &= ~UDC_ATT;
  1503. }
  1504. if (change & UDC_USB_RESET) {
  1505. if (devstat & UDC_USB_RESET) {
  1506. VDBG("RESET=1\n");
  1507. } else {
  1508. udc->gadget.speed = USB_SPEED_FULL;
  1509. INFO("USB reset done, gadget %s\n",
  1510. udc->driver->driver.name);
  1511. /* ep0 traffic is legal from now on */
  1512. omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
  1513. UDC_IRQ_EN);
  1514. }
  1515. change &= ~UDC_USB_RESET;
  1516. }
  1517. }
  1518. if (change & UDC_SUS) {
  1519. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1520. /* FIXME tell isp1301 to suspend/resume (?) */
  1521. if (devstat & UDC_SUS) {
  1522. VDBG("suspend\n");
  1523. update_otg(udc);
  1524. /* HNP could be under way already */
  1525. if (udc->gadget.speed == USB_SPEED_FULL
  1526. && udc->driver->suspend) {
  1527. spin_unlock(&udc->lock);
  1528. udc->driver->suspend(&udc->gadget);
  1529. spin_lock(&udc->lock);
  1530. }
  1531. if (!IS_ERR_OR_NULL(udc->transceiver))
  1532. usb_phy_set_suspend(
  1533. udc->transceiver, 1);
  1534. } else {
  1535. VDBG("resume\n");
  1536. if (!IS_ERR_OR_NULL(udc->transceiver))
  1537. usb_phy_set_suspend(
  1538. udc->transceiver, 0);
  1539. if (udc->gadget.speed == USB_SPEED_FULL
  1540. && udc->driver->resume) {
  1541. spin_unlock(&udc->lock);
  1542. udc->driver->resume(&udc->gadget);
  1543. spin_lock(&udc->lock);
  1544. }
  1545. }
  1546. }
  1547. change &= ~UDC_SUS;
  1548. }
  1549. if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
  1550. update_otg(udc);
  1551. change &= ~OTG_FLAGS;
  1552. }
  1553. change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
  1554. if (change)
  1555. VDBG("devstat %03x, ignore change %03x\n",
  1556. devstat, change);
  1557. omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
  1558. }
  1559. static irqreturn_t omap_udc_irq(int irq, void *_udc)
  1560. {
  1561. struct omap_udc *udc = _udc;
  1562. u16 irq_src;
  1563. irqreturn_t status = IRQ_NONE;
  1564. unsigned long flags;
  1565. spin_lock_irqsave(&udc->lock, flags);
  1566. irq_src = omap_readw(UDC_IRQ_SRC);
  1567. /* Device state change (usb ch9 stuff) */
  1568. if (irq_src & UDC_DS_CHG) {
  1569. devstate_irq(_udc, irq_src);
  1570. status = IRQ_HANDLED;
  1571. irq_src &= ~UDC_DS_CHG;
  1572. }
  1573. /* EP0 control transfers */
  1574. if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
  1575. ep0_irq(_udc, irq_src);
  1576. status = IRQ_HANDLED;
  1577. irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
  1578. }
  1579. /* DMA transfer completion */
  1580. if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
  1581. dma_irq(_udc, irq_src);
  1582. status = IRQ_HANDLED;
  1583. irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
  1584. }
  1585. irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
  1586. if (irq_src)
  1587. DBG("udc_irq, unhandled %03x\n", irq_src);
  1588. spin_unlock_irqrestore(&udc->lock, flags);
  1589. return status;
  1590. }
  1591. /* workaround for seemingly-lost IRQs for RX ACKs... */
  1592. #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
  1593. #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
  1594. static void pio_out_timer(struct timer_list *t)
  1595. {
  1596. struct omap_ep *ep = from_timer(ep, t, timer);
  1597. unsigned long flags;
  1598. u16 stat_flg;
  1599. spin_lock_irqsave(&ep->udc->lock, flags);
  1600. if (!list_empty(&ep->queue) && ep->ackwait) {
  1601. use_ep(ep, UDC_EP_SEL);
  1602. stat_flg = omap_readw(UDC_STAT_FLG);
  1603. if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
  1604. || (ep->double_buf && HALF_FULL(stat_flg)))) {
  1605. struct omap_req *req;
  1606. VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
  1607. req = container_of(ep->queue.next,
  1608. struct omap_req, queue);
  1609. (void) read_fifo(ep, req);
  1610. omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
  1611. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1612. ep->ackwait = 1 + ep->double_buf;
  1613. } else
  1614. deselect_ep();
  1615. }
  1616. mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
  1617. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1618. }
  1619. static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
  1620. {
  1621. u16 epn_stat, irq_src;
  1622. irqreturn_t status = IRQ_NONE;
  1623. struct omap_ep *ep;
  1624. int epnum;
  1625. struct omap_udc *udc = _dev;
  1626. struct omap_req *req;
  1627. unsigned long flags;
  1628. spin_lock_irqsave(&udc->lock, flags);
  1629. epn_stat = omap_readw(UDC_EPN_STAT);
  1630. irq_src = omap_readw(UDC_IRQ_SRC);
  1631. /* handle OUT first, to avoid some wasteful NAKs */
  1632. if (irq_src & UDC_EPN_RX) {
  1633. epnum = (epn_stat >> 8) & 0x0f;
  1634. omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
  1635. status = IRQ_HANDLED;
  1636. ep = &udc->ep[epnum];
  1637. ep->irqs++;
  1638. omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
  1639. ep->fnf = 0;
  1640. if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
  1641. ep->ackwait--;
  1642. if (!list_empty(&ep->queue)) {
  1643. int stat;
  1644. req = container_of(ep->queue.next,
  1645. struct omap_req, queue);
  1646. stat = read_fifo(ep, req);
  1647. if (!ep->double_buf)
  1648. ep->fnf = 1;
  1649. }
  1650. }
  1651. /* min 6 clock delay before clearing EP_SEL ... */
  1652. epn_stat = omap_readw(UDC_EPN_STAT);
  1653. epn_stat = omap_readw(UDC_EPN_STAT);
  1654. omap_writew(epnum, UDC_EP_NUM);
  1655. /* enabling fifo _after_ clearing ACK, contrary to docs,
  1656. * reduces lossage; timer still needed though (sigh).
  1657. */
  1658. if (ep->fnf) {
  1659. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1660. ep->ackwait = 1 + ep->double_buf;
  1661. }
  1662. mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
  1663. }
  1664. /* then IN transfers */
  1665. else if (irq_src & UDC_EPN_TX) {
  1666. epnum = epn_stat & 0x0f;
  1667. omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
  1668. status = IRQ_HANDLED;
  1669. ep = &udc->ep[16 + epnum];
  1670. ep->irqs++;
  1671. omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
  1672. if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
  1673. ep->ackwait = 0;
  1674. if (!list_empty(&ep->queue)) {
  1675. req = container_of(ep->queue.next,
  1676. struct omap_req, queue);
  1677. (void) write_fifo(ep, req);
  1678. }
  1679. }
  1680. /* min 6 clock delay before clearing EP_SEL ... */
  1681. epn_stat = omap_readw(UDC_EPN_STAT);
  1682. epn_stat = omap_readw(UDC_EPN_STAT);
  1683. omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
  1684. /* then 6 clocks before it'd tx */
  1685. }
  1686. spin_unlock_irqrestore(&udc->lock, flags);
  1687. return status;
  1688. }
  1689. #ifdef USE_ISO
  1690. static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
  1691. {
  1692. struct omap_udc *udc = _dev;
  1693. struct omap_ep *ep;
  1694. int pending = 0;
  1695. unsigned long flags;
  1696. spin_lock_irqsave(&udc->lock, flags);
  1697. /* handle all non-DMA ISO transfers */
  1698. list_for_each_entry(ep, &udc->iso, iso) {
  1699. u16 stat;
  1700. struct omap_req *req;
  1701. if (ep->has_dma || list_empty(&ep->queue))
  1702. continue;
  1703. req = list_entry(ep->queue.next, struct omap_req, queue);
  1704. use_ep(ep, UDC_EP_SEL);
  1705. stat = omap_readw(UDC_STAT_FLG);
  1706. /* NOTE: like the other controller drivers, this isn't
  1707. * currently reporting lost or damaged frames.
  1708. */
  1709. if (ep->bEndpointAddress & USB_DIR_IN) {
  1710. if (stat & UDC_MISS_IN)
  1711. /* done(ep, req, -EPROTO) */;
  1712. else
  1713. write_fifo(ep, req);
  1714. } else {
  1715. int status = 0;
  1716. if (stat & UDC_NO_RXPACKET)
  1717. status = -EREMOTEIO;
  1718. else if (stat & UDC_ISO_ERR)
  1719. status = -EILSEQ;
  1720. else if (stat & UDC_DATA_FLUSH)
  1721. status = -ENOSR;
  1722. if (status)
  1723. /* done(ep, req, status) */;
  1724. else
  1725. read_fifo(ep, req);
  1726. }
  1727. deselect_ep();
  1728. /* 6 wait states before next EP */
  1729. ep->irqs++;
  1730. if (!list_empty(&ep->queue))
  1731. pending = 1;
  1732. }
  1733. if (!pending) {
  1734. u16 w;
  1735. w = omap_readw(UDC_IRQ_EN);
  1736. w &= ~UDC_SOF_IE;
  1737. omap_writew(w, UDC_IRQ_EN);
  1738. }
  1739. omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
  1740. spin_unlock_irqrestore(&udc->lock, flags);
  1741. return IRQ_HANDLED;
  1742. }
  1743. #endif
  1744. /*-------------------------------------------------------------------------*/
  1745. static inline int machine_without_vbus_sense(void)
  1746. {
  1747. return machine_is_omap_innovator()
  1748. || machine_is_omap_osk()
  1749. || machine_is_omap_palmte()
  1750. || machine_is_sx1()
  1751. /* No known omap7xx boards with vbus sense */
  1752. || cpu_is_omap7xx();
  1753. }
  1754. static int omap_udc_start(struct usb_gadget *g,
  1755. struct usb_gadget_driver *driver)
  1756. {
  1757. int status;
  1758. struct omap_ep *ep;
  1759. unsigned long flags;
  1760. spin_lock_irqsave(&udc->lock, flags);
  1761. /* reset state */
  1762. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  1763. ep->irqs = 0;
  1764. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
  1765. continue;
  1766. use_ep(ep, 0);
  1767. omap_writew(UDC_SET_HALT, UDC_CTRL);
  1768. }
  1769. udc->ep0_pending = 0;
  1770. udc->ep[0].irqs = 0;
  1771. udc->softconnect = 1;
  1772. /* hook up the driver */
  1773. driver->driver.bus = NULL;
  1774. udc->driver = driver;
  1775. spin_unlock_irqrestore(&udc->lock, flags);
  1776. if (udc->dc_clk != NULL)
  1777. omap_udc_enable_clock(1);
  1778. omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
  1779. /* connect to bus through transceiver */
  1780. if (!IS_ERR_OR_NULL(udc->transceiver)) {
  1781. status = otg_set_peripheral(udc->transceiver->otg,
  1782. &udc->gadget);
  1783. if (status < 0) {
  1784. ERR("can't bind to transceiver\n");
  1785. udc->driver = NULL;
  1786. goto done;
  1787. }
  1788. } else {
  1789. status = 0;
  1790. if (can_pullup(udc))
  1791. pullup_enable(udc);
  1792. else
  1793. pullup_disable(udc);
  1794. }
  1795. /* boards that don't have VBUS sensing can't autogate 48MHz;
  1796. * can't enter deep sleep while a gadget driver is active.
  1797. */
  1798. if (machine_without_vbus_sense())
  1799. omap_vbus_session(&udc->gadget, 1);
  1800. done:
  1801. if (udc->dc_clk != NULL)
  1802. omap_udc_enable_clock(0);
  1803. return status;
  1804. }
  1805. static int omap_udc_stop(struct usb_gadget *g)
  1806. {
  1807. unsigned long flags;
  1808. int status = -ENODEV;
  1809. if (udc->dc_clk != NULL)
  1810. omap_udc_enable_clock(1);
  1811. if (machine_without_vbus_sense())
  1812. omap_vbus_session(&udc->gadget, 0);
  1813. if (!IS_ERR_OR_NULL(udc->transceiver))
  1814. (void) otg_set_peripheral(udc->transceiver->otg, NULL);
  1815. else
  1816. pullup_disable(udc);
  1817. spin_lock_irqsave(&udc->lock, flags);
  1818. udc_quiesce(udc);
  1819. spin_unlock_irqrestore(&udc->lock, flags);
  1820. udc->driver = NULL;
  1821. if (udc->dc_clk != NULL)
  1822. omap_udc_enable_clock(0);
  1823. return status;
  1824. }
  1825. /*-------------------------------------------------------------------------*/
  1826. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1827. #include <linux/seq_file.h>
  1828. static const char proc_filename[] = "driver/udc";
  1829. #define FOURBITS "%s%s%s%s"
  1830. #define EIGHTBITS "%s%s%s%s%s%s%s%s"
  1831. static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
  1832. {
  1833. u16 stat_flg;
  1834. struct omap_req *req;
  1835. char buf[20];
  1836. use_ep(ep, 0);
  1837. if (use_dma && ep->has_dma)
  1838. snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
  1839. (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
  1840. ep->dma_channel - 1, ep->lch);
  1841. else
  1842. buf[0] = 0;
  1843. stat_flg = omap_readw(UDC_STAT_FLG);
  1844. seq_printf(s,
  1845. "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
  1846. ep->name, buf,
  1847. ep->double_buf ? "dbuf " : "",
  1848. ({ char *s;
  1849. switch (ep->ackwait) {
  1850. case 0:
  1851. s = "";
  1852. break;
  1853. case 1:
  1854. s = "(ackw) ";
  1855. break;
  1856. case 2:
  1857. s = "(ackw2) ";
  1858. break;
  1859. default:
  1860. s = "(?) ";
  1861. break;
  1862. } s; }),
  1863. ep->irqs, stat_flg,
  1864. (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
  1865. (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
  1866. (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
  1867. (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
  1868. (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
  1869. (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
  1870. (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
  1871. (stat_flg & UDC_STALL) ? "STALL " : "",
  1872. (stat_flg & UDC_NAK) ? "NAK " : "",
  1873. (stat_flg & UDC_ACK) ? "ACK " : "",
  1874. (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
  1875. (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
  1876. (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
  1877. if (list_empty(&ep->queue))
  1878. seq_printf(s, "\t(queue empty)\n");
  1879. else
  1880. list_for_each_entry(req, &ep->queue, queue) {
  1881. unsigned length = req->req.actual;
  1882. if (use_dma && buf[0]) {
  1883. length += ((ep->bEndpointAddress & USB_DIR_IN)
  1884. ? dma_src_len : dma_dest_len)
  1885. (ep, req->req.dma + length);
  1886. buf[0] = 0;
  1887. }
  1888. seq_printf(s, "\treq %p len %d/%d buf %p\n",
  1889. &req->req, length,
  1890. req->req.length, req->req.buf);
  1891. }
  1892. }
  1893. static char *trx_mode(unsigned m, int enabled)
  1894. {
  1895. switch (m) {
  1896. case 0:
  1897. return enabled ? "*6wire" : "unused";
  1898. case 1:
  1899. return "4wire";
  1900. case 2:
  1901. return "3wire";
  1902. case 3:
  1903. return "6wire";
  1904. default:
  1905. return "unknown";
  1906. }
  1907. }
  1908. static int proc_otg_show(struct seq_file *s)
  1909. {
  1910. u32 tmp;
  1911. u32 trans = 0;
  1912. char *ctrl_name = "(UNKNOWN)";
  1913. tmp = omap_readl(OTG_REV);
  1914. ctrl_name = "tranceiver_ctrl";
  1915. trans = omap_readw(USB_TRANSCEIVER_CTRL);
  1916. seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
  1917. tmp >> 4, tmp & 0xf, ctrl_name, trans);
  1918. tmp = omap_readw(OTG_SYSCON_1);
  1919. seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
  1920. FOURBITS "\n", tmp,
  1921. trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
  1922. trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
  1923. (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
  1924. ? "internal"
  1925. : trx_mode(USB0_TRX_MODE(tmp), 1),
  1926. (tmp & OTG_IDLE_EN) ? " !otg" : "",
  1927. (tmp & HST_IDLE_EN) ? " !host" : "",
  1928. (tmp & DEV_IDLE_EN) ? " !dev" : "",
  1929. (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
  1930. tmp = omap_readl(OTG_SYSCON_2);
  1931. seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
  1932. " b_ase_brst=%d hmc=%d\n", tmp,
  1933. (tmp & OTG_EN) ? " otg_en" : "",
  1934. (tmp & USBX_SYNCHRO) ? " synchro" : "",
  1935. /* much more SRP stuff */
  1936. (tmp & SRP_DATA) ? " srp_data" : "",
  1937. (tmp & SRP_VBUS) ? " srp_vbus" : "",
  1938. (tmp & OTG_PADEN) ? " otg_paden" : "",
  1939. (tmp & HMC_PADEN) ? " hmc_paden" : "",
  1940. (tmp & UHOST_EN) ? " uhost_en" : "",
  1941. (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
  1942. (tmp & HMC_TLLATTACH) ? " tllattach" : "",
  1943. B_ASE_BRST(tmp),
  1944. OTG_HMC(tmp));
  1945. tmp = omap_readl(OTG_CTRL);
  1946. seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
  1947. (tmp & OTG_ASESSVLD) ? " asess" : "",
  1948. (tmp & OTG_BSESSEND) ? " bsess_end" : "",
  1949. (tmp & OTG_BSESSVLD) ? " bsess" : "",
  1950. (tmp & OTG_VBUSVLD) ? " vbus" : "",
  1951. (tmp & OTG_ID) ? " id" : "",
  1952. (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
  1953. (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
  1954. (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
  1955. (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
  1956. (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
  1957. (tmp & OTG_BUSDROP) ? " busdrop" : "",
  1958. (tmp & OTG_PULLDOWN) ? " down" : "",
  1959. (tmp & OTG_PULLUP) ? " up" : "",
  1960. (tmp & OTG_DRV_VBUS) ? " drv" : "",
  1961. (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
  1962. (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
  1963. (tmp & OTG_PU_ID) ? " pu_id" : ""
  1964. );
  1965. tmp = omap_readw(OTG_IRQ_EN);
  1966. seq_printf(s, "otg_irq_en %04x" "\n", tmp);
  1967. tmp = omap_readw(OTG_IRQ_SRC);
  1968. seq_printf(s, "otg_irq_src %04x" "\n", tmp);
  1969. tmp = omap_readw(OTG_OUTCTRL);
  1970. seq_printf(s, "otg_outctrl %04x" "\n", tmp);
  1971. tmp = omap_readw(OTG_TEST);
  1972. seq_printf(s, "otg_test %04x" "\n", tmp);
  1973. return 0;
  1974. }
  1975. static int proc_udc_show(struct seq_file *s, void *_)
  1976. {
  1977. u32 tmp;
  1978. struct omap_ep *ep;
  1979. unsigned long flags;
  1980. spin_lock_irqsave(&udc->lock, flags);
  1981. seq_printf(s, "%s, version: " DRIVER_VERSION
  1982. #ifdef USE_ISO
  1983. " (iso)"
  1984. #endif
  1985. "%s\n",
  1986. driver_desc,
  1987. use_dma ? " (dma)" : "");
  1988. tmp = omap_readw(UDC_REV) & 0xff;
  1989. seq_printf(s,
  1990. "UDC rev %d.%d, fifo mode %d, gadget %s\n"
  1991. "hmc %d, transceiver %s\n",
  1992. tmp >> 4, tmp & 0xf,
  1993. fifo_mode,
  1994. udc->driver ? udc->driver->driver.name : "(none)",
  1995. HMC,
  1996. udc->transceiver
  1997. ? udc->transceiver->label
  1998. : (cpu_is_omap1710()
  1999. ? "external" : "(none)"));
  2000. seq_printf(s, "ULPD control %04x req %04x status %04x\n",
  2001. omap_readw(ULPD_CLOCK_CTRL),
  2002. omap_readw(ULPD_SOFT_REQ),
  2003. omap_readw(ULPD_STATUS_REQ));
  2004. /* OTG controller registers */
  2005. if (!cpu_is_omap15xx())
  2006. proc_otg_show(s);
  2007. tmp = omap_readw(UDC_SYSCON1);
  2008. seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
  2009. (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
  2010. (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
  2011. (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
  2012. (tmp & UDC_NAK_EN) ? " nak" : "",
  2013. (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
  2014. (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
  2015. (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
  2016. (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
  2017. /* syscon2 is write-only */
  2018. /* UDC controller registers */
  2019. if (!(tmp & UDC_PULLUP_EN)) {
  2020. seq_printf(s, "(suspended)\n");
  2021. spin_unlock_irqrestore(&udc->lock, flags);
  2022. return 0;
  2023. }
  2024. tmp = omap_readw(UDC_DEVSTAT);
  2025. seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
  2026. (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
  2027. (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
  2028. (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
  2029. (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
  2030. (tmp & UDC_USB_RESET) ? " usb_reset" : "",
  2031. (tmp & UDC_SUS) ? " SUS" : "",
  2032. (tmp & UDC_CFG) ? " CFG" : "",
  2033. (tmp & UDC_ADD) ? " ADD" : "",
  2034. (tmp & UDC_DEF) ? " DEF" : "",
  2035. (tmp & UDC_ATT) ? " ATT" : "");
  2036. seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
  2037. tmp = omap_readw(UDC_IRQ_EN);
  2038. seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
  2039. (tmp & UDC_SOF_IE) ? " sof" : "",
  2040. (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
  2041. (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
  2042. (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
  2043. (tmp & UDC_EP0_IE) ? " ep0" : "");
  2044. tmp = omap_readw(UDC_IRQ_SRC);
  2045. seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
  2046. (tmp & UDC_TXN_DONE) ? " txn_done" : "",
  2047. (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
  2048. (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
  2049. (tmp & UDC_IRQ_SOF) ? " sof" : "",
  2050. (tmp & UDC_EPN_RX) ? " epn_rx" : "",
  2051. (tmp & UDC_EPN_TX) ? " epn_tx" : "",
  2052. (tmp & UDC_DS_CHG) ? " ds_chg" : "",
  2053. (tmp & UDC_SETUP) ? " setup" : "",
  2054. (tmp & UDC_EP0_RX) ? " ep0out" : "",
  2055. (tmp & UDC_EP0_TX) ? " ep0in" : "");
  2056. if (use_dma) {
  2057. unsigned i;
  2058. tmp = omap_readw(UDC_DMA_IRQ_EN);
  2059. seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
  2060. (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
  2061. (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
  2062. (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
  2063. (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
  2064. (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
  2065. (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
  2066. (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
  2067. (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
  2068. (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
  2069. tmp = omap_readw(UDC_RXDMA_CFG);
  2070. seq_printf(s, "rxdma_cfg %04x\n", tmp);
  2071. if (tmp) {
  2072. for (i = 0; i < 3; i++) {
  2073. if ((tmp & (0x0f << (i * 4))) == 0)
  2074. continue;
  2075. seq_printf(s, "rxdma[%d] %04x\n", i,
  2076. omap_readw(UDC_RXDMA(i + 1)));
  2077. }
  2078. }
  2079. tmp = omap_readw(UDC_TXDMA_CFG);
  2080. seq_printf(s, "txdma_cfg %04x\n", tmp);
  2081. if (tmp) {
  2082. for (i = 0; i < 3; i++) {
  2083. if (!(tmp & (0x0f << (i * 4))))
  2084. continue;
  2085. seq_printf(s, "txdma[%d] %04x\n", i,
  2086. omap_readw(UDC_TXDMA(i + 1)));
  2087. }
  2088. }
  2089. }
  2090. tmp = omap_readw(UDC_DEVSTAT);
  2091. if (tmp & UDC_ATT) {
  2092. proc_ep_show(s, &udc->ep[0]);
  2093. if (tmp & UDC_ADD) {
  2094. list_for_each_entry(ep, &udc->gadget.ep_list,
  2095. ep.ep_list) {
  2096. if (ep->ep.desc)
  2097. proc_ep_show(s, ep);
  2098. }
  2099. }
  2100. }
  2101. spin_unlock_irqrestore(&udc->lock, flags);
  2102. return 0;
  2103. }
  2104. static void create_proc_file(void)
  2105. {
  2106. proc_create_single(proc_filename, 0, NULL, proc_udc_show);
  2107. }
  2108. static void remove_proc_file(void)
  2109. {
  2110. remove_proc_entry(proc_filename, NULL);
  2111. }
  2112. #else
  2113. static inline void create_proc_file(void) {}
  2114. static inline void remove_proc_file(void) {}
  2115. #endif
  2116. /*-------------------------------------------------------------------------*/
  2117. /* Before this controller can enumerate, we need to pick an endpoint
  2118. * configuration, or "fifo_mode" That involves allocating 2KB of packet
  2119. * buffer space among the endpoints we'll be operating.
  2120. *
  2121. * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
  2122. * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
  2123. * capability yet though.
  2124. */
  2125. static unsigned
  2126. omap_ep_setup(char *name, u8 addr, u8 type,
  2127. unsigned buf, unsigned maxp, int dbuf)
  2128. {
  2129. struct omap_ep *ep;
  2130. u16 epn_rxtx = 0;
  2131. /* OUT endpoints first, then IN */
  2132. ep = &udc->ep[addr & 0xf];
  2133. if (addr & USB_DIR_IN)
  2134. ep += 16;
  2135. /* in case of ep init table bugs */
  2136. BUG_ON(ep->name[0]);
  2137. /* chip setup ... bit values are same for IN, OUT */
  2138. if (type == USB_ENDPOINT_XFER_ISOC) {
  2139. switch (maxp) {
  2140. case 8:
  2141. epn_rxtx = 0 << 12;
  2142. break;
  2143. case 16:
  2144. epn_rxtx = 1 << 12;
  2145. break;
  2146. case 32:
  2147. epn_rxtx = 2 << 12;
  2148. break;
  2149. case 64:
  2150. epn_rxtx = 3 << 12;
  2151. break;
  2152. case 128:
  2153. epn_rxtx = 4 << 12;
  2154. break;
  2155. case 256:
  2156. epn_rxtx = 5 << 12;
  2157. break;
  2158. case 512:
  2159. epn_rxtx = 6 << 12;
  2160. break;
  2161. default:
  2162. BUG();
  2163. }
  2164. epn_rxtx |= UDC_EPN_RX_ISO;
  2165. dbuf = 1;
  2166. } else {
  2167. /* double-buffering "not supported" on 15xx,
  2168. * and ignored for PIO-IN on newer chips
  2169. * (for more reliable behavior)
  2170. */
  2171. if (!use_dma || cpu_is_omap15xx())
  2172. dbuf = 0;
  2173. switch (maxp) {
  2174. case 8:
  2175. epn_rxtx = 0 << 12;
  2176. break;
  2177. case 16:
  2178. epn_rxtx = 1 << 12;
  2179. break;
  2180. case 32:
  2181. epn_rxtx = 2 << 12;
  2182. break;
  2183. case 64:
  2184. epn_rxtx = 3 << 12;
  2185. break;
  2186. default:
  2187. BUG();
  2188. }
  2189. if (dbuf && addr)
  2190. epn_rxtx |= UDC_EPN_RX_DB;
  2191. timer_setup(&ep->timer, pio_out_timer, 0);
  2192. }
  2193. if (addr)
  2194. epn_rxtx |= UDC_EPN_RX_VALID;
  2195. BUG_ON(buf & 0x07);
  2196. epn_rxtx |= buf >> 3;
  2197. DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
  2198. name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
  2199. if (addr & USB_DIR_IN)
  2200. omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
  2201. else
  2202. omap_writew(epn_rxtx, UDC_EP_RX(addr));
  2203. /* next endpoint's buffer starts after this one's */
  2204. buf += maxp;
  2205. if (dbuf)
  2206. buf += maxp;
  2207. BUG_ON(buf > 2048);
  2208. /* set up driver data structures */
  2209. BUG_ON(strlen(name) >= sizeof ep->name);
  2210. strlcpy(ep->name, name, sizeof ep->name);
  2211. INIT_LIST_HEAD(&ep->queue);
  2212. INIT_LIST_HEAD(&ep->iso);
  2213. ep->bEndpointAddress = addr;
  2214. ep->bmAttributes = type;
  2215. ep->double_buf = dbuf;
  2216. ep->udc = udc;
  2217. switch (type) {
  2218. case USB_ENDPOINT_XFER_CONTROL:
  2219. ep->ep.caps.type_control = true;
  2220. ep->ep.caps.dir_in = true;
  2221. ep->ep.caps.dir_out = true;
  2222. break;
  2223. case USB_ENDPOINT_XFER_ISOC:
  2224. ep->ep.caps.type_iso = true;
  2225. break;
  2226. case USB_ENDPOINT_XFER_BULK:
  2227. ep->ep.caps.type_bulk = true;
  2228. break;
  2229. case USB_ENDPOINT_XFER_INT:
  2230. ep->ep.caps.type_int = true;
  2231. break;
  2232. };
  2233. if (addr & USB_DIR_IN)
  2234. ep->ep.caps.dir_in = true;
  2235. else
  2236. ep->ep.caps.dir_out = true;
  2237. ep->ep.name = ep->name;
  2238. ep->ep.ops = &omap_ep_ops;
  2239. ep->maxpacket = maxp;
  2240. usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
  2241. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  2242. return buf;
  2243. }
  2244. static void omap_udc_release(struct device *dev)
  2245. {
  2246. pullup_disable(udc);
  2247. if (!IS_ERR_OR_NULL(udc->transceiver)) {
  2248. usb_put_phy(udc->transceiver);
  2249. udc->transceiver = NULL;
  2250. }
  2251. omap_writew(0, UDC_SYSCON1);
  2252. remove_proc_file();
  2253. if (udc->dc_clk) {
  2254. if (udc->clk_requested)
  2255. omap_udc_enable_clock(0);
  2256. clk_put(udc->hhc_clk);
  2257. clk_put(udc->dc_clk);
  2258. }
  2259. if (udc->done)
  2260. complete(udc->done);
  2261. kfree(udc);
  2262. }
  2263. static int
  2264. omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
  2265. {
  2266. unsigned tmp, buf;
  2267. /* abolish any previous hardware state */
  2268. omap_writew(0, UDC_SYSCON1);
  2269. omap_writew(0, UDC_IRQ_EN);
  2270. omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
  2271. omap_writew(0, UDC_DMA_IRQ_EN);
  2272. omap_writew(0, UDC_RXDMA_CFG);
  2273. omap_writew(0, UDC_TXDMA_CFG);
  2274. /* UDC_PULLUP_EN gates the chip clock */
  2275. /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
  2276. udc = kzalloc(sizeof(*udc), GFP_KERNEL);
  2277. if (!udc)
  2278. return -ENOMEM;
  2279. spin_lock_init(&udc->lock);
  2280. udc->gadget.ops = &omap_gadget_ops;
  2281. udc->gadget.ep0 = &udc->ep[0].ep;
  2282. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2283. INIT_LIST_HEAD(&udc->iso);
  2284. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2285. udc->gadget.max_speed = USB_SPEED_FULL;
  2286. udc->gadget.name = driver_name;
  2287. udc->gadget.quirk_ep_out_aligned_size = 1;
  2288. udc->transceiver = xceiv;
  2289. /* ep0 is special; put it right after the SETUP buffer */
  2290. buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
  2291. 8 /* after SETUP */, 64 /* maxpacket */, 0);
  2292. list_del_init(&udc->ep[0].ep.ep_list);
  2293. /* initially disable all non-ep0 endpoints */
  2294. for (tmp = 1; tmp < 15; tmp++) {
  2295. omap_writew(0, UDC_EP_RX(tmp));
  2296. omap_writew(0, UDC_EP_TX(tmp));
  2297. }
  2298. #define OMAP_BULK_EP(name, addr) \
  2299. buf = omap_ep_setup(name "-bulk", addr, \
  2300. USB_ENDPOINT_XFER_BULK, buf, 64, 1);
  2301. #define OMAP_INT_EP(name, addr, maxp) \
  2302. buf = omap_ep_setup(name "-int", addr, \
  2303. USB_ENDPOINT_XFER_INT, buf, maxp, 0);
  2304. #define OMAP_ISO_EP(name, addr, maxp) \
  2305. buf = omap_ep_setup(name "-iso", addr, \
  2306. USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
  2307. switch (fifo_mode) {
  2308. case 0:
  2309. OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
  2310. OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
  2311. OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
  2312. break;
  2313. case 1:
  2314. OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
  2315. OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
  2316. OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
  2317. OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
  2318. OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
  2319. OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
  2320. OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
  2321. OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
  2322. OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
  2323. OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
  2324. OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
  2325. OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
  2326. OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
  2327. OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
  2328. OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
  2329. OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
  2330. OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
  2331. OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
  2332. OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
  2333. OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
  2334. OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
  2335. OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
  2336. break;
  2337. #ifdef USE_ISO
  2338. case 2: /* mixed iso/bulk */
  2339. OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
  2340. OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
  2341. OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
  2342. OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
  2343. OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
  2344. OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
  2345. OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
  2346. OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
  2347. break;
  2348. case 3: /* mixed bulk/iso */
  2349. OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
  2350. OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
  2351. OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
  2352. OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
  2353. OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
  2354. OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
  2355. OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
  2356. OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
  2357. OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
  2358. break;
  2359. #endif
  2360. /* add more modes as needed */
  2361. default:
  2362. ERR("unsupported fifo_mode #%d\n", fifo_mode);
  2363. return -ENODEV;
  2364. }
  2365. omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
  2366. INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
  2367. return 0;
  2368. }
  2369. static int omap_udc_probe(struct platform_device *pdev)
  2370. {
  2371. int status = -ENODEV;
  2372. int hmc;
  2373. struct usb_phy *xceiv = NULL;
  2374. const char *type = NULL;
  2375. struct omap_usb_config *config = dev_get_platdata(&pdev->dev);
  2376. struct clk *dc_clk = NULL;
  2377. struct clk *hhc_clk = NULL;
  2378. if (cpu_is_omap7xx())
  2379. use_dma = 0;
  2380. /* NOTE: "knows" the order of the resources! */
  2381. if (!request_mem_region(pdev->resource[0].start,
  2382. pdev->resource[0].end - pdev->resource[0].start + 1,
  2383. driver_name)) {
  2384. DBG("request_mem_region failed\n");
  2385. return -EBUSY;
  2386. }
  2387. if (cpu_is_omap16xx()) {
  2388. dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
  2389. hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
  2390. BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
  2391. /* can't use omap_udc_enable_clock yet */
  2392. clk_enable(dc_clk);
  2393. clk_enable(hhc_clk);
  2394. udelay(100);
  2395. }
  2396. if (cpu_is_omap7xx()) {
  2397. dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
  2398. hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
  2399. BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
  2400. /* can't use omap_udc_enable_clock yet */
  2401. clk_enable(dc_clk);
  2402. clk_enable(hhc_clk);
  2403. udelay(100);
  2404. }
  2405. INFO("OMAP UDC rev %d.%d%s\n",
  2406. omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
  2407. config->otg ? ", Mini-AB" : "");
  2408. /* use the mode given to us by board init code */
  2409. if (cpu_is_omap15xx()) {
  2410. hmc = HMC_1510;
  2411. type = "(unknown)";
  2412. if (machine_without_vbus_sense()) {
  2413. /* just set up software VBUS detect, and then
  2414. * later rig it so we always report VBUS.
  2415. * FIXME without really sensing VBUS, we can't
  2416. * know when to turn PULLUP_EN on/off; and that
  2417. * means we always "need" the 48MHz clock.
  2418. */
  2419. u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
  2420. tmp &= ~VBUS_CTRL_1510;
  2421. omap_writel(tmp, FUNC_MUX_CTRL_0);
  2422. tmp |= VBUS_MODE_1510;
  2423. tmp &= ~VBUS_CTRL_1510;
  2424. omap_writel(tmp, FUNC_MUX_CTRL_0);
  2425. }
  2426. } else {
  2427. /* The transceiver may package some GPIO logic or handle
  2428. * loopback and/or transceiverless setup; if we find one,
  2429. * use it. Except for OTG, we don't _need_ to talk to one;
  2430. * but not having one probably means no VBUS detection.
  2431. */
  2432. xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  2433. if (!IS_ERR_OR_NULL(xceiv))
  2434. type = xceiv->label;
  2435. else if (config->otg) {
  2436. DBG("OTG requires external transceiver!\n");
  2437. goto cleanup0;
  2438. }
  2439. hmc = HMC_1610;
  2440. switch (hmc) {
  2441. case 0: /* POWERUP DEFAULT == 0 */
  2442. case 4:
  2443. case 12:
  2444. case 20:
  2445. if (!cpu_is_omap1710()) {
  2446. type = "integrated";
  2447. break;
  2448. }
  2449. /* FALL THROUGH */
  2450. case 3:
  2451. case 11:
  2452. case 16:
  2453. case 19:
  2454. case 25:
  2455. if (IS_ERR_OR_NULL(xceiv)) {
  2456. DBG("external transceiver not registered!\n");
  2457. type = "unknown";
  2458. }
  2459. break;
  2460. case 21: /* internal loopback */
  2461. type = "loopback";
  2462. break;
  2463. case 14: /* transceiverless */
  2464. if (cpu_is_omap1710())
  2465. goto bad_on_1710;
  2466. /* FALL THROUGH */
  2467. case 13:
  2468. case 15:
  2469. type = "no";
  2470. break;
  2471. default:
  2472. bad_on_1710:
  2473. ERR("unrecognized UDC HMC mode %d\n", hmc);
  2474. goto cleanup0;
  2475. }
  2476. }
  2477. INFO("hmc mode %d, %s transceiver\n", hmc, type);
  2478. /* a "gadget" abstracts/virtualizes the controller */
  2479. status = omap_udc_setup(pdev, xceiv);
  2480. if (status)
  2481. goto cleanup0;
  2482. xceiv = NULL;
  2483. /* "udc" is now valid */
  2484. pullup_disable(udc);
  2485. #if IS_ENABLED(CONFIG_USB_OHCI_HCD)
  2486. udc->gadget.is_otg = (config->otg != 0);
  2487. #endif
  2488. /* starting with omap1710 es2.0, clear toggle is a separate bit */
  2489. if (omap_readw(UDC_REV) >= 0x61)
  2490. udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
  2491. else
  2492. udc->clr_halt = UDC_RESET_EP;
  2493. /* USB general purpose IRQ: ep0, state changes, dma, etc */
  2494. status = devm_request_irq(&pdev->dev, pdev->resource[1].start,
  2495. omap_udc_irq, 0, driver_name, udc);
  2496. if (status != 0) {
  2497. ERR("can't get irq %d, err %d\n",
  2498. (int) pdev->resource[1].start, status);
  2499. goto cleanup1;
  2500. }
  2501. /* USB "non-iso" IRQ (PIO for all but ep0) */
  2502. status = devm_request_irq(&pdev->dev, pdev->resource[2].start,
  2503. omap_udc_pio_irq, 0, "omap_udc pio", udc);
  2504. if (status != 0) {
  2505. ERR("can't get irq %d, err %d\n",
  2506. (int) pdev->resource[2].start, status);
  2507. goto cleanup1;
  2508. }
  2509. #ifdef USE_ISO
  2510. status = devm_request_irq(&pdev->dev, pdev->resource[3].start,
  2511. omap_udc_iso_irq, 0, "omap_udc iso", udc);
  2512. if (status != 0) {
  2513. ERR("can't get irq %d, err %d\n",
  2514. (int) pdev->resource[3].start, status);
  2515. goto cleanup1;
  2516. }
  2517. #endif
  2518. if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
  2519. udc->dc_clk = dc_clk;
  2520. udc->hhc_clk = hhc_clk;
  2521. clk_disable(hhc_clk);
  2522. clk_disable(dc_clk);
  2523. }
  2524. create_proc_file();
  2525. return usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
  2526. omap_udc_release);
  2527. cleanup1:
  2528. kfree(udc);
  2529. udc = NULL;
  2530. cleanup0:
  2531. if (!IS_ERR_OR_NULL(xceiv))
  2532. usb_put_phy(xceiv);
  2533. if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
  2534. clk_disable(hhc_clk);
  2535. clk_disable(dc_clk);
  2536. clk_put(hhc_clk);
  2537. clk_put(dc_clk);
  2538. }
  2539. release_mem_region(pdev->resource[0].start,
  2540. pdev->resource[0].end - pdev->resource[0].start + 1);
  2541. return status;
  2542. }
  2543. static int omap_udc_remove(struct platform_device *pdev)
  2544. {
  2545. DECLARE_COMPLETION_ONSTACK(done);
  2546. udc->done = &done;
  2547. usb_del_gadget_udc(&udc->gadget);
  2548. wait_for_completion(&done);
  2549. release_mem_region(pdev->resource[0].start,
  2550. pdev->resource[0].end - pdev->resource[0].start + 1);
  2551. return 0;
  2552. }
  2553. /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
  2554. * system is forced into deep sleep
  2555. *
  2556. * REVISIT we should probably reject suspend requests when there's a host
  2557. * session active, rather than disconnecting, at least on boards that can
  2558. * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
  2559. * make host resumes and VBUS detection trigger OMAP wakeup events; that
  2560. * may involve talking to an external transceiver (e.g. isp1301).
  2561. */
  2562. static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
  2563. {
  2564. u32 devstat;
  2565. devstat = omap_readw(UDC_DEVSTAT);
  2566. /* we're requesting 48 MHz clock if the pullup is enabled
  2567. * (== we're attached to the host) and we're not suspended,
  2568. * which would prevent entry to deep sleep...
  2569. */
  2570. if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
  2571. WARNING("session active; suspend requires disconnect\n");
  2572. omap_pullup(&udc->gadget, 0);
  2573. }
  2574. return 0;
  2575. }
  2576. static int omap_udc_resume(struct platform_device *dev)
  2577. {
  2578. DBG("resume + wakeup/SRP\n");
  2579. omap_pullup(&udc->gadget, 1);
  2580. /* maybe the host would enumerate us if we nudged it */
  2581. msleep(100);
  2582. return omap_wakeup(&udc->gadget);
  2583. }
  2584. /*-------------------------------------------------------------------------*/
  2585. static struct platform_driver udc_driver = {
  2586. .probe = omap_udc_probe,
  2587. .remove = omap_udc_remove,
  2588. .suspend = omap_udc_suspend,
  2589. .resume = omap_udc_resume,
  2590. .driver = {
  2591. .name = (char *) driver_name,
  2592. },
  2593. };
  2594. module_platform_driver(udc_driver);
  2595. MODULE_DESCRIPTION(DRIVER_DESC);
  2596. MODULE_LICENSE("GPL");
  2597. MODULE_ALIAS("platform:omap_udc");