ak4113.c 18 KB

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  1. /*
  2. * Routines for control of the AK4113 via I2C/4-wire serial interface
  3. * IEC958 (S/PDIF) receiver by Asahi Kasei
  4. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  5. * Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/module.h>
  26. #include <sound/core.h>
  27. #include <sound/control.h>
  28. #include <sound/pcm.h>
  29. #include <sound/ak4113.h>
  30. #include <sound/asoundef.h>
  31. #include <sound/info.h>
  32. MODULE_AUTHOR("Pavel Hofman <pavel.hofman@ivitera.com>");
  33. MODULE_DESCRIPTION("AK4113 IEC958 (S/PDIF) receiver by Asahi Kasei");
  34. MODULE_LICENSE("GPL");
  35. #define AK4113_ADDR 0x00 /* fixed address */
  36. static void ak4113_stats(struct work_struct *work);
  37. static void ak4113_init_regs(struct ak4113 *chip);
  38. static void reg_write(struct ak4113 *ak4113, unsigned char reg,
  39. unsigned char val)
  40. {
  41. ak4113->write(ak4113->private_data, reg, val);
  42. if (reg < sizeof(ak4113->regmap))
  43. ak4113->regmap[reg] = val;
  44. }
  45. static inline unsigned char reg_read(struct ak4113 *ak4113, unsigned char reg)
  46. {
  47. return ak4113->read(ak4113->private_data, reg);
  48. }
  49. static void snd_ak4113_free(struct ak4113 *chip)
  50. {
  51. atomic_inc(&chip->wq_processing); /* don't schedule new work */
  52. cancel_delayed_work_sync(&chip->work);
  53. kfree(chip);
  54. }
  55. static int snd_ak4113_dev_free(struct snd_device *device)
  56. {
  57. struct ak4113 *chip = device->device_data;
  58. snd_ak4113_free(chip);
  59. return 0;
  60. }
  61. int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read,
  62. ak4113_write_t *write, const unsigned char *pgm,
  63. void *private_data, struct ak4113 **r_ak4113)
  64. {
  65. struct ak4113 *chip;
  66. int err;
  67. unsigned char reg;
  68. static struct snd_device_ops ops = {
  69. .dev_free = snd_ak4113_dev_free,
  70. };
  71. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  72. if (chip == NULL)
  73. return -ENOMEM;
  74. spin_lock_init(&chip->lock);
  75. chip->card = card;
  76. chip->read = read;
  77. chip->write = write;
  78. chip->private_data = private_data;
  79. INIT_DELAYED_WORK(&chip->work, ak4113_stats);
  80. atomic_set(&chip->wq_processing, 0);
  81. mutex_init(&chip->reinit_mutex);
  82. for (reg = 0; reg < AK4113_WRITABLE_REGS ; reg++)
  83. chip->regmap[reg] = pgm[reg];
  84. ak4113_init_regs(chip);
  85. chip->rcs0 = reg_read(chip, AK4113_REG_RCS0) & ~(AK4113_QINT |
  86. AK4113_CINT | AK4113_STC);
  87. chip->rcs1 = reg_read(chip, AK4113_REG_RCS1);
  88. chip->rcs2 = reg_read(chip, AK4113_REG_RCS2);
  89. err = snd_device_new(card, SNDRV_DEV_CODEC, chip, &ops);
  90. if (err < 0)
  91. goto __fail;
  92. if (r_ak4113)
  93. *r_ak4113 = chip;
  94. return 0;
  95. __fail:
  96. snd_ak4113_free(chip);
  97. return err;
  98. }
  99. EXPORT_SYMBOL_GPL(snd_ak4113_create);
  100. void snd_ak4113_reg_write(struct ak4113 *chip, unsigned char reg,
  101. unsigned char mask, unsigned char val)
  102. {
  103. if (reg >= AK4113_WRITABLE_REGS)
  104. return;
  105. reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val);
  106. }
  107. EXPORT_SYMBOL_GPL(snd_ak4113_reg_write);
  108. static void ak4113_init_regs(struct ak4113 *chip)
  109. {
  110. unsigned char old = chip->regmap[AK4113_REG_PWRDN], reg;
  111. /* bring the chip to reset state and powerdown state */
  112. reg_write(chip, AK4113_REG_PWRDN, old & ~(AK4113_RST|AK4113_PWN));
  113. udelay(200);
  114. /* release reset, but leave powerdown */
  115. reg_write(chip, AK4113_REG_PWRDN, (old | AK4113_RST) & ~AK4113_PWN);
  116. udelay(200);
  117. for (reg = 1; reg < AK4113_WRITABLE_REGS; reg++)
  118. reg_write(chip, reg, chip->regmap[reg]);
  119. /* release powerdown, everything is initialized now */
  120. reg_write(chip, AK4113_REG_PWRDN, old | AK4113_RST | AK4113_PWN);
  121. }
  122. void snd_ak4113_reinit(struct ak4113 *chip)
  123. {
  124. if (atomic_inc_return(&chip->wq_processing) == 1)
  125. cancel_delayed_work_sync(&chip->work);
  126. mutex_lock(&chip->reinit_mutex);
  127. ak4113_init_regs(chip);
  128. mutex_unlock(&chip->reinit_mutex);
  129. /* bring up statistics / event queing */
  130. if (atomic_dec_and_test(&chip->wq_processing))
  131. schedule_delayed_work(&chip->work, HZ / 10);
  132. }
  133. EXPORT_SYMBOL_GPL(snd_ak4113_reinit);
  134. static unsigned int external_rate(unsigned char rcs1)
  135. {
  136. switch (rcs1 & (AK4113_FS0|AK4113_FS1|AK4113_FS2|AK4113_FS3)) {
  137. case AK4113_FS_8000HZ:
  138. return 8000;
  139. case AK4113_FS_11025HZ:
  140. return 11025;
  141. case AK4113_FS_16000HZ:
  142. return 16000;
  143. case AK4113_FS_22050HZ:
  144. return 22050;
  145. case AK4113_FS_24000HZ:
  146. return 24000;
  147. case AK4113_FS_32000HZ:
  148. return 32000;
  149. case AK4113_FS_44100HZ:
  150. return 44100;
  151. case AK4113_FS_48000HZ:
  152. return 48000;
  153. case AK4113_FS_64000HZ:
  154. return 64000;
  155. case AK4113_FS_88200HZ:
  156. return 88200;
  157. case AK4113_FS_96000HZ:
  158. return 96000;
  159. case AK4113_FS_176400HZ:
  160. return 176400;
  161. case AK4113_FS_192000HZ:
  162. return 192000;
  163. default:
  164. return 0;
  165. }
  166. }
  167. static int snd_ak4113_in_error_info(struct snd_kcontrol *kcontrol,
  168. struct snd_ctl_elem_info *uinfo)
  169. {
  170. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  171. uinfo->count = 1;
  172. uinfo->value.integer.min = 0;
  173. uinfo->value.integer.max = LONG_MAX;
  174. return 0;
  175. }
  176. static int snd_ak4113_in_error_get(struct snd_kcontrol *kcontrol,
  177. struct snd_ctl_elem_value *ucontrol)
  178. {
  179. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  180. spin_lock_irq(&chip->lock);
  181. ucontrol->value.integer.value[0] =
  182. chip->errors[kcontrol->private_value];
  183. chip->errors[kcontrol->private_value] = 0;
  184. spin_unlock_irq(&chip->lock);
  185. return 0;
  186. }
  187. #define snd_ak4113_in_bit_info snd_ctl_boolean_mono_info
  188. static int snd_ak4113_in_bit_get(struct snd_kcontrol *kcontrol,
  189. struct snd_ctl_elem_value *ucontrol)
  190. {
  191. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  192. unsigned char reg = kcontrol->private_value & 0xff;
  193. unsigned char bit = (kcontrol->private_value >> 8) & 0xff;
  194. unsigned char inv = (kcontrol->private_value >> 31) & 1;
  195. ucontrol->value.integer.value[0] =
  196. ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv;
  197. return 0;
  198. }
  199. static int snd_ak4113_rx_info(struct snd_kcontrol *kcontrol,
  200. struct snd_ctl_elem_info *uinfo)
  201. {
  202. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  203. uinfo->count = 1;
  204. uinfo->value.integer.min = 0;
  205. uinfo->value.integer.max = 5;
  206. return 0;
  207. }
  208. static int snd_ak4113_rx_get(struct snd_kcontrol *kcontrol,
  209. struct snd_ctl_elem_value *ucontrol)
  210. {
  211. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  212. ucontrol->value.integer.value[0] =
  213. (AK4113_IPS(chip->regmap[AK4113_REG_IO1]));
  214. return 0;
  215. }
  216. static int snd_ak4113_rx_put(struct snd_kcontrol *kcontrol,
  217. struct snd_ctl_elem_value *ucontrol)
  218. {
  219. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  220. int change;
  221. u8 old_val;
  222. spin_lock_irq(&chip->lock);
  223. old_val = chip->regmap[AK4113_REG_IO1];
  224. change = ucontrol->value.integer.value[0] != AK4113_IPS(old_val);
  225. if (change)
  226. reg_write(chip, AK4113_REG_IO1,
  227. (old_val & (~AK4113_IPS(0xff))) |
  228. (AK4113_IPS(ucontrol->value.integer.value[0])));
  229. spin_unlock_irq(&chip->lock);
  230. return change;
  231. }
  232. static int snd_ak4113_rate_info(struct snd_kcontrol *kcontrol,
  233. struct snd_ctl_elem_info *uinfo)
  234. {
  235. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  236. uinfo->count = 1;
  237. uinfo->value.integer.min = 0;
  238. uinfo->value.integer.max = 192000;
  239. return 0;
  240. }
  241. static int snd_ak4113_rate_get(struct snd_kcontrol *kcontrol,
  242. struct snd_ctl_elem_value *ucontrol)
  243. {
  244. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  245. ucontrol->value.integer.value[0] = external_rate(reg_read(chip,
  246. AK4113_REG_RCS1));
  247. return 0;
  248. }
  249. static int snd_ak4113_spdif_info(struct snd_kcontrol *kcontrol,
  250. struct snd_ctl_elem_info *uinfo)
  251. {
  252. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  253. uinfo->count = 1;
  254. return 0;
  255. }
  256. static int snd_ak4113_spdif_get(struct snd_kcontrol *kcontrol,
  257. struct snd_ctl_elem_value *ucontrol)
  258. {
  259. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  260. unsigned i;
  261. for (i = 0; i < AK4113_REG_RXCSB_SIZE; i++)
  262. ucontrol->value.iec958.status[i] = reg_read(chip,
  263. AK4113_REG_RXCSB0 + i);
  264. return 0;
  265. }
  266. static int snd_ak4113_spdif_mask_info(struct snd_kcontrol *kcontrol,
  267. struct snd_ctl_elem_info *uinfo)
  268. {
  269. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  270. uinfo->count = 1;
  271. return 0;
  272. }
  273. static int snd_ak4113_spdif_mask_get(struct snd_kcontrol *kcontrol,
  274. struct snd_ctl_elem_value *ucontrol)
  275. {
  276. memset(ucontrol->value.iec958.status, 0xff, AK4113_REG_RXCSB_SIZE);
  277. return 0;
  278. }
  279. static int snd_ak4113_spdif_pinfo(struct snd_kcontrol *kcontrol,
  280. struct snd_ctl_elem_info *uinfo)
  281. {
  282. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  283. uinfo->value.integer.min = 0;
  284. uinfo->value.integer.max = 0xffff;
  285. uinfo->count = 4;
  286. return 0;
  287. }
  288. static int snd_ak4113_spdif_pget(struct snd_kcontrol *kcontrol,
  289. struct snd_ctl_elem_value *ucontrol)
  290. {
  291. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  292. unsigned short tmp;
  293. ucontrol->value.integer.value[0] = 0xf8f2;
  294. ucontrol->value.integer.value[1] = 0x4e1f;
  295. tmp = reg_read(chip, AK4113_REG_Pc0) |
  296. (reg_read(chip, AK4113_REG_Pc1) << 8);
  297. ucontrol->value.integer.value[2] = tmp;
  298. tmp = reg_read(chip, AK4113_REG_Pd0) |
  299. (reg_read(chip, AK4113_REG_Pd1) << 8);
  300. ucontrol->value.integer.value[3] = tmp;
  301. return 0;
  302. }
  303. static int snd_ak4113_spdif_qinfo(struct snd_kcontrol *kcontrol,
  304. struct snd_ctl_elem_info *uinfo)
  305. {
  306. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  307. uinfo->count = AK4113_REG_QSUB_SIZE;
  308. return 0;
  309. }
  310. static int snd_ak4113_spdif_qget(struct snd_kcontrol *kcontrol,
  311. struct snd_ctl_elem_value *ucontrol)
  312. {
  313. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  314. unsigned i;
  315. for (i = 0; i < AK4113_REG_QSUB_SIZE; i++)
  316. ucontrol->value.bytes.data[i] = reg_read(chip,
  317. AK4113_REG_QSUB_ADDR + i);
  318. return 0;
  319. }
  320. /* Don't forget to change AK4113_CONTROLS define!!! */
  321. static struct snd_kcontrol_new snd_ak4113_iec958_controls[] = {
  322. {
  323. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  324. .name = "IEC958 Parity Errors",
  325. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  326. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  327. .info = snd_ak4113_in_error_info,
  328. .get = snd_ak4113_in_error_get,
  329. .private_value = AK4113_PARITY_ERRORS,
  330. },
  331. {
  332. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  333. .name = "IEC958 V-Bit Errors",
  334. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  335. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  336. .info = snd_ak4113_in_error_info,
  337. .get = snd_ak4113_in_error_get,
  338. .private_value = AK4113_V_BIT_ERRORS,
  339. },
  340. {
  341. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  342. .name = "IEC958 C-CRC Errors",
  343. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  344. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  345. .info = snd_ak4113_in_error_info,
  346. .get = snd_ak4113_in_error_get,
  347. .private_value = AK4113_CCRC_ERRORS,
  348. },
  349. {
  350. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  351. .name = "IEC958 Q-CRC Errors",
  352. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  353. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  354. .info = snd_ak4113_in_error_info,
  355. .get = snd_ak4113_in_error_get,
  356. .private_value = AK4113_QCRC_ERRORS,
  357. },
  358. {
  359. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  360. .name = "IEC958 External Rate",
  361. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  362. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  363. .info = snd_ak4113_rate_info,
  364. .get = snd_ak4113_rate_get,
  365. },
  366. {
  367. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  368. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
  369. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  370. .info = snd_ak4113_spdif_mask_info,
  371. .get = snd_ak4113_spdif_mask_get,
  372. },
  373. {
  374. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  375. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
  376. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  377. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  378. .info = snd_ak4113_spdif_info,
  379. .get = snd_ak4113_spdif_get,
  380. },
  381. {
  382. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  383. .name = "IEC958 Preamble Capture Default",
  384. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  385. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  386. .info = snd_ak4113_spdif_pinfo,
  387. .get = snd_ak4113_spdif_pget,
  388. },
  389. {
  390. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  391. .name = "IEC958 Q-subcode Capture Default",
  392. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  393. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  394. .info = snd_ak4113_spdif_qinfo,
  395. .get = snd_ak4113_spdif_qget,
  396. },
  397. {
  398. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  399. .name = "IEC958 Audio",
  400. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  401. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  402. .info = snd_ak4113_in_bit_info,
  403. .get = snd_ak4113_in_bit_get,
  404. .private_value = (1<<31) | (1<<8) | AK4113_REG_RCS0,
  405. },
  406. {
  407. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  408. .name = "IEC958 Non-PCM Bitstream",
  409. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  410. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  411. .info = snd_ak4113_in_bit_info,
  412. .get = snd_ak4113_in_bit_get,
  413. .private_value = (0<<8) | AK4113_REG_RCS1,
  414. },
  415. {
  416. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  417. .name = "IEC958 DTS Bitstream",
  418. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  419. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  420. .info = snd_ak4113_in_bit_info,
  421. .get = snd_ak4113_in_bit_get,
  422. .private_value = (1<<8) | AK4113_REG_RCS1,
  423. },
  424. {
  425. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  426. .name = "AK4113 Input Select",
  427. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  428. SNDRV_CTL_ELEM_ACCESS_WRITE,
  429. .info = snd_ak4113_rx_info,
  430. .get = snd_ak4113_rx_get,
  431. .put = snd_ak4113_rx_put,
  432. }
  433. };
  434. static void snd_ak4113_proc_regs_read(struct snd_info_entry *entry,
  435. struct snd_info_buffer *buffer)
  436. {
  437. struct ak4113 *ak4113 = entry->private_data;
  438. int reg, val;
  439. /* all ak4113 registers 0x00 - 0x1c */
  440. for (reg = 0; reg < 0x1d; reg++) {
  441. val = reg_read(ak4113, reg);
  442. snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val);
  443. }
  444. }
  445. static void snd_ak4113_proc_init(struct ak4113 *ak4113)
  446. {
  447. struct snd_info_entry *entry;
  448. if (!snd_card_proc_new(ak4113->card, "ak4113", &entry))
  449. snd_info_set_text_ops(entry, ak4113, snd_ak4113_proc_regs_read);
  450. }
  451. int snd_ak4113_build(struct ak4113 *ak4113,
  452. struct snd_pcm_substream *cap_substream)
  453. {
  454. struct snd_kcontrol *kctl;
  455. unsigned int idx;
  456. int err;
  457. if (snd_BUG_ON(!cap_substream))
  458. return -EINVAL;
  459. ak4113->substream = cap_substream;
  460. for (idx = 0; idx < AK4113_CONTROLS; idx++) {
  461. kctl = snd_ctl_new1(&snd_ak4113_iec958_controls[idx], ak4113);
  462. if (kctl == NULL)
  463. return -ENOMEM;
  464. kctl->id.device = cap_substream->pcm->device;
  465. kctl->id.subdevice = cap_substream->number;
  466. err = snd_ctl_add(ak4113->card, kctl);
  467. if (err < 0)
  468. return err;
  469. ak4113->kctls[idx] = kctl;
  470. }
  471. snd_ak4113_proc_init(ak4113);
  472. /* trigger workq */
  473. schedule_delayed_work(&ak4113->work, HZ / 10);
  474. return 0;
  475. }
  476. EXPORT_SYMBOL_GPL(snd_ak4113_build);
  477. int snd_ak4113_external_rate(struct ak4113 *ak4113)
  478. {
  479. unsigned char rcs1;
  480. rcs1 = reg_read(ak4113, AK4113_REG_RCS1);
  481. return external_rate(rcs1);
  482. }
  483. EXPORT_SYMBOL_GPL(snd_ak4113_external_rate);
  484. int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags)
  485. {
  486. struct snd_pcm_runtime *runtime =
  487. ak4113->substream ? ak4113->substream->runtime : NULL;
  488. unsigned long _flags;
  489. int res = 0;
  490. unsigned char rcs0, rcs1, rcs2;
  491. unsigned char c0, c1;
  492. rcs1 = reg_read(ak4113, AK4113_REG_RCS1);
  493. if (flags & AK4113_CHECK_NO_STAT)
  494. goto __rate;
  495. rcs0 = reg_read(ak4113, AK4113_REG_RCS0);
  496. rcs2 = reg_read(ak4113, AK4113_REG_RCS2);
  497. spin_lock_irqsave(&ak4113->lock, _flags);
  498. if (rcs0 & AK4113_PAR)
  499. ak4113->errors[AK4113_PARITY_ERRORS]++;
  500. if (rcs0 & AK4113_V)
  501. ak4113->errors[AK4113_V_BIT_ERRORS]++;
  502. if (rcs2 & AK4113_CCRC)
  503. ak4113->errors[AK4113_CCRC_ERRORS]++;
  504. if (rcs2 & AK4113_QCRC)
  505. ak4113->errors[AK4113_QCRC_ERRORS]++;
  506. c0 = (ak4113->rcs0 & (AK4113_QINT | AK4113_CINT | AK4113_STC |
  507. AK4113_AUDION | AK4113_AUTO | AK4113_UNLCK)) ^
  508. (rcs0 & (AK4113_QINT | AK4113_CINT | AK4113_STC |
  509. AK4113_AUDION | AK4113_AUTO | AK4113_UNLCK));
  510. c1 = (ak4113->rcs1 & (AK4113_DTSCD | AK4113_NPCM | AK4113_PEM |
  511. AK4113_DAT | 0xf0)) ^
  512. (rcs1 & (AK4113_DTSCD | AK4113_NPCM | AK4113_PEM |
  513. AK4113_DAT | 0xf0));
  514. ak4113->rcs0 = rcs0 & ~(AK4113_QINT | AK4113_CINT | AK4113_STC);
  515. ak4113->rcs1 = rcs1;
  516. ak4113->rcs2 = rcs2;
  517. spin_unlock_irqrestore(&ak4113->lock, _flags);
  518. if (rcs0 & AK4113_PAR)
  519. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  520. &ak4113->kctls[0]->id);
  521. if (rcs0 & AK4113_V)
  522. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  523. &ak4113->kctls[1]->id);
  524. if (rcs2 & AK4113_CCRC)
  525. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  526. &ak4113->kctls[2]->id);
  527. if (rcs2 & AK4113_QCRC)
  528. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  529. &ak4113->kctls[3]->id);
  530. /* rate change */
  531. if (c1 & 0xf0)
  532. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  533. &ak4113->kctls[4]->id);
  534. if ((c1 & AK4113_PEM) | (c0 & AK4113_CINT))
  535. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  536. &ak4113->kctls[6]->id);
  537. if (c0 & AK4113_QINT)
  538. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  539. &ak4113->kctls[8]->id);
  540. if (c0 & AK4113_AUDION)
  541. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  542. &ak4113->kctls[9]->id);
  543. if (c1 & AK4113_NPCM)
  544. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  545. &ak4113->kctls[10]->id);
  546. if (c1 & AK4113_DTSCD)
  547. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  548. &ak4113->kctls[11]->id);
  549. if (ak4113->change_callback && (c0 | c1) != 0)
  550. ak4113->change_callback(ak4113, c0, c1);
  551. __rate:
  552. /* compare rate */
  553. res = external_rate(rcs1);
  554. if (!(flags & AK4113_CHECK_NO_RATE) && runtime &&
  555. (runtime->rate != res)) {
  556. snd_pcm_stream_lock_irqsave(ak4113->substream, _flags);
  557. if (snd_pcm_running(ak4113->substream)) {
  558. /*printk(KERN_DEBUG "rate changed (%i <- %i)\n",
  559. * runtime->rate, res); */
  560. snd_pcm_stop(ak4113->substream,
  561. SNDRV_PCM_STATE_DRAINING);
  562. wake_up(&runtime->sleep);
  563. res = 1;
  564. }
  565. snd_pcm_stream_unlock_irqrestore(ak4113->substream, _flags);
  566. }
  567. return res;
  568. }
  569. EXPORT_SYMBOL_GPL(snd_ak4113_check_rate_and_errors);
  570. static void ak4113_stats(struct work_struct *work)
  571. {
  572. struct ak4113 *chip = container_of(work, struct ak4113, work.work);
  573. if (atomic_inc_return(&chip->wq_processing) == 1)
  574. snd_ak4113_check_rate_and_errors(chip, chip->check_flags);
  575. if (atomic_dec_and_test(&chip->wq_processing))
  576. schedule_delayed_work(&chip->work, HZ / 10);
  577. }
  578. #ifdef CONFIG_PM
  579. void snd_ak4113_suspend(struct ak4113 *chip)
  580. {
  581. atomic_inc(&chip->wq_processing); /* don't schedule new work */
  582. cancel_delayed_work_sync(&chip->work);
  583. }
  584. EXPORT_SYMBOL(snd_ak4113_suspend);
  585. void snd_ak4113_resume(struct ak4113 *chip)
  586. {
  587. atomic_dec(&chip->wq_processing);
  588. snd_ak4113_reinit(chip);
  589. }
  590. EXPORT_SYMBOL(snd_ak4113_resume);
  591. #endif