ak4117.c 16 KB

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  1. /*
  2. * Routines for control of the AK4117 via 4-wire serial interface
  3. * IEC958 (S/PDIF) receiver by Asahi Kasei
  4. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  5. *
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. */
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <sound/core.h>
  26. #include <sound/control.h>
  27. #include <sound/pcm.h>
  28. #include <sound/ak4117.h>
  29. #include <sound/asoundef.h>
  30. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  31. MODULE_DESCRIPTION("AK4117 IEC958 (S/PDIF) receiver by Asahi Kasei");
  32. MODULE_LICENSE("GPL");
  33. #define AK4117_ADDR 0x00 /* fixed address */
  34. static void snd_ak4117_timer(struct timer_list *t);
  35. static void reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char val)
  36. {
  37. ak4117->write(ak4117->private_data, reg, val);
  38. if (reg < sizeof(ak4117->regmap))
  39. ak4117->regmap[reg] = val;
  40. }
  41. static inline unsigned char reg_read(struct ak4117 *ak4117, unsigned char reg)
  42. {
  43. return ak4117->read(ak4117->private_data, reg);
  44. }
  45. #if 0
  46. static void reg_dump(struct ak4117 *ak4117)
  47. {
  48. int i;
  49. printk(KERN_DEBUG "AK4117 REG DUMP:\n");
  50. for (i = 0; i < 0x1b; i++)
  51. printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4117, i), i < sizeof(ak4117->regmap) ? ak4117->regmap[i] : 0);
  52. }
  53. #endif
  54. static void snd_ak4117_free(struct ak4117 *chip)
  55. {
  56. del_timer_sync(&chip->timer);
  57. kfree(chip);
  58. }
  59. static int snd_ak4117_dev_free(struct snd_device *device)
  60. {
  61. struct ak4117 *chip = device->device_data;
  62. snd_ak4117_free(chip);
  63. return 0;
  64. }
  65. int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
  66. const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117)
  67. {
  68. struct ak4117 *chip;
  69. int err = 0;
  70. unsigned char reg;
  71. static struct snd_device_ops ops = {
  72. .dev_free = snd_ak4117_dev_free,
  73. };
  74. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  75. if (chip == NULL)
  76. return -ENOMEM;
  77. spin_lock_init(&chip->lock);
  78. chip->card = card;
  79. chip->read = read;
  80. chip->write = write;
  81. chip->private_data = private_data;
  82. timer_setup(&chip->timer, snd_ak4117_timer, 0);
  83. for (reg = 0; reg < 5; reg++)
  84. chip->regmap[reg] = pgm[reg];
  85. snd_ak4117_reinit(chip);
  86. chip->rcs0 = reg_read(chip, AK4117_REG_RCS0) & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
  87. chip->rcs1 = reg_read(chip, AK4117_REG_RCS1);
  88. chip->rcs2 = reg_read(chip, AK4117_REG_RCS2);
  89. if ((err = snd_device_new(card, SNDRV_DEV_CODEC, chip, &ops)) < 0)
  90. goto __fail;
  91. if (r_ak4117)
  92. *r_ak4117 = chip;
  93. return 0;
  94. __fail:
  95. snd_ak4117_free(chip);
  96. return err;
  97. }
  98. void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val)
  99. {
  100. if (reg >= 5)
  101. return;
  102. reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val);
  103. }
  104. void snd_ak4117_reinit(struct ak4117 *chip)
  105. {
  106. unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg;
  107. del_timer(&chip->timer);
  108. chip->init = 1;
  109. /* bring the chip to reset state and powerdown state */
  110. reg_write(chip, AK4117_REG_PWRDN, 0);
  111. udelay(200);
  112. /* release reset, but leave powerdown */
  113. reg_write(chip, AK4117_REG_PWRDN, (old | AK4117_RST) & ~AK4117_PWN);
  114. udelay(200);
  115. for (reg = 1; reg < 5; reg++)
  116. reg_write(chip, reg, chip->regmap[reg]);
  117. /* release powerdown, everything is initialized now */
  118. reg_write(chip, AK4117_REG_PWRDN, old | AK4117_RST | AK4117_PWN);
  119. chip->init = 0;
  120. mod_timer(&chip->timer, 1 + jiffies);
  121. }
  122. static unsigned int external_rate(unsigned char rcs1)
  123. {
  124. switch (rcs1 & (AK4117_FS0|AK4117_FS1|AK4117_FS2|AK4117_FS3)) {
  125. case AK4117_FS_32000HZ: return 32000;
  126. case AK4117_FS_44100HZ: return 44100;
  127. case AK4117_FS_48000HZ: return 48000;
  128. case AK4117_FS_88200HZ: return 88200;
  129. case AK4117_FS_96000HZ: return 96000;
  130. case AK4117_FS_176400HZ: return 176400;
  131. case AK4117_FS_192000HZ: return 192000;
  132. default: return 0;
  133. }
  134. }
  135. static int snd_ak4117_in_error_info(struct snd_kcontrol *kcontrol,
  136. struct snd_ctl_elem_info *uinfo)
  137. {
  138. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  139. uinfo->count = 1;
  140. uinfo->value.integer.min = 0;
  141. uinfo->value.integer.max = LONG_MAX;
  142. return 0;
  143. }
  144. static int snd_ak4117_in_error_get(struct snd_kcontrol *kcontrol,
  145. struct snd_ctl_elem_value *ucontrol)
  146. {
  147. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  148. spin_lock_irq(&chip->lock);
  149. ucontrol->value.integer.value[0] =
  150. chip->errors[kcontrol->private_value];
  151. chip->errors[kcontrol->private_value] = 0;
  152. spin_unlock_irq(&chip->lock);
  153. return 0;
  154. }
  155. #define snd_ak4117_in_bit_info snd_ctl_boolean_mono_info
  156. static int snd_ak4117_in_bit_get(struct snd_kcontrol *kcontrol,
  157. struct snd_ctl_elem_value *ucontrol)
  158. {
  159. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  160. unsigned char reg = kcontrol->private_value & 0xff;
  161. unsigned char bit = (kcontrol->private_value >> 8) & 0xff;
  162. unsigned char inv = (kcontrol->private_value >> 31) & 1;
  163. ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv;
  164. return 0;
  165. }
  166. static int snd_ak4117_rx_info(struct snd_kcontrol *kcontrol,
  167. struct snd_ctl_elem_info *uinfo)
  168. {
  169. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  170. uinfo->count = 1;
  171. uinfo->value.integer.min = 0;
  172. uinfo->value.integer.max = 1;
  173. return 0;
  174. }
  175. static int snd_ak4117_rx_get(struct snd_kcontrol *kcontrol,
  176. struct snd_ctl_elem_value *ucontrol)
  177. {
  178. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  179. ucontrol->value.integer.value[0] = (chip->regmap[AK4117_REG_IO] & AK4117_IPS) ? 1 : 0;
  180. return 0;
  181. }
  182. static int snd_ak4117_rx_put(struct snd_kcontrol *kcontrol,
  183. struct snd_ctl_elem_value *ucontrol)
  184. {
  185. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  186. int change;
  187. u8 old_val;
  188. spin_lock_irq(&chip->lock);
  189. old_val = chip->regmap[AK4117_REG_IO];
  190. change = !!ucontrol->value.integer.value[0] != ((old_val & AK4117_IPS) ? 1 : 0);
  191. if (change)
  192. reg_write(chip, AK4117_REG_IO, (old_val & ~AK4117_IPS) | (ucontrol->value.integer.value[0] ? AK4117_IPS : 0));
  193. spin_unlock_irq(&chip->lock);
  194. return change;
  195. }
  196. static int snd_ak4117_rate_info(struct snd_kcontrol *kcontrol,
  197. struct snd_ctl_elem_info *uinfo)
  198. {
  199. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  200. uinfo->count = 1;
  201. uinfo->value.integer.min = 0;
  202. uinfo->value.integer.max = 192000;
  203. return 0;
  204. }
  205. static int snd_ak4117_rate_get(struct snd_kcontrol *kcontrol,
  206. struct snd_ctl_elem_value *ucontrol)
  207. {
  208. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  209. ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4117_REG_RCS1));
  210. return 0;
  211. }
  212. static int snd_ak4117_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  213. {
  214. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  215. uinfo->count = 1;
  216. return 0;
  217. }
  218. static int snd_ak4117_spdif_get(struct snd_kcontrol *kcontrol,
  219. struct snd_ctl_elem_value *ucontrol)
  220. {
  221. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  222. unsigned i;
  223. for (i = 0; i < AK4117_REG_RXCSB_SIZE; i++)
  224. ucontrol->value.iec958.status[i] = reg_read(chip, AK4117_REG_RXCSB0 + i);
  225. return 0;
  226. }
  227. static int snd_ak4117_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  228. {
  229. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  230. uinfo->count = 1;
  231. return 0;
  232. }
  233. static int snd_ak4117_spdif_mask_get(struct snd_kcontrol *kcontrol,
  234. struct snd_ctl_elem_value *ucontrol)
  235. {
  236. memset(ucontrol->value.iec958.status, 0xff, AK4117_REG_RXCSB_SIZE);
  237. return 0;
  238. }
  239. static int snd_ak4117_spdif_pinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  240. {
  241. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  242. uinfo->value.integer.min = 0;
  243. uinfo->value.integer.max = 0xffff;
  244. uinfo->count = 4;
  245. return 0;
  246. }
  247. static int snd_ak4117_spdif_pget(struct snd_kcontrol *kcontrol,
  248. struct snd_ctl_elem_value *ucontrol)
  249. {
  250. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  251. unsigned short tmp;
  252. ucontrol->value.integer.value[0] = 0xf8f2;
  253. ucontrol->value.integer.value[1] = 0x4e1f;
  254. tmp = reg_read(chip, AK4117_REG_Pc0) | (reg_read(chip, AK4117_REG_Pc1) << 8);
  255. ucontrol->value.integer.value[2] = tmp;
  256. tmp = reg_read(chip, AK4117_REG_Pd0) | (reg_read(chip, AK4117_REG_Pd1) << 8);
  257. ucontrol->value.integer.value[3] = tmp;
  258. return 0;
  259. }
  260. static int snd_ak4117_spdif_qinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  261. {
  262. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  263. uinfo->count = AK4117_REG_QSUB_SIZE;
  264. return 0;
  265. }
  266. static int snd_ak4117_spdif_qget(struct snd_kcontrol *kcontrol,
  267. struct snd_ctl_elem_value *ucontrol)
  268. {
  269. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  270. unsigned i;
  271. for (i = 0; i < AK4117_REG_QSUB_SIZE; i++)
  272. ucontrol->value.bytes.data[i] = reg_read(chip, AK4117_REG_QSUB_ADDR + i);
  273. return 0;
  274. }
  275. /* Don't forget to change AK4117_CONTROLS define!!! */
  276. static struct snd_kcontrol_new snd_ak4117_iec958_controls[] = {
  277. {
  278. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  279. .name = "IEC958 Parity Errors",
  280. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  281. .info = snd_ak4117_in_error_info,
  282. .get = snd_ak4117_in_error_get,
  283. .private_value = AK4117_PARITY_ERRORS,
  284. },
  285. {
  286. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  287. .name = "IEC958 V-Bit Errors",
  288. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  289. .info = snd_ak4117_in_error_info,
  290. .get = snd_ak4117_in_error_get,
  291. .private_value = AK4117_V_BIT_ERRORS,
  292. },
  293. {
  294. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  295. .name = "IEC958 C-CRC Errors",
  296. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  297. .info = snd_ak4117_in_error_info,
  298. .get = snd_ak4117_in_error_get,
  299. .private_value = AK4117_CCRC_ERRORS,
  300. },
  301. {
  302. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  303. .name = "IEC958 Q-CRC Errors",
  304. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  305. .info = snd_ak4117_in_error_info,
  306. .get = snd_ak4117_in_error_get,
  307. .private_value = AK4117_QCRC_ERRORS,
  308. },
  309. {
  310. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  311. .name = "IEC958 External Rate",
  312. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  313. .info = snd_ak4117_rate_info,
  314. .get = snd_ak4117_rate_get,
  315. },
  316. {
  317. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  318. .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK),
  319. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  320. .info = snd_ak4117_spdif_mask_info,
  321. .get = snd_ak4117_spdif_mask_get,
  322. },
  323. {
  324. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  325. .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,DEFAULT),
  326. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  327. .info = snd_ak4117_spdif_info,
  328. .get = snd_ak4117_spdif_get,
  329. },
  330. {
  331. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  332. .name = "IEC958 Preamble Capture Default",
  333. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  334. .info = snd_ak4117_spdif_pinfo,
  335. .get = snd_ak4117_spdif_pget,
  336. },
  337. {
  338. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  339. .name = "IEC958 Q-subcode Capture Default",
  340. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  341. .info = snd_ak4117_spdif_qinfo,
  342. .get = snd_ak4117_spdif_qget,
  343. },
  344. {
  345. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  346. .name = "IEC958 Audio",
  347. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  348. .info = snd_ak4117_in_bit_info,
  349. .get = snd_ak4117_in_bit_get,
  350. .private_value = (1<<31) | (3<<8) | AK4117_REG_RCS0,
  351. },
  352. {
  353. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  354. .name = "IEC958 Non-PCM Bitstream",
  355. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  356. .info = snd_ak4117_in_bit_info,
  357. .get = snd_ak4117_in_bit_get,
  358. .private_value = (5<<8) | AK4117_REG_RCS1,
  359. },
  360. {
  361. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  362. .name = "IEC958 DTS Bitstream",
  363. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  364. .info = snd_ak4117_in_bit_info,
  365. .get = snd_ak4117_in_bit_get,
  366. .private_value = (6<<8) | AK4117_REG_RCS1,
  367. },
  368. {
  369. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  370. .name = "AK4117 Input Select",
  371. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE,
  372. .info = snd_ak4117_rx_info,
  373. .get = snd_ak4117_rx_get,
  374. .put = snd_ak4117_rx_put,
  375. }
  376. };
  377. int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *cap_substream)
  378. {
  379. struct snd_kcontrol *kctl;
  380. unsigned int idx;
  381. int err;
  382. if (snd_BUG_ON(!cap_substream))
  383. return -EINVAL;
  384. ak4117->substream = cap_substream;
  385. for (idx = 0; idx < AK4117_CONTROLS; idx++) {
  386. kctl = snd_ctl_new1(&snd_ak4117_iec958_controls[idx], ak4117);
  387. if (kctl == NULL)
  388. return -ENOMEM;
  389. kctl->id.device = cap_substream->pcm->device;
  390. kctl->id.subdevice = cap_substream->number;
  391. err = snd_ctl_add(ak4117->card, kctl);
  392. if (err < 0)
  393. return err;
  394. ak4117->kctls[idx] = kctl;
  395. }
  396. return 0;
  397. }
  398. int snd_ak4117_external_rate(struct ak4117 *ak4117)
  399. {
  400. unsigned char rcs1;
  401. rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
  402. return external_rate(rcs1);
  403. }
  404. int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags)
  405. {
  406. struct snd_pcm_runtime *runtime = ak4117->substream ? ak4117->substream->runtime : NULL;
  407. unsigned long _flags;
  408. int res = 0;
  409. unsigned char rcs0, rcs1, rcs2;
  410. unsigned char c0, c1;
  411. rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
  412. if (flags & AK4117_CHECK_NO_STAT)
  413. goto __rate;
  414. rcs0 = reg_read(ak4117, AK4117_REG_RCS0);
  415. rcs2 = reg_read(ak4117, AK4117_REG_RCS2);
  416. // printk(KERN_DEBUG "AK IRQ: rcs0 = 0x%x, rcs1 = 0x%x, rcs2 = 0x%x\n", rcs0, rcs1, rcs2);
  417. spin_lock_irqsave(&ak4117->lock, _flags);
  418. if (rcs0 & AK4117_PAR)
  419. ak4117->errors[AK4117_PARITY_ERRORS]++;
  420. if (rcs0 & AK4117_V)
  421. ak4117->errors[AK4117_V_BIT_ERRORS]++;
  422. if (rcs2 & AK4117_CCRC)
  423. ak4117->errors[AK4117_CCRC_ERRORS]++;
  424. if (rcs2 & AK4117_QCRC)
  425. ak4117->errors[AK4117_QCRC_ERRORS]++;
  426. c0 = (ak4117->rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK)) ^
  427. (rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK));
  428. c1 = (ak4117->rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f)) ^
  429. (rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f));
  430. ak4117->rcs0 = rcs0 & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
  431. ak4117->rcs1 = rcs1;
  432. ak4117->rcs2 = rcs2;
  433. spin_unlock_irqrestore(&ak4117->lock, _flags);
  434. if (rcs0 & AK4117_PAR)
  435. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[0]->id);
  436. if (rcs0 & AK4117_V)
  437. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[1]->id);
  438. if (rcs2 & AK4117_CCRC)
  439. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[2]->id);
  440. if (rcs2 & AK4117_QCRC)
  441. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[3]->id);
  442. /* rate change */
  443. if (c1 & 0x0f)
  444. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[4]->id);
  445. if ((c1 & AK4117_PEM) | (c0 & AK4117_CINT))
  446. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[6]->id);
  447. if (c0 & AK4117_QINT)
  448. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[8]->id);
  449. if (c0 & AK4117_AUDION)
  450. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[9]->id);
  451. if (c1 & AK4117_NPCM)
  452. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[10]->id);
  453. if (c1 & AK4117_DTSCD)
  454. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[11]->id);
  455. if (ak4117->change_callback && (c0 | c1) != 0)
  456. ak4117->change_callback(ak4117, c0, c1);
  457. __rate:
  458. /* compare rate */
  459. res = external_rate(rcs1);
  460. if (!(flags & AK4117_CHECK_NO_RATE) && runtime && runtime->rate != res) {
  461. snd_pcm_stream_lock_irqsave(ak4117->substream, _flags);
  462. if (snd_pcm_running(ak4117->substream)) {
  463. // printk(KERN_DEBUG "rate changed (%i <- %i)\n", runtime->rate, res);
  464. snd_pcm_stop(ak4117->substream, SNDRV_PCM_STATE_DRAINING);
  465. wake_up(&runtime->sleep);
  466. res = 1;
  467. }
  468. snd_pcm_stream_unlock_irqrestore(ak4117->substream, _flags);
  469. }
  470. return res;
  471. }
  472. static void snd_ak4117_timer(struct timer_list *t)
  473. {
  474. struct ak4117 *chip = from_timer(chip, t, timer);
  475. if (chip->init)
  476. return;
  477. snd_ak4117_check_rate_and_errors(chip, 0);
  478. mod_timer(&chip->timer, 1 + jiffies);
  479. }
  480. EXPORT_SYMBOL(snd_ak4117_create);
  481. EXPORT_SYMBOL(snd_ak4117_reg_write);
  482. EXPORT_SYMBOL(snd_ak4117_reinit);
  483. EXPORT_SYMBOL(snd_ak4117_build);
  484. EXPORT_SYMBOL(snd_ak4117_external_rate);
  485. EXPORT_SYMBOL(snd_ak4117_check_rate_and_errors);