slicetimer.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. #include <common.h>
  7. #include <asm/timer.h>
  8. #include <asm/immap.h>
  9. #include <asm/io.h>
  10. DECLARE_GLOBAL_DATA_PTR;
  11. static ulong timestamp;
  12. #if defined(CONFIG_SLTTMR)
  13. #ifndef CONFIG_SYS_UDELAY_BASE
  14. # error "uDelay base not defined!"
  15. #endif
  16. #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
  17. # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
  18. #endif
  19. extern void dtimer_intr_setup(void);
  20. void __udelay(unsigned long usec)
  21. {
  22. slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
  23. u32 now, freq;
  24. /* 1 us period */
  25. freq = CONFIG_SYS_TIMER_PRESCALER;
  26. /* Disable */
  27. out_be32(&timerp->cr, 0);
  28. out_be32(&timerp->tcnt, usec * freq);
  29. out_be32(&timerp->cr, SLT_CR_TEN);
  30. now = in_be32(&timerp->cnt);
  31. while (now != 0)
  32. now = in_be32(&timerp->cnt);
  33. setbits_be32(&timerp->sr, SLT_SR_ST);
  34. out_be32(&timerp->cr, 0);
  35. }
  36. void dtimer_interrupt(void *not_used)
  37. {
  38. slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
  39. /* check for timer interrupt asserted */
  40. if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
  41. setbits_be32(&timerp->sr, SLT_SR_ST);
  42. timestamp++;
  43. return;
  44. }
  45. }
  46. int timer_init(void)
  47. {
  48. slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
  49. timestamp = 0;
  50. /* disable timer */
  51. out_be32(&timerp->cr, 0);
  52. out_be32(&timerp->tcnt, 0);
  53. /* clear status */
  54. out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
  55. /* initialize and enable timer interrupt */
  56. irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
  57. /* Interrupt every ms */
  58. out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
  59. dtimer_intr_setup();
  60. /* set a period of 1us, set timer mode to restart and
  61. enable timer and interrupt */
  62. out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
  63. return 0;
  64. }
  65. ulong get_timer(ulong base)
  66. {
  67. return (timestamp - base);
  68. }
  69. #endif /* CONFIG_SLTTMR */