brcm,bcm6318.dtsi 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  4. */
  5. #include <dt-bindings/clock/bcm6318-clock.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/power-domain/bcm6318-power-domain.h>
  8. #include <dt-bindings/reset/bcm6318-reset.h>
  9. #include "skeleton.dtsi"
  10. / {
  11. compatible = "brcm,bcm6318";
  12. aliases {
  13. spi0 = &spi;
  14. };
  15. cpus {
  16. reg = <0x10000000 0x4>;
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. u-boot,dm-pre-reloc;
  20. cpu@0 {
  21. compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
  22. device_type = "cpu";
  23. reg = <0>;
  24. u-boot,dm-pre-reloc;
  25. };
  26. };
  27. clocks {
  28. compatible = "simple-bus";
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. u-boot,dm-pre-reloc;
  32. hsspi_pll: hsspi-pll {
  33. compatible = "fixed-clock";
  34. #clock-cells = <0>;
  35. clock-frequency = <250000000>;
  36. };
  37. periph_osc: periph-osc {
  38. compatible = "fixed-clock";
  39. #clock-cells = <0>;
  40. clock-frequency = <50000000>;
  41. u-boot,dm-pre-reloc;
  42. };
  43. periph_clk: periph-clk {
  44. compatible = "brcm,bcm6345-clk";
  45. reg = <0x10000004 0x4>;
  46. #clock-cells = <1>;
  47. };
  48. };
  49. ubus {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. u-boot,dm-pre-reloc;
  54. periph_rst: reset-controller@10000010 {
  55. compatible = "brcm,bcm6345-reset";
  56. reg = <0x10000010 0x4>;
  57. #reset-cells = <1>;
  58. };
  59. wdt: watchdog@10000068 {
  60. compatible = "brcm,bcm6345-wdt";
  61. reg = <0x10000068 0xc>;
  62. clocks = <&periph_osc>;
  63. };
  64. wdt-reboot {
  65. compatible = "wdt-reboot";
  66. wdt = <&wdt>;
  67. };
  68. pll_cntl: syscon@10000074 {
  69. compatible = "syscon";
  70. reg = <0x10000074 0x4>;
  71. };
  72. syscon-reboot {
  73. compatible = "syscon-reboot";
  74. regmap = <&pll_cntl>;
  75. offset = <0x0>;
  76. mask = <0x1>;
  77. };
  78. gpio1: gpio-controller@10000080 {
  79. compatible = "brcm,bcm6345-gpio";
  80. reg = <0x10000080 0x4>, <0x10000088 0x4>;
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. ngpios = <18>;
  84. status = "disabled";
  85. };
  86. gpio0: gpio-controller@10000084 {
  87. compatible = "brcm,bcm6345-gpio";
  88. reg = <0x10000084 0x4>, <0x1000008c 0x4>;
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. status = "disabled";
  92. };
  93. uart0: serial@10000100 {
  94. compatible = "brcm,bcm6345-uart";
  95. reg = <0x10000100 0x18>;
  96. clocks = <&periph_osc>;
  97. status = "disabled";
  98. };
  99. leds: led-controller@10000200 {
  100. compatible = "brcm,bcm6328-leds";
  101. reg = <0x10000200 0x28>;
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. status = "disabled";
  105. };
  106. periph_pwr: power-controller@100008e8 {
  107. compatible = "brcm,bcm6328-power-domain";
  108. reg = <0x100008e8 0x4>;
  109. #power-domain-cells = <1>;
  110. };
  111. spi: spi@10003000 {
  112. compatible = "brcm,bcm6328-hsspi";
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. reg = <0x10003000 0x600>;
  116. clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
  117. clock-names = "hsspi", "pll";
  118. resets = <&periph_rst BCM6318_RST_SPI>;
  119. spi-max-frequency = <33333334>;
  120. num-cs = <3>;
  121. status = "disabled";
  122. };
  123. memory-controller@10004000 {
  124. compatible = "brcm,bcm6318-mc";
  125. reg = <0x10004000 0x38>;
  126. u-boot,dm-pre-reloc;
  127. };
  128. ehci: usb-controller@10005000 {
  129. compatible = "brcm,bcm6318-ehci", "generic-ehci";
  130. reg = <0x10005000 0x100>;
  131. phys = <&usbh>;
  132. big-endian;
  133. status = "disabled";
  134. };
  135. ohci: usb-controller@10005100 {
  136. compatible = "brcm,bcm6318-ohci", "generic-ohci";
  137. reg = <0x10005100 0x100>;
  138. phys = <&usbh>;
  139. big-endian;
  140. status = "disabled";
  141. };
  142. usbh: usb-phy@10005200 {
  143. compatible = "brcm,bcm6318-usbh";
  144. reg = <0x10005200 0x30>;
  145. #phy-cells = <0>;
  146. clocks = <&periph_clk BCM6318_CLK_USB>;
  147. clock-names = "usbh";
  148. power-domains = <&periph_pwr BCM6318_PWR_USB>;
  149. resets = <&periph_rst BCM6318_RST_USBH>;
  150. status = "disabled";
  151. };
  152. };
  153. };