mx31pdk.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
  5. *
  6. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. */
  8. #include <common.h>
  9. #include <netdev.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <watchdog.h>
  14. #include <power/pmic.h>
  15. #include <fsl_pmic.h>
  16. #include <errno.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #ifdef CONFIG_SPL_BUILD
  19. void board_init_f(ulong bootflag)
  20. {
  21. /*
  22. * copy ourselves from where we are running to where we were
  23. * linked at. Use ulong pointers as all addresses involved
  24. * are 4-byte-aligned.
  25. */
  26. ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
  27. asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
  28. asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
  29. asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
  30. asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
  31. for (dst = start_ptr; dst < end_ptr; dst++)
  32. *dst = *(dst+(run_ptr-link_ptr));
  33. /*
  34. * branch to nand_boot's link-time address.
  35. */
  36. asm volatile("ldr pc, =nand_boot");
  37. }
  38. #endif
  39. int dram_init(void)
  40. {
  41. /* dram_init must store complete ramsize in gd->ram_size */
  42. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  43. PHYS_SDRAM_1_SIZE);
  44. return 0;
  45. }
  46. int board_early_init_f(void)
  47. {
  48. /* CS5: CPLD incl. network controller */
  49. static const struct mxc_weimcs cs5 = {
  50. /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  51. CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
  52. /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  53. CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
  54. /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  55. CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
  56. };
  57. mxc_setup_weimcs(5, &cs5);
  58. /* Setup UART1 and SPI2 pins */
  59. mx31_uart1_hw_init();
  60. mx31_spi2_hw_init();
  61. return 0;
  62. }
  63. int board_init(void)
  64. {
  65. /* adress of boot parameters */
  66. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  67. return 0;
  68. }
  69. int board_late_init(void)
  70. {
  71. u32 val;
  72. struct pmic *p;
  73. int ret;
  74. ret = pmic_init(CONFIG_FSL_PMIC_BUS);
  75. if (ret)
  76. return ret;
  77. p = pmic_get("FSL_PMIC");
  78. if (!p)
  79. return -ENODEV;
  80. /* Enable RTC battery */
  81. pmic_reg_read(p, REG_POWER_CTL0, &val);
  82. pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
  83. pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
  84. #ifdef CONFIG_HW_WATCHDOG
  85. hw_watchdog_init();
  86. #endif
  87. return 0;
  88. }
  89. int checkboard(void)
  90. {
  91. printf("Board: MX31PDK\n");
  92. return 0;
  93. }
  94. int board_eth_init(bd_t *bis)
  95. {
  96. int rc = 0;
  97. #ifdef CONFIG_SMC911X
  98. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  99. #endif
  100. return rc;
  101. }