sleep.S 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Exynos low-level resume code
  7. */
  8. #include <linux/linkage.h>
  9. #include <asm/asm-offsets.h>
  10. #include <asm/hardware/cache-l2x0.h>
  11. #include "smc.h"
  12. #define CPU_MASK 0xff0ffff0
  13. #define CPU_CORTEX_A9 0x410fc090
  14. .text
  15. .align
  16. /*
  17. * sleep magic, to allow the bootloader to check for an valid
  18. * image to resume to. Must be the first word before the
  19. * exynos_cpu_resume entry.
  20. */
  21. .word 0x2bedf00d
  22. /*
  23. * exynos_cpu_resume
  24. *
  25. * resume code entry for bootloader to call
  26. */
  27. ENTRY(exynos_cpu_resume)
  28. #ifdef CONFIG_CACHE_L2X0
  29. mrc p15, 0, r0, c0, c0, 0
  30. ldr r1, =CPU_MASK
  31. and r0, r0, r1
  32. ldr r1, =CPU_CORTEX_A9
  33. cmp r0, r1
  34. bleq l2c310_early_resume
  35. #endif
  36. b cpu_resume
  37. ENDPROC(exynos_cpu_resume)
  38. .align
  39. ENTRY(exynos_cpu_resume_ns)
  40. mrc p15, 0, r0, c0, c0, 0
  41. ldr r1, =CPU_MASK
  42. and r0, r0, r1
  43. ldr r1, =CPU_CORTEX_A9
  44. cmp r0, r1
  45. bne skip_cp15
  46. adr r0, _cp15_save_power
  47. ldr r1, [r0]
  48. ldr r1, [r0, r1]
  49. adr r0, _cp15_save_diag
  50. ldr r2, [r0]
  51. ldr r2, [r0, r2]
  52. mov r0, #SMC_CMD_C15RESUME
  53. dsb
  54. smc #0
  55. #ifdef CONFIG_CACHE_L2X0
  56. adr r0, 1f
  57. ldr r2, [r0]
  58. add r0, r2, r0
  59. /* Check that the address has been initialised. */
  60. ldr r1, [r0, #L2X0_R_PHY_BASE]
  61. teq r1, #0
  62. beq skip_l2x0
  63. /* Check if controller has been enabled. */
  64. ldr r2, [r1, #L2X0_CTRL]
  65. tst r2, #0x1
  66. bne skip_l2x0
  67. ldr r1, [r0, #L2X0_R_TAG_LATENCY]
  68. ldr r2, [r0, #L2X0_R_DATA_LATENCY]
  69. ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
  70. mov r0, #SMC_CMD_L2X0SETUP1
  71. smc #0
  72. /* Reload saved regs pointer because smc corrupts registers. */
  73. adr r0, 1f
  74. ldr r2, [r0]
  75. add r0, r2, r0
  76. ldr r1, [r0, #L2X0_R_PWR_CTRL]
  77. ldr r2, [r0, #L2X0_R_AUX_CTRL]
  78. mov r0, #SMC_CMD_L2X0SETUP2
  79. smc #0
  80. mov r0, #SMC_CMD_L2X0INVALL
  81. smc #0
  82. mov r1, #1
  83. mov r0, #SMC_CMD_L2X0CTRL
  84. smc #0
  85. skip_l2x0:
  86. #endif /* CONFIG_CACHE_L2X0 */
  87. skip_cp15:
  88. b cpu_resume
  89. ENDPROC(exynos_cpu_resume_ns)
  90. .align
  91. _cp15_save_power:
  92. .long cp15_save_power - .
  93. _cp15_save_diag:
  94. .long cp15_save_diag - .
  95. #ifdef CONFIG_CACHE_L2X0
  96. 1: .long l2x0_saved_regs - .
  97. #endif /* CONFIG_CACHE_L2X0 */
  98. .data
  99. .align 2
  100. .globl cp15_save_diag
  101. cp15_save_diag:
  102. .long 0 @ cp15 diagnostic
  103. .globl cp15_save_power
  104. cp15_save_power:
  105. .long 0 @ cp15 power control