gpio-htc-egpio.c 10 KB

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  1. /*
  2. * Support for the GPIO/IRQ expander chips present on several HTC phones.
  3. * These are implemented in CPLD chips present on the board.
  4. *
  5. * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
  6. * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
  7. *
  8. * This file may be distributed under the terms of the GNU GPL license.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/errno.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/io.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/platform_data/gpio-htc-egpio.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #include <linux/init.h>
  20. #include <linux/gpio/driver.h>
  21. struct egpio_chip {
  22. int reg_start;
  23. int cached_values;
  24. unsigned long is_out;
  25. struct device *dev;
  26. struct gpio_chip chip;
  27. };
  28. struct egpio_info {
  29. spinlock_t lock;
  30. /* iomem info */
  31. void __iomem *base_addr;
  32. int bus_shift; /* byte shift */
  33. int reg_shift; /* bit shift */
  34. int reg_mask;
  35. /* irq info */
  36. int ack_register;
  37. int ack_write;
  38. u16 irqs_enabled;
  39. uint irq_start;
  40. int nirqs;
  41. uint chained_irq;
  42. /* egpio info */
  43. struct egpio_chip *chip;
  44. int nchips;
  45. };
  46. static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
  47. {
  48. writew(value, ei->base_addr + (reg << ei->bus_shift));
  49. }
  50. static inline u16 egpio_readw(struct egpio_info *ei, int reg)
  51. {
  52. return readw(ei->base_addr + (reg << ei->bus_shift));
  53. }
  54. /*
  55. * IRQs
  56. */
  57. static inline void ack_irqs(struct egpio_info *ei)
  58. {
  59. egpio_writew(ei->ack_write, ei, ei->ack_register);
  60. pr_debug("EGPIO ack - write %x to base+%x\n",
  61. ei->ack_write, ei->ack_register << ei->bus_shift);
  62. }
  63. static void egpio_ack(struct irq_data *data)
  64. {
  65. }
  66. /* There does not appear to be a way to proactively mask interrupts
  67. * on the egpio chip itself. So, we simply ignore interrupts that
  68. * aren't desired. */
  69. static void egpio_mask(struct irq_data *data)
  70. {
  71. struct egpio_info *ei = irq_data_get_irq_chip_data(data);
  72. ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
  73. pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
  74. }
  75. static void egpio_unmask(struct irq_data *data)
  76. {
  77. struct egpio_info *ei = irq_data_get_irq_chip_data(data);
  78. ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
  79. pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
  80. }
  81. static struct irq_chip egpio_muxed_chip = {
  82. .name = "htc-egpio",
  83. .irq_ack = egpio_ack,
  84. .irq_mask = egpio_mask,
  85. .irq_unmask = egpio_unmask,
  86. };
  87. static void egpio_handler(struct irq_desc *desc)
  88. {
  89. struct egpio_info *ei = irq_desc_get_handler_data(desc);
  90. int irqpin;
  91. /* Read current pins. */
  92. unsigned long readval = egpio_readw(ei, ei->ack_register);
  93. pr_debug("IRQ reg: %x\n", (unsigned int)readval);
  94. /* Ack/unmask interrupts. */
  95. ack_irqs(ei);
  96. /* Process all set pins. */
  97. readval &= ei->irqs_enabled;
  98. for_each_set_bit(irqpin, &readval, ei->nirqs) {
  99. /* Run irq handler */
  100. pr_debug("got IRQ %d\n", irqpin);
  101. generic_handle_irq(ei->irq_start + irqpin);
  102. }
  103. }
  104. int htc_egpio_get_wakeup_irq(struct device *dev)
  105. {
  106. struct egpio_info *ei = dev_get_drvdata(dev);
  107. /* Read current pins. */
  108. u16 readval = egpio_readw(ei, ei->ack_register);
  109. /* Ack/unmask interrupts. */
  110. ack_irqs(ei);
  111. /* Return first set pin. */
  112. readval &= ei->irqs_enabled;
  113. return ei->irq_start + ffs(readval) - 1;
  114. }
  115. EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
  116. static inline int egpio_pos(struct egpio_info *ei, int bit)
  117. {
  118. return bit >> ei->reg_shift;
  119. }
  120. static inline int egpio_bit(struct egpio_info *ei, int bit)
  121. {
  122. return 1 << (bit & ((1 << ei->reg_shift)-1));
  123. }
  124. /*
  125. * Input pins
  126. */
  127. static int egpio_get(struct gpio_chip *chip, unsigned offset)
  128. {
  129. struct egpio_chip *egpio;
  130. struct egpio_info *ei;
  131. unsigned bit;
  132. int reg;
  133. int value;
  134. pr_debug("egpio_get_value(%d)\n", chip->base + offset);
  135. egpio = gpiochip_get_data(chip);
  136. ei = dev_get_drvdata(egpio->dev);
  137. bit = egpio_bit(ei, offset);
  138. reg = egpio->reg_start + egpio_pos(ei, offset);
  139. if (test_bit(offset, &egpio->is_out)) {
  140. return !!(egpio->cached_values & (1 << offset));
  141. } else {
  142. value = egpio_readw(ei, reg);
  143. pr_debug("readw(%p + %x) = %x\n",
  144. ei->base_addr, reg << ei->bus_shift, value);
  145. return !!(value & bit);
  146. }
  147. }
  148. static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
  149. {
  150. struct egpio_chip *egpio;
  151. egpio = gpiochip_get_data(chip);
  152. return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
  153. }
  154. /*
  155. * Output pins
  156. */
  157. static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
  158. {
  159. unsigned long flag;
  160. struct egpio_chip *egpio;
  161. struct egpio_info *ei;
  162. unsigned bit;
  163. int pos;
  164. int reg;
  165. int shift;
  166. pr_debug("egpio_set(%s, %d(%d), %d)\n",
  167. chip->label, offset, offset+chip->base, value);
  168. egpio = gpiochip_get_data(chip);
  169. ei = dev_get_drvdata(egpio->dev);
  170. bit = egpio_bit(ei, offset);
  171. pos = egpio_pos(ei, offset);
  172. reg = egpio->reg_start + pos;
  173. shift = pos << ei->reg_shift;
  174. pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
  175. reg, (egpio->cached_values >> shift) & ei->reg_mask);
  176. spin_lock_irqsave(&ei->lock, flag);
  177. if (value)
  178. egpio->cached_values |= (1 << offset);
  179. else
  180. egpio->cached_values &= ~(1 << offset);
  181. egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
  182. spin_unlock_irqrestore(&ei->lock, flag);
  183. }
  184. static int egpio_direction_output(struct gpio_chip *chip,
  185. unsigned offset, int value)
  186. {
  187. struct egpio_chip *egpio;
  188. egpio = gpiochip_get_data(chip);
  189. if (test_bit(offset, &egpio->is_out)) {
  190. egpio_set(chip, offset, value);
  191. return 0;
  192. } else {
  193. return -EINVAL;
  194. }
  195. }
  196. static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
  197. {
  198. struct egpio_chip *egpio;
  199. egpio = gpiochip_get_data(chip);
  200. return !test_bit(offset, &egpio->is_out);
  201. }
  202. static void egpio_write_cache(struct egpio_info *ei)
  203. {
  204. int i;
  205. struct egpio_chip *egpio;
  206. int shift;
  207. for (i = 0; i < ei->nchips; i++) {
  208. egpio = &(ei->chip[i]);
  209. if (!egpio->is_out)
  210. continue;
  211. for (shift = 0; shift < egpio->chip.ngpio;
  212. shift += (1<<ei->reg_shift)) {
  213. int reg = egpio->reg_start + egpio_pos(ei, shift);
  214. if (!((egpio->is_out >> shift) & ei->reg_mask))
  215. continue;
  216. pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
  217. (egpio->cached_values >> shift) & ei->reg_mask,
  218. egpio_readw(ei, reg));
  219. egpio_writew((egpio->cached_values >> shift)
  220. & ei->reg_mask, ei, reg);
  221. }
  222. }
  223. }
  224. /*
  225. * Setup
  226. */
  227. static int __init egpio_probe(struct platform_device *pdev)
  228. {
  229. struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
  230. struct resource *res;
  231. struct egpio_info *ei;
  232. struct gpio_chip *chip;
  233. unsigned int irq, irq_end;
  234. int i;
  235. int ret;
  236. /* Initialize ei data structure. */
  237. ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
  238. if (!ei)
  239. return -ENOMEM;
  240. spin_lock_init(&ei->lock);
  241. /* Find chained irq */
  242. ret = -EINVAL;
  243. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  244. if (res)
  245. ei->chained_irq = res->start;
  246. /* Map egpio chip into virtual address space. */
  247. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  248. if (!res)
  249. goto fail;
  250. ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start,
  251. resource_size(res));
  252. if (!ei->base_addr)
  253. goto fail;
  254. pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);
  255. if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
  256. goto fail;
  257. ei->bus_shift = fls(pdata->bus_width - 1) - 3;
  258. pr_debug("bus_shift = %d\n", ei->bus_shift);
  259. if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
  260. goto fail;
  261. ei->reg_shift = fls(pdata->reg_width - 1);
  262. pr_debug("reg_shift = %d\n", ei->reg_shift);
  263. ei->reg_mask = (1 << pdata->reg_width) - 1;
  264. platform_set_drvdata(pdev, ei);
  265. ei->nchips = pdata->num_chips;
  266. ei->chip = devm_kcalloc(&pdev->dev,
  267. ei->nchips, sizeof(struct egpio_chip),
  268. GFP_KERNEL);
  269. if (!ei->chip) {
  270. ret = -ENOMEM;
  271. goto fail;
  272. }
  273. for (i = 0; i < ei->nchips; i++) {
  274. ei->chip[i].reg_start = pdata->chip[i].reg_start;
  275. ei->chip[i].cached_values = pdata->chip[i].initial_values;
  276. ei->chip[i].is_out = pdata->chip[i].direction;
  277. ei->chip[i].dev = &(pdev->dev);
  278. chip = &(ei->chip[i].chip);
  279. chip->label = "htc-egpio";
  280. chip->parent = &pdev->dev;
  281. chip->owner = THIS_MODULE;
  282. chip->get = egpio_get;
  283. chip->set = egpio_set;
  284. chip->direction_input = egpio_direction_input;
  285. chip->direction_output = egpio_direction_output;
  286. chip->get_direction = egpio_get_direction;
  287. chip->base = pdata->chip[i].gpio_base;
  288. chip->ngpio = pdata->chip[i].num_gpios;
  289. gpiochip_add_data(chip, &ei->chip[i]);
  290. }
  291. /* Set initial pin values */
  292. egpio_write_cache(ei);
  293. ei->irq_start = pdata->irq_base;
  294. ei->nirqs = pdata->num_irqs;
  295. ei->ack_register = pdata->ack_register;
  296. if (ei->chained_irq) {
  297. /* Setup irq handlers */
  298. ei->ack_write = 0xFFFF;
  299. if (pdata->invert_acks)
  300. ei->ack_write = 0;
  301. irq_end = ei->irq_start + ei->nirqs;
  302. for (irq = ei->irq_start; irq < irq_end; irq++) {
  303. irq_set_chip_and_handler(irq, &egpio_muxed_chip,
  304. handle_simple_irq);
  305. irq_set_chip_data(irq, ei);
  306. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  307. }
  308. irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
  309. irq_set_chained_handler_and_data(ei->chained_irq,
  310. egpio_handler, ei);
  311. ack_irqs(ei);
  312. device_init_wakeup(&pdev->dev, 1);
  313. }
  314. return 0;
  315. fail:
  316. printk(KERN_ERR "EGPIO failed to setup\n");
  317. return ret;
  318. }
  319. #ifdef CONFIG_PM
  320. static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
  321. {
  322. struct egpio_info *ei = platform_get_drvdata(pdev);
  323. if (ei->chained_irq && device_may_wakeup(&pdev->dev))
  324. enable_irq_wake(ei->chained_irq);
  325. return 0;
  326. }
  327. static int egpio_resume(struct platform_device *pdev)
  328. {
  329. struct egpio_info *ei = platform_get_drvdata(pdev);
  330. if (ei->chained_irq && device_may_wakeup(&pdev->dev))
  331. disable_irq_wake(ei->chained_irq);
  332. /* Update registers from the cache, in case
  333. the CPLD was powered off during suspend */
  334. egpio_write_cache(ei);
  335. return 0;
  336. }
  337. #else
  338. #define egpio_suspend NULL
  339. #define egpio_resume NULL
  340. #endif
  341. static struct platform_driver egpio_driver = {
  342. .driver = {
  343. .name = "htc-egpio",
  344. .suppress_bind_attrs = true,
  345. },
  346. .suspend = egpio_suspend,
  347. .resume = egpio_resume,
  348. };
  349. static int __init egpio_init(void)
  350. {
  351. return platform_driver_probe(&egpio_driver, egpio_probe);
  352. }
  353. /* start early for dependencies */
  354. subsys_initcall(egpio_init);